电子束纳米光刻技术研究

纳米光刻技术在微电子制作中起着关键作用 ,而电子束光刻在纳米光刻技术制作中是最好的方法之一。我们使用VB5电子束曝光系统 ,经过工艺研究 ,现已研究出最细分辨率剥离金属条为 17nm ,最小剥离电极间距为 10nm ,最细T型栅为 10 0nm。     

电子束纳米光刻技术研究

纳米光刻技术在微电子制作中起着关键作用,而电子束光刻在纳米光刻技术制作中是最好的方法之一.我们使用VB5电子束曝光系统,经过工艺研究,现已研究出最细分辨率剥离金属条为17nm,最小剥离电极间距为10nm,最细T型栅为100nm.     

高能电子束纳米曝光系统的研制

微电子产业的飞速发展要求半导体器件的最小特征尺寸越来越小。传统的光学光刻技术由于受到光的衍射等限制，开始面临挑战。电子束曝光技术具有高分辨、长焦深、无需掩模等优点，成为下一代光刻技术中极具发展潜力的一种。     

基于电子束光刻的LIGA技术研究

提出了基于电子束的LIGA(Lithographie，Galvanoformung，Abformung)技术新概念。根据Grune公式就电子束能量对抗蚀剂刻蚀深度的影响进行了理论分析，并在SDS—2电子束曝光机上分别采用5keV、10keV、15keV、20keV、25keV、30keV等能量的电子束对国产胶苏州2号进行了曝光实验，得出了能量／刻蚀深度关系曲线。用5keV、30keV两种能量的电子束，通过改变曝光时间进行了曝光剂量对刻蚀深度的影响实验，得出了曝光剂量—刻蚀深度关系曲线。实验结果表明，增大电子束能量或增强曝光剂量，就可以增大刻蚀深度，证明了基于电子束光刻的LIGA技术不但是可行的，而且更易于加工各种带曲率的微器件。     

美国MIT研究结果显示电子束光刻可以到达9纳米的精度

美国麻省理工学院(MIT)的研究人员日前发表的一项研究成果显示,电子束光刻精度可以小到9纳米的范围,刷新了以前一项精度为25纳米的结果,这一进展有可能为电子束光刻和EUV(超紫外)光刻技术展开竞争提供了动力。     

电子束三维光刻技术的研究

在IH(Integrated Harden Polymer Stereo Lithography)技术和电子束光刻技术的基础上提出了电子束微三维光刻技术新概念。对其实现方法的可行性进行了简要的理论分析，并使用SDV—Ⅱ型真空腔在约1．33Pa的真空下对环氧618、WSJ-202和苏州2号抗蚀剂进行了气化试验，得出了它们在真空中的气化实验结果，证明了电子束液态光刻的可行性。     

ASML推出新款光刻系统成就两次图形曝光技术

据Semiconductor Reporter报道，ASML Holding NV日前在日本推出了新的193nM光刻系统Twinscan[第一段]     

纳米压印光刻技术

为了避免纳米压印光刻技术与光刻技术混淆，纳米压印光刻技术严谨的专业术语定义是：不使用光线或者辐射使光刻胶感光成形，而是直接在硅衬底或者其他衬底上利用物理学机理构造纳米级别的图形。这种纳米成像技术真正地实现了纳米级别的图形印制。     

富勒烯作为电子束抗蚀剂在纳米光刻中的应用

纳米光刻对于纳米电子学的研究与发展具有非常重要的意义。分子尺寸为０．７纳米且可发生电子束诱导聚合的富勒烯（主要是Ｃ６０）,可以作为电子束抗蚀剂,用于电子束纳米光刻,制作纳米级精细图形。这类抗蚀剂主要有三种类型：纯Ｃ６０、、Ｃ６０衍生物及Ｃ６０与常用抗旬剂形成的纳米复合抗旬剂。介绍了这方面工作的研究现状、存在的问题及发展前景。     

A fully scaled submicrometer NMOS technology using direct-write E-beam lithography

Fully scaled NMOS devices, circuits, and dynamic memory with 1/2-µm nominal minimum dimensions at each level have been fabricated using direct-write e-beam patterning. This high-density NMOS technology yields nominally loaded average gate delays of 650 ps/stage with a power dissipation of 38 µW. The characteristics of this technology are presented with specific emphasis placed on features of the design which are unique to submicrometer MOSFET's, including a study of nonscaling effects and their impact on the device and circuit design.     

Efficient E-beam excitation of XeCl

Efficient laser output at 308 nm has been obtained from XeCl in an Ne/Xe/HCl mixture at a pressure of 4 atm bye-beam excitation and bye-beam controlled discharge pumping. Maximum energy extraction is 7 J/1 fore-beam excitation and 9 J/1 for thee-beam controlled discharge. Efficiencies based on total energy deposited in the gas are approximately 4 percent. Similar results were obtained with KrF in the same device, indicating that undere-beam ore-beam controlled discharge excitation, XeCl may be as efficient as KrF.     

原子纳米光刻中双层光学掩膜的实现方法研究

利用原子光刻的方法制备纳米结构的光栅已经成为了一种较为成熟的工艺。通过原子与激光驻波场的相互作用,利用原子自生在势能场中的偶极力对原子的密度进行调制,从而得到所需要的光栅结构。利用此种工艺所制备的光栅相对于传统工艺来说具有精度高,光栅常数直接溯源于原子能级。希望能够通过对激光的改良来提升原子沉积结果。通过双层驻波场来提高原子沉积质量已经被多次提到。实验中利用几何光学的方法实现了所需要的新型激光驻波场。并对其汇聚,相干等特性进行了研究,取得了较为满意的结果。为利用双层驻波场来沉积原子打下了基础。     

Micro/nano-heater integrated cantilevers for micro/nano-lithography applications

This paper describes an array of micro/nano-heater-integrated cantilevers for micro- and nano-lithography applications. In the scanning thermal cantilever, as the electrical current flows through the cantilever with a conductive tip, electrical power is dissipated mainly within the tip area, and this dissipation raises the local temperature around the tip area. When the thermal power is applied to a thin photoresist film, spin-coated on silicon wafers or mask substrates, more than 90% of solvents involved in the photoresist starts to evaporate from the layer. Hence, the exposed areas can resist commercial developers during the development process. Patterning speed has been improved by employing an array of heaters with various sizes. The novel concept of the SPM-based nano-lithography has been successfully demonstrated by application on the fabricated cantilevers and a commercial SPM system.     

Josephson edge-junction devices using E-beam lithography

Superconducting interferometers containing up to nine lithographic levels were exposed by direct e-beam writing in a vectorscan (VS) system, The number and thickness of the layers presented a new challenge to e-beam and liftoff resist technology. A novel approach to level-to-level registration was required. In the edge-junction structure, the Josephson-junction width of typically 0.3 µm was achieved by forming the Josephson junctions on the edges of the niobium base electrode without using submicrometer lithography. Such Nb-oxide-Pb-alloy edge junctions are promising for logic and memory applications. The ruggedness of a niobium base electrode is combined with a high-current-density device having low capacitance by virtue of the small junction area.     

Scheduling of mask shop E-beam writers

Reducing wafer fabrication cycle time and providing on-time wafer deliveries are among the top priorities of semiconductor companies. Mask manufacturing is essential to the overall wafer fabrication process since on-time delivery of masks significantly affects wafer fabrication cycle times. Moreover, delivering wafers on time means deliveries of masks must be on time as well. This research studies the scheduling problem of the bottleneck machine-the Electrical Beam (E-beam) Writer-of a mask shop. The criterion of minimum total tardiness is used as our performance measure to schedule this bottleneck operation. Using a predetermined Earliest-Due-Date (EDD) dispatch policy set by management, this study first addresses the problem of scheduling batches of a single mask size on a single machine. The approach is extended to the problem of scheduling batches of two mask sizes on a single machine; finally, a heuristic for a multiple-machine problem is developed. For the problem of a single machine under EDD dispatching policy, the problem can be formulated as a Dynamic Program (DP). Thus, it can be solved for an optimal solution in polynomial time. For the multiple machines problem, we heuristically allocate the masks to each machine. Each machine with allocated masks can then be solved by the DP formulation designed for the single machine problem. Based on the computational experiments in this study, the proposed DP approach reduces total tardiness by an average of 55% from the method currently in use at a major IC manufacturing foundry. Furthermore, in the case that due dates are set realistically, the DP approach reduces the tardiness about 95% from the shop's current method and about 88% from a simple full-batch method of scheduling     

电子束致沉积手控生长碳纳米线

用电子束致沉积(EBID)来制备各种纳米尺寸的结构在纳米材料的制备和器件构建方面有着良好的应用前景。相对于聚焦离子束(FIB),它具有对样品损伤小和所得结构尺寸更小等优点。此前,电子束致沉积的工作大多数在扫描电镜中完成,而在透射电镜中沉积直到近两年才发展起来。本文尝试在普通热发射透射电镜中,手动控制生长碳纳米线、点等结构。对碳纳米线的生长过程进行了原位观测,并对电子束斑的大小、形状和辐照时间对沉积物形状的影响作了初步的研究。最后对电子束致沉积可控生长无定型碳纳米线可能的应用作了一些探索。     

电子束曝光机静电偏转系统

以静电极板为电子束曝光机偏转负载，用双通道扫描原理进行扫描，并使用计算机辅助设计研究电子束曝光机聚焦偏转系统的结构。由SDS-3电子束曝光机试验结果表明，复合静电偏转可以达到磁偏转相似的像差水平。     

电子束与光学混合制版技术在GaAs器件研制中的应用

介绍了用光学制版设备制作GaAs器件光刻中除栅条掩模版外的其它各层掩模版,用高分辨率电子束制版设备制作线宽≤0.5μm、并能与光学设备制作的各层掩模版精确套刻的栅条掩模版,即电子束与光学混合制版技术。对解决两类制版系统制作的掩模版精确互套的方法、干法刻蚀等工艺过程做了必要的阐述。