Electron trap generation in high-/spl kappa/ gate stacks by constant voltage stress

Positive bias constant voltage stress combined with charge pumping (CP) measurements were applied to study trap generation phenomena in SiO/sub 2//HfO/sub 2//TiN stacks. Using gate stacks with varying thicknesses of the interfacial SiO/sub 2/ layer (IL) or high-/spl kappa/ layer and analysis for frequency-dependent CP data developed to address trap depth profiling, the authors have determined that the defect generation in the stress voltage range of practical importance occurs primarily within the IL on as-grown "precursor" defects most likely caused by the overlaying HfO/sub 2/ layer. The generated traps can be passivated by a forming gas or nitrogen (N/sub 2/) anneal, whereas a postanneal stress reactivates these defects. The results obtained identify the IL as one of the major targets for reliability improvement of high-/spl kappa/ stacks.     

Observations of NBTI-induced atomic-scale defects

A combination of MOSFET gate-controlled diode measurements and a very sensitive electron spin resonance technique called spin-dependent recombination was utilized to observe and identify defect centers generated by a negative bias temperature stress in fully processed SiO/sub 2/-based pMOSFETs. In SiO/sub 2/ devices, the defects include two Si/SiO/sub 2/ interface silicon dangling bond centers (P/sub b0/ and P/sub b1/) and may also include an oxide silicon dangling bond center (E'). The observations indicate that both P/sub b0/ and P/sub b1/ defects play major roles in these SiO/sub 2/-based devices and suggest that E' centers could play an important role.     

Measurement of the interface trap and dielectric charge density in high-/spl kappa/ gate stacks

We demonstrate an accurate measurement of the interface trap density and the stress-induced dielectric charge density in Si/high-/spl kappa/ gate dielectric stacks of metal-oxide-semiconductor field-effect transistors (MOSFETs) using the direct-current current-voltage (DCIV) technique. The capture cross section and density of the interface traps in the high-/spl kappa/ gate stack were found to be similar to those of the Si/SiO/sub 2/ interface. A constant-voltage stress of the p-channel MOSFET in inversion is shown to result in a negative dielectric charging and an increase in the interface trap density.     

Magnetic resonance studies of trapping centers in high-/spl kappa/ dielectric films on silicon

The electrical properties of high dielectric constant materials being considered for replacements of SiO/sub 2/ in metal-oxide semiconductor (MOS) field effect transistors are dominated by point defects. These point defects play important roles in determining the response of these films in almost any imaginable reliability problem. A fundamental understanding of these defects may help to alleviate the problems which they can cause. The best known methods for determining the structure of electrically active defects in MOS materials and devices are conventional electron spin resonance (ESR) and electrically detected magnetic resonance (EDMR). In this paper, we review the limited ESR and EDMR work performed to date on high-/spl kappa/ materials. A discussion of magnetic resonance techniques as well as a brief overview of the extensively studied Si/SiO/sub 2/ system is also included.     

Impact of high-/spl kappa/ dielectric HfO/sub 2/ on the mobility and device performance of sub-100-nm nMOSFETs

Scaling of Si MOSFETs beyond the 90-nm technology node requires performance boosters in order to satisfy the International Technology Roadmap for Semiconductors requirements for drive current in high-performance transistors. Amongst the preferred near term solutions are transport enhanced FETs utilizing strained Si (SSi) channels. Additionally, high-/spl kappa/ dielectrics are expected to replace SiO/sub 2/ around or after the 45-nm node to reduce the gate leakage current problem, facilitating further scaling. However, aside from the many technological issues such as trapped charge and partial crystallization of the dielectric, both of which are major issues limiting the reliability and device performance of devices employing high-/spl kappa/ gate stacks, a fundamental drawback of MOSFETs with high-/spl kappa/ dielectrics is the mobility degradation due to strong soft optical phonon scattering. In this work we study the impact of soft optical phonon scattering on the mobility and device performance of conventional and strained Si n-MOSFETs with high-/spl kappa/ dielectrics using a self-consistent Poisson Ensemble Monte Carlo device simulator, with effective gate lengths of 67 and 25-nm. Additionally we have also briefly investigated the effect (the percentage change) that a trapped charge within the gate oxide will have on the drive current for both a SiO/sub 2/ oxide and an equivalent oxide thickness of high-/spl kappa/ dielectric.     

BTI characteristics and mechanisms of metal gated HfO/sub 2/ films with enhanced interface/bulk process treatments

Significant deviations in BTI characteristics for metal gate HfO/sub 2/ films compared to silicon oxide based films prove that conventional reliability models based on SiO/sub 2/ films can no longer be directly applied to HfO/sub 2/ based MOSFETS. This study shows the use of conventional accelerated reliability testing in the Fowler-Nordheim tunneling regime to extrapolate time to failure at operating voltages (direct tunneling regime) overestimates device lifetimes. Additionally, unlike conventional gate oxides, the slope of /spl Delta/V/sub t/ versus time (or the rate of charge trapping) in HfO/sub 2/ MOSFETS is dependent on stress voltage. The HfO/sub 2/ based metal gated nMOSFETS show poor PBTI characteristics and do not meet the 10 year lifetime criterion for threshold voltage stability. On the other hand, HfO/sub 2/ based pMOSFETS show superior NBTI behavior and meet the 10 year lifetime criterion. These results are contrary to the observations with conventional gate dielectrics. This paper explores the anomalous charge trapping behavior and provides a comprehensive study of the PBTI characteristics and recovery mechanisms in metal gated HfO/sub 2/ films.     

Threshold voltage instabilities in high-/spl kappa/ gate dielectric stacks

Over recent years, there has been increasing research and development efforts to replace SiO/sub 2/ with high dielectric constant (high-/spl kappa/) materials such as HfO/sub 2/, HfSiO, and Al/sub 2/O/sub 3/. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In these materials, threshold voltage is observed to shift with stressing time and conditions, thereby giving rise to threshold voltage instabilities. In this paper, we review various causes of threshold voltage instability: charge trapping under positive bias stressing, positive charge creation under negative bias stressing (NBTI), hot-carrier stressing, de-trapping and transient charge trapping effects in high-/spl kappa/ gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed.     

Widely tunable Al/sub 2/O/sub 3/-GaAs DBR filters with variable tuning characteristics

We demonstrate an optical tunable filter using Al/sub 2/O/sub 3/-GaAs layers as the top distributed Bragg reflector mirror. The mechanical properties and spectral response versus voltage are characterized. The tuning characteristics can be changed by removing the tensile-stressed Si/sub 3/N/sub 4/ on the mirror and legs. An integrated optical-mechanical model is used to analyze the result. Axial nitride and initial residual stress are incorporated into the model to obtain accurate fit. A 64-nm tuning range with 12-V tuning voltage is measured, a significant improvement over previous designs.     

Fabrication of SiO/sub 2/ microlenses on silicone rubber using a vacuum-ultraviolet F/sub 2/ laser

SiO/sub 2/ microlenses are fabricated on a silicone rubber surface. The silicone surface irradiated by an F/sub 2/ laser beam swells and is modified to SiO/sub 2/ by means of photochemical reaction. When the surface is irradiated by 6000-12000 shot laser pulses, it becomes smooth and spherical. By altering the number of pulses, it is possible to alter the microlenses' focal lengths within the range of 120-170 /spl mu/m.     

Validity of constant voltage stress based reliability assessment of high-/spl kappa/ devices

Charge trapping in high-/spl kappa/ gate dielectrics affects the result of electrical characterization significantly. DC mobility degradation and device threshold voltage instability and C-V and I-V hysteresis are a few examples. The charging effects in high-/spl kappa/ gate dielectric also affect the validity of conventional reliability test methodologies developed for SiO/sub 2/ devices. In this paper, we review high-/spl kappa/ materials specific phenomena that can affect the validity of constant-voltage-stress-based reliability test methods to address the direction of future reliability study on high-/spl kappa/ devices.     

Two-trap-assisted tunneling model for post-breakdown I-V characteristics in ultrathin silicon dioxide

This paper investigated the degradation and breakdown characteristics of an ultrathin silicon dioxide film by using conductive atomic force microscopy (C-AFM) with repetitive ramped voltage stress (RVS). Two-step oxide degradation was determined from the measured current-voltage (I-V) characteristics and topographies. In the first step, bond breaking and negative-charge accumulation near the SiO/sub 2//Si interface causes oxide thinning and an effective increase in SiO/sub 2//Si barrier height. In this step, hard breakdown (HBD) actually does not occur until permanent damage is produced within the oxide during the second step after several times of repetitive RVS. The permanent damage produced inside the oxide film is in the form of traps, which will cause the crooked I-V curves and a larger I-V shift along the voltage axis. A two-trap-assisted tunneling (TTAT) model was proposed to explain the postbreakdown I-V behaviors. In this model, two isolated traps were generated in the oxide after breakdown. The trap location of the nearer traps determines the bending of the postbreakdown I-V curves and that of the farther traps causes the I-V oxide voltage shift along the voltage axis. The model fits the measured postbreakdown I-V curves well when the locations of both the nearer trap and the farther trap are chosen correctly.     

Write/erase cycling endurance of memory cells with SiO/sub 2//HfO/sub 2/ tunnel dielectric

The write/erase cycling endurance of low voltage floating-gate memory cells programmed and erased by tunneling through a SiO/sub 2//HfO/sub 2/ dual layer tunnel dielectric stack is investigated. The use of fixed single pulse program and erase conditions leads to fast shifting (after /spl sim/1000 cycles) of the threshold voltage window, so that only a limited number of write/erase cycles can be achieved. Increasing the write and erase duration quickly leads to an excessive erase time so that a different erase method has to be used. Improvement of the erase behavior and cycling endurance has been obtained by a combination of two methods. Inclusion of soft write pulses between the erase pulses reduces the amount of charge trapped in the tunnel dielectric and therefore limits the increase in erase time. Also, the erase voltage can progressively be raised in order to further limit the erase time, leading to an endurance of 10 000 cycles on the considered cells. When combining the SiO/sub 2//HfO/sub 2/ stack with channel hot electron injection so that tunneling is only required in one direction, 100 000 write/erase cycles are demonstrated with minimal change of the memory window.     

Mechanisms of concurrent SiO desorption with oxide layer formation at Si(001) surface

Oxidation reactions at Si(001) surfaces have been studied via real‐time in situ photoemission spectroscopy with synchrotron radiation for chemical bonding states of Si and O atoms and mass spectrometry for desorption of SiO molecules with supersonic O₂ molecular beams in a temperature region from 900 K to 1300 K. In our previous studies, the SiO desorption yield decreased with increasing incident energy in a temperature region from 900 K to 1000 K. In that case, the time evolutions of Si 2p photoemission spectra showed that SiO₂ structure on the surface was easily formed by the action of larger incident energy and the increased SiO₂ coverage correlated with the decreased SiO desorption yield. In this study, simultaneous measurements of Si 2p photoemission spectra and SiO desorption yield revealed that the decrease of SiO correlated with the increase of Si²⁺ component, and the SiO desorption was terminated at the oxide thickness of 0.22 nm. These facts suggest that the SiO desorption takes place at the topmost Si dimers and a precursor for SiO desorption is a so‐called T site, in which O atoms are bonding with the dangling bonds of the dimers. Consequently, M1 and M2 in the Dual‐Oxide‐Species (DOS) model have been clarified to be a T site and a Si²⁺ state, respectively. © 2008 Wiley Periodicals, Inc. Electr Eng Jpn, 164(3): 60–68, 2008; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20678     

Point defects in ZrO/sub 2/ high-/spl kappa/ gate oxide

This paper presents calculations of the electrical energy levels of the main point defects in ZrO/sub 2/, the oxygen vacancy and the oxygen interstitial. The levels are aligned to those of the Si channel using the known band offsets. The oxygen vacancy gives an energy level in the Si gap or just above the gap, depending on its charge state. This is the main electrically active defect and trap in ZrO/sub 2/ films. The oxygen interstitial gives levels just above the oxide valence band, and the neutral interstitial also gives a level near the Si conduction band.     

Time-Dependent Dielectric Breakdown of 4H-SiC/$ hbox{SiO}_{2}$ MOS Capacitors

Time-dependent dielectric breakdown (TDDB) is one of the major issues concerning long-range reliability of dielectric layers in SiC-based high-power devices. Despite the extensive research on TDDB of $hbox{SiO}_{2}$ layers on Si, there is a lack of high-quality statistical TDDB data of $hbox{SiO}_{2}$ layers on SiC. This paper presents comprehensive TDDB data of 4H-SiC capacitors with a $ hbox{SiO}_{2}$ gate insulator collected over a wide range of electric fields and temperatures. The results show that at low fields, the electric field acceleration parameter is between 2.07 and 3.22 cm/MV. At fields higher than 8.5 MV/cm, the electric field acceleration parameter is about 4.6 cm/MV, indicating a different failure mechanism under high electric field stress. Thus, lifetime extrapolation must be based on failure data collected below 8.5 MV/cm. Temperature acceleration follows the Arrhenius model with activation energy of about 1 eV, similar to thick $hbox{SiO}_{2}$ layers on Si. Based on these experimental data, we propose an accurate model for lifetime assessment of 4H-SiC MOS devices considering electric field and temperature acceleration, area, and failure rate percentile scaling. It is also demonstrated that temperatures as high as 365 $^{circ}hbox{C}$ can be used to accelerate TDDB of SiC devices at the wafer level.      

Composition Optimization and Phase Transformation of Si-Nanocrystal-Doped $hbox{SiO}_{x}$ for Enhancing Luminescence From MOSLED

Near-infrared (NIR) photo- and electroluminescence (PL and EL) of Si nanocrystals buried in Si-rich SiO_x, film, and their correlation with the structural phase transformation and the varied oxygen composition of SiO_x, are investigated. By detuning the N₂O flowing ratio (Y_{N 2 O} = [N₂O/(N₂O + SiH₄)] times 100%) from 93% to 80% during plasma-enhanced chemical vapor deposition growth, the oxygen composition ratio of the Si-rich SiO_x, can be adjusted from 1.64 to 0.88. The grazing incident X-ray diffraction and X-ray photoelectron spectroscopy spectra indicate that the SiO_x, transforms its structural phase from Si + SiO₂ isomer to Si + SiO + SiO₂ isomer. With O/Si ratio >1.24, the SiO_x, matrix becomes SiO₂ isomer, whereas the SiO_x, structure approaches SiO phase at O/Si ratio that is nearly 1.0. The formation of SiO matrix in SiO_x, grown at Y_{N 2 O} below 85% reduces the precipitated Si nanocrystal density from 2.8 times 10¹⁸ to 7 times 10¹⁶ cm^-3, and monotonically attenuates the NIR PL by one order of magnitude. Such a structural phase transformation from SiO₂ to SiO in SiO_x with lower O/Si ratio causes the degradation in EL power conversion efficiency and external quantum efficiency (EQE). Maximum EL power of 0.5 muW and EQE of 0.06% are obtained from MOSLED made on SiO_x, with optimized O/Si ratio of 1.24.     

Conduction band-edge States associated with the removal of d-state degeneracies by the Jahn-Teller effect

X-ray absorption spectroscopy (XAS) is used to study band edge electronic structure of high-/spl kappa/ transition metal (TM) and trivalent lanthanide rare earth (RE) oxide gate dielectrics. The lowest conduction band d/sup */-states in TiO/sub 2/, ZrO/sub 2/ and HfO/sub 2/ are correlated with: 1) features in the O K/sub 1/ edge, and 2) transitions from occupied Ti 2p, Zr 3p and Hf 4p states to empty Ti 3d-, Zr 4d-, and Hf 5d-states, respectively. The relative energies of d-state features indicate that the respective optical bandgaps, E/sub opt/ (or equivalently, E/sub g/), and conduction band offset energy with respect to Si, E/sub B/, scale monotonically with the d-state energies of the TM/RE atoms. The multiplicity of d-state features in the Ti L/sub 2,3/ spectrum of TiO/sub 2/, and in the derivative of the O K/sub 1/ spectra for ZrO/sub 2/ and HfO/sub 2/ indicate a removal of d-state degeneracies that results from a static Jahn-Teller effect in these nanocrystalline thin film oxides. Similar removals of d-state degeneracies are demonstrated for complex TM/RE oxides including Zr and Hf titanates, and La, Gd and Dy scandates. Analysis of XAS and band edge spectra indicate an additional band edge state that is assigned Jahn-Teller distortions at internal grain boundaries. These band edges defect states are electronically active in photoconductivity (PC), internal photoemission (IPE), and act as bulk traps in metal oxide semiconductor (MOS) devices, contributing to asymmetries in tunneling and Frenkel-Poole transport that have important consequences for performance and reliability in advanced Si devices.     

Preparation of PLZT Ferroelectric Films by RF Sputtering on 200 mmφ Substrate

(Pb, La)(Zr, Ti) O 3 (PLZT) thin films were deposited on 200mm } Pt/Ti/SiO2/Si substrates by RF magnetron Sputtering using multichamber production system. The Pb content in PLZT films deposited at low temperature was measured by X-ray fluorescence spectroscopy (XRF), and ferroelectrics properties were measured. Good uniformities of Pb content and deposition rate were achieved on 200mm } substrate. For ferroelectrics properties, only small deference was observed between the center and the edge of 200mm } substrate.     

Electrical Characteristics and Thermal Stability of Pt/HfO 2 /Si Metal-Insulatror-Semiconductror Capacitors

The HfO 2 thin films for use in gate dielectric applications were deposited at 300 onto p-type Si (100) substratee using Hf[OC(CH 3 ) 3 ] 4 as the precursor in the absence of oxygen by plasma-enhanced chemical vapor deposition. The HfO 2 films deposited in the absence of O 2 show excellent electrical properties such as low capacitance equivalent thickness (CET), good thermal stability and low charge trapping. The as-deposited films have an interfacial layer of approximately 1 nm in thickness, resulting in a decrease in the thickness of the interfacial layer by about 50% compared to films deposited in the presence of oxygen. The leakage current density of HfO 2 films was approximately 3 orders of magnitude lower than an electrically comparable SiO 2 at the same CET. The improvement of electrical properties can be attributed to the decrease in the SiO 2 interfacial layer. The thickness of the interfacial layer can be contolled by the deposition in the absence of oxygen after evacuation of the reaction chamber by means of an ultra-high vacuum.     

Review on high-k dielectrics reliability issues

High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in CMOS advanced technologies. One of the important challenges in integrating these materials is to achieve lifetimes equal or better than their SiO/sub 2/ counterparts. In this paper we review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fast and reversible charge. Reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. One of the main issues is to understand these new mechanisms in order to asses the lifetime accurately and reduce them.