共查询到17条相似文献,搜索用时 93 毫秒
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考虑工艺随机扰动对互连线传输性能的影响,建立了互连线随机扰动模型,提出了一种基于谱域随机方法的互连线串扰分析新方法.该方法将具有随机扰动的耦合互连线模型在线元分析阶段进行解耦,分别采用随机伽辽金方法(SGM)和随机点匹配方法(SCM)进行串扰分析.最后,利用复逼近给出工艺随机扰动下互连线串扰噪声的解析表达式.实验结果表明本文方法不仅可以对工艺随机扰动下的非均匀耦合互连线串扰进行有效估计,相较于SPICE仿真还具有更高的计算效率. 相似文献
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针对高速互连系统中传输线上的串扰问题,基于电磁耦合理论,研究了耦合传输线信道传输矩阵的性质,建立了以下两种情况的耦合传输线信道传输矩阵模型及其矩阵分解形式,分别是:(1)考虑受扰线两边各一条相邻微带线对受扰线的串扰;(2)考虑受扰线两边各两条相邻微带线对受扰线的串扰.给出了上述两种情况下基于耦合传输线信道传输矩阵分解形式的串扰抵消方案,并利用仿真工具ADS对其进行了验证.结果表明:信号抖动和失真大幅下降,串扰抵消效果良好,并且第二种情况下的串扰抵消效果优于第一种情况.该结果说明了在基于耦合传输线信道传输矩阵进行串扰抵消时,考虑两边各两条相邻微带线的串扰效果较好,对保持高速信号完整性具有一定的实际应用价值. 相似文献
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随着微电子技术的进步,集成电路的特征尺寸逐步缩小,IC设计已经向着深亚微米甚至超深亚微米设计发展,一系列由于互连线引起的信号完整性问题需要设计者更多的考虑,互连线串扰已经成为影响IC设计成功与否的一个重要因素。针对串扰这一问题本文讨论了串扰对于电路的影响,分析了深亚微米集成电路设计中对两相邻耦合RC互连串扰的成因,介绍了互连线R,C参数的提取。以反相器驱动源和容性负载为例,建立了两相邻等长平行互连线的10阶互连模型,并且针对该模型,利用Cadence软件进行仿真,分析了引起串扰的因素。在此基础上,最后给出了有效抑制串扰的方法。 相似文献
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Crosstalk analysis for a CMOS gate driven inductively and capacitively coupled interconnects 总被引:1,自引:0,他引:1
This paper deals with crosstalk analysis of a CMOS driven capacitively and inductively coupled interconnect. The Alpha Power Law model of MOS transistor is used to represent a CMOS driver. This is combined with a transmission line-based coupled RLC model of interconnect to develop a composite model for analytical purpose. On this basis a transient analysis of crosstalk noise is carried out. Comparison of the analytical results with SPICE extracted results shows that the error involved is nominal. 相似文献
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A coupled interconnect model is developed using even mode and odd mode capacitance analysis. Signal coupling is presented in terms of interconnect width, substrate thickness, interconnect line spacing, and frequency. Picosecond photoconductor based measurements of coupled transmission lines on the integrated circuit support the even and odd mode signal transmission simulation results. SPICE circuit simulation is used to demonstrate the model utility and explore the sensitivity of the self- and mutual capacitances and inductances in signal crosstalk. 相似文献
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超深亚微米集成电路串扰估计及优化 总被引:3,自引:2,他引:1
采用RLC模型来估计互连线间的耦合噪声并对模拟结果进行分析,在此基础上,提出了几种不同的算法实现了带串扰约束的集成电路布线结果调整. 相似文献
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采用RLC模型来估计互连线间的耦合噪声并对模拟结果进行分析,在此基础上,提出了几种不同的算法实现了带串扰约束的集成电路布线结果调整. 相似文献
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Crosstalk fault modeling in defective pair of interconnects 总被引:1,自引:0,他引:1
Ajoy K. Palit Author Vitae Kishore K. Duganapalli Author Vitae Author Vitae 《Integration, the VLSI Journal》2008,41(1):27-37
The manufacturing defect in the interconnect lines can lead to various electrical faults, e.g. defect due to under-etching effect/conductive particle contamination on interconnect line can lead to increased coupling capacitances between the two adjacent interconnects, which, in turn, can eventually result in crosstalk fault in the deep sub-micron (DSM) chips. In this paper, we describe the line-defect-based crosstalk fault model that will be helpful in analyzing the severity of the defect/fault, as the crosstalk fault occasionally leads to various signal integrity losses, such as timing violation due to excessive signal delay or speed-up, logic failure due to crosstalk positive/negative glitch above/below logic low/high threshold and also reliability problem particularly due to crosstalk glitch above logic high threshold. Our crosstalk fault model is very fast (at least 11 times faster than PSPICE model) and its accuracy is very close to PSPICE simulation results when the defect/fault is located in the middle of interconnects, whereas for the defects located at the near-end/far-end side of aggressor-victim the model accuracy differs marginally. 相似文献