a-Si厚度对TFT开关特性的影响

通过在线电学测试设备,研究了不同a-Si厚度对TFT开关电学特性的影响。本试验通过调整刻蚀时间改变沟道内a-Si的剩余厚度,在此基础上找出电学特性比较稳定的区域和电学特性变差的临界点。试验结果表明,在其它条件不变的情况下,a-Si剩余厚度在33～61%时TFT的电学特性比较好,a-Si剩余厚度小于33%之后,TFT的电学特性变差,即工作电流变小,阈值电压变大,迁移率变小。     

TFT有源层刻蚀均一性和电学性质的研究

对TFT制作工艺中,TFT有源层刻蚀均一性与电学性质进行分析研究。通过扫描电子显微镜,电学测试设备对样品进行分析。结果显示沟道有源层的刻蚀功率,气体比例及刻蚀压强对有源层的刻蚀均一性都有较大影响,并会影响TFT电学特性的均一性。通过适当降低刻蚀功率及反应气体SF6/Cl2的比例,同时,降低反应压强,可以改善有源层刻蚀的均一性。从而,TFT电学特性的均匀性得到优化。     

a-Si剩余膜厚对TFT特性的影响

本文通过电学特性测试设备在黑暗(Dark)和光照(Photo)两种测试环境下,研究了沟道不同a-Si剩余厚度对TFT电学特性的影响。通过调整刻蚀时间改变沟道内a-Si剩余厚度,找出电学特性稳定区域以及突变的临界点。实验结果表明:在黑暗(Dark)环境下a-Si剩余厚度在30%～48%之间时,TFT器件的电学特性比较稳定,波动较小;而剩余厚度少于30%时,TFT特性变差,工作电流变小,开启电压变大,电子迁移率变小;在光照环境下主要考虑漏电流的影响,在a-Si剩余厚度43%以内时,光照I_(off)相对较低(小于Spec 20pA),同时变化趋势较缓;而剩余厚度大于43%时,光照I_(off)增加25%,同时变化趋势陡峭。综合黑暗和光照测试环境,在其他条件不变的情况下,a-Si剩余厚度在30%～43%之间时TFT的电学特性较好,同时相对稳定。     

分析TFT亮态漏电流影响因素的测试方法

对于薄膜晶体管液晶显示器来说,TFT的特性对产品的品质有很大的影响,而其亮态漏电流Ioff的影响尤为重要。为改善器件性能,需要深入分析TFT亮态漏电流的影响因素。本文在实验基础上提出一种测试方法,首先使用BM PR(Black Matrix Photo Resist)对TFT沟道的不同位置进行遮挡;再对遮挡样品进行TFT特性测试。进而能模拟出实际工作中的TFT亮态漏电流,可以更加简便有效地优化TFT下方的栅极金属线宽,同时降低亮态漏电流。最后制作了54.6cm(21.5in)改善样品,通过新测试方法分析,将栅极金属线加宽约1.5μm,改善后样品的亮态漏电流从14.08pA降至约9.50pA。所以,使用新的测试方法无需将样品制作到模组后再进行品质评价,简单有效并降低了产品制造成本。     

TFT-LCD周边驱动电路集成化设计

根据N沟道和P沟道多晶硅薄膜晶体管(poly SiTFT)的特性,使用Orcad作为辅助工具,设计了应用于132(RGB)×176TFT LCD的栅驱动电路和数据驱动电路。依据132RGB×176TFT LCD的参数对电路进行了模拟,实现了小尺寸液晶屏的p SiTFT周边集成驱动电路的设计。     

Halo LDD结构多晶硅薄膜晶体管的模拟研究

提出了多晶硅薄膜晶体管的一种Halo LDD新结构,这种结构是在基于LDD结构的基础上,在沟道靠近源、漏端引入高掺杂的Halo区.并利用工艺和器件模拟软件对该Halo LDD P-Si TFT的电学特性进行了分析,并将其与常规结构、LDD结构和Halo结构进行了比较.发现Halo LDD结构的P-si TFT能有效地降低泄漏电流、抑制阈值电压漂移和Kink效应;减少因尺寸减小后所带来的一系列问题.     

不同双栅极设计对a-Si:H TFT特性影响

本实验于原有的单底栅a-Si TFT产品结构下,通过增加不同的顶栅极设计方式(不同a-Si覆盖比例、不同沟道几何形貌、不同沟道W/L比例)来研究双栅极设计对a-Si TFT特性的影响。实验结果显示双栅极a-Si TFT比现行单底栅a-Si TFT可以提升I_on 7%、降低SS 3%、同时对I_off以及TFT稳定性影响不明显,显示双栅极a-Si TFT设计结构具有在不提高成本以及不变更工艺流程下,达到整体提升TFT特性的效果。顶栅极 TFT 特性不如底栅极,推测为a-Si/PVX界面不佳使得电子导通困难导致,未来可以借由改善a-Si/PVX界面工艺提升顶栅极TFT特性。     

高可靠性Cu BCE a-IGZO TFTs的制作

背沟道刻蚀型（BCE）非晶氧化铟镓锌薄膜晶体管（a-IGZO TFT）具有工艺简单、寄生电容小以及开口率高等优点,但BCE IGZO器件背沟道易受酸液和等离子体损伤,进而引起TFT均匀性和稳定性等方面问题,随着GOA技术的导入,对TFT器件电学性能的均匀性和稳定性提升的要求也日益迫切,因此开发高信赖性BCE IGZO TFT是技术和市场的迫切要求。本文主要分析了基于IGZO的背沟道刻蚀型薄膜晶体管电学性质,通过优化钝化层材料,色阻材料以及GOA TFT结构等削弱因背沟道水汽吸附引起的器件劣化,偏压温度应力测试结果显示优化后的TFT展现了良好的稳定性——在80℃,栅极30 V负向偏压条件下,2 000 s的ΔV_th小于1 V。最终,利用优化的IGZO TFT制作了215.9 mm（85 in）8K4K 120 Hz液晶显示器。     

高可靠性Cu BCE a-IGZO TFTs的制作（英文）

背沟道刻蚀型(BCE)非晶氧化铟镓锌薄膜晶体管(a~-IGZO TFT)具有工艺简单、寄生电容小以及开口率高等优点,但BCE IGZO器件背沟道易受酸液和等离子体损伤,进而引起TFT均匀性和稳定性等方面问题,随着GOA技术的导入,对TFT器件电学性能的均匀性和稳定性提升的要求也日益迫切,因此开发高信赖性BCE IGZO TFT是技术和市场的迫切要求。本文主要分析了基于IGZO的背沟道刻蚀型薄膜晶体管电学性质,通过优化钝化层材料,色阻材料以及GOA TFT结构等削弱因背沟道水汽吸附引起的器件劣化,偏压温度应力测试结果显示优化后的TFT展现了良好的稳定性——在80℃,栅极30V负向偏压条件下,2 000s的ΔV_(th)小于1V。最终,利用优化的IGZO TFT制作了215.9mm(85in)8K4K120Hz液晶显示器。     

不同光刻胶作保护层对a-IGZO TFT性能的影响

采用脉冲直流溅射的方式沉积IGZO膜层作为底栅结构TFT的有源层,并在背沟道上涂覆不同类型的光刻胶作为保护层,探讨不同保护层对器件电学特性的影响。经考察发现:采用光刻胶作为保护层时,保护层制作后短期内可维持器件的电学特性基本不变;但涂胶后暴露在空气中一定时间后,器件的电学特性开始衰退,尤其是阈值电压变化较明显,器件工作模式由增强型变为耗尽型,并推断光刻胶中溶剂接触到背沟道中IGZO,其化学反应导致沟道中氧脱附,载流子浓度增加。实验还发现:使用SU-8负性光刻胶作为保护层的器件,其电学特性衰退较小,在空气中放置一段时间后表现最稳定。     

一种TFT源漏极沟道尺寸的自动测量方法

为了实现对图像中TFT源漏极的快速定位和沟道尺寸的自动测量,采用基于图像特征点的图像识别方法。在识别过程中先采用图像处理的方法对图像进行优化,再采用多边形拟合的方法确定目标的边缘,并通过改进的角点检测方法对物体形状进行更精确的定位,从而实现了对TFT源漏极沟道尺寸的精确测量。经过实验验证,精度可达到0.02像素。     

工艺路线对TFT工厂能源消耗的影响

为了在TFT工厂的设计、建设及运营阶段采取有针对性的节能降耗措施,有效降低器件制备过程中的能耗,本文根据我院多年从事TFT生产线节能评估工作的经验数据,针对不同技术路线,选取具有代表性的TFT-LCD及AMOLED生产线,并对其能耗进行对比分析,以讨论不同技术路线对TFT-LCD及AMOLED显示器件生产能耗的影响。分析结果表明:阵列制备是最主要用能工序,其制备复杂程度可采用光罩次数(Mask)表征。随着光罩次数的增加,器件制造对电力、氮气、新鲜水等能源及耗能工质的需求呈急剧增长:采用10-13Mask技术的LTPS及AMOLED显示器件,其综合能耗达到a-Si及Oxide技术路线的约350%之多;在不同技术路线下,电力均为最主要的用能需求,其消耗量占总能耗的80%~87%。能耗的增加导致用能成本的大幅上升。在国家大力提倡绿色经济的环境下,建议各大厂商采取科学有效的能耗管控措施,以降低能源消耗及用能成本,实现产业的健康可持续发展。     

ITO像素电极工序对于HADS产品TFT特性的影响

通过不同TFT几何结构验证ITO像素电极工序对于HADS产品TFT特性的影响。实验结果显示TN5mask与倒反HADS结构(源漏极→ITO像素电极)二者有比现行HADS结构(ITO像素电极→源漏极)更高的Ion,提升比率达到40%。推测主要原因为现行HADS结构(ITO像素电极→源漏极)在Si岛完成后进行ITO像素电极工序增加了N+与源漏极之间接触阻抗导致Ion降低。对于HADS产品,倒反HADS结构(源漏极→ITO像素电极)可以具有更好的TFT特性表现。对现行HADS结构,在沟道形成工序前的N+表面ITO残沙程度越少则Ioff越低;对于倒反HADS结构,沟道形成之后沟道表面ITO残沙程度对则对TFT特性没有明显影响。对于Poole-Frenkel区域,现行HADS结构(ITO像素电极→源漏极)比TN5mask与倒反HADS结构(源漏极→ITO像素电极)二者较低Ioff[Vg=-20V],下降达50%,主要为N+与源漏极之间接触阻抗增加的影响。     

多晶硅超薄沟道薄膜晶体管研制

提出了一种新结构的低温多晶硅薄膜晶体管 ( poly- Si TFT) .该 poly- Si TFT由一超薄的沟道区和厚的源漏区组成 .超薄沟道区可有效降低沟道内陷阱密度 ,而厚源漏区能保证良好的源漏接触和低的寄生电阻 .沟道区和源漏区通过一低掺杂的交叠区相连接 .该交叠区使得在较高偏置时 ,靠近漏端的沟道区电力线能充分发散 ,导致电场峰值显著降低 .模拟结果显示该TFT漏电场峰值仅是常规 TFT的一半 .实验结果表明该 TFT能获得好的电流饱和特性和高的击穿电压 .而且 ,与常规器件相比 ,该 TFT的通态电流增加了两倍 ,而最小关态电流减少了3.5倍 .     

An artificial fingerprint device (AFD): a study of identification number applications utilizing characteristics variation of polycrystalline silicon TFTs

An idea for obtaining unique identification (ID) numbers using polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a logic LSI compatible process is proposed. Like an actual human fingerprint, the characteristic variations of poly-Si TFTs are utilized for ID numbers in LSIs. The variation of poly-Si TFT characteristics is random, and this method offers unique, nonalterable, and nonduplicable numbers without any special processes, unlike other methods such as flash memory and mask ROM. These characteristics are highly suitable for ID number applications. The device physics of poly-Si TFTs for realizing the stable recognition of ID numbers was studied and a recognition circuit is proposed. The design guidelines for the grain size of poly-Si and AFD applications are also discussed.     

Study of polycrystalline-Si thin-film transistors with different channel layer thickness at low bias voltage

A sub-micron poly-Si TFT device, operating at a drain bias of 1.5 V, has been studied with respect to channel layer thickness. A thinner channel layer may lead to better good gate control over the entire channel region, thus resulting in a lower threshold voltage. Similarly, under negative gate bias, a thinner channel layer would sustain larger vertical electric field. However, a thinned channel layer can reduce the source/drain bulk punch-through, thus causing a smaller channel region with relatively high electric field for carrier field emission. With using a low drain bias of 1.5 V, for the poly-Si TFT device with a thinner channel layer, the leakage current would be more effectively suppressed by the resultantly smaller channel region with relatively high electric field for carrier field emission. As a result, even for a gate length of 0.5 μm, the poly-Si TFT device with 20-nm channel layer can cause an off-state leakage of about 0.1 pA/μm at a drain bias of 1.5 V, and an on/off current ratio higher than 8 orders can be achieved.     

A Novel Four-Mask-Step Low-Temperature Polysilicon Thin-Film Transistor With Self-Aligned Raised Source/Drain (SARSD)

In this letter, a novel structure of polycrystalline-silicon thin-film transistors (TFTs) with self-aligned raised source/drain (SARSD) and a thin channel has been developed and investigated. In the proposed structure, a thick SD and a thin active region could be achieved with only four mask steps, which are less than that in conventional raised SD TFTs. The proposed SARSD TFT has a higher on-state current and a lower off-state leakage current. Moreover, the on/off current ratio of the proposed SARSD TFT is also higher than that of a conventional coplanar TFT     

Effect of LDD structure and channel poly-Si thinning on agate-all-around TFT (GAT) for SRAM's

A lightly doped drain (LDD) structure was used in a gate-all-around TFT (GAT). This suppresses the leakage current much more than the LDD used in a single-gate TFT (SGT), and the current level of the GAT with the LDD is almost the same as that of the single-gate TFT (SGT) with the LDD keeping the GAT's advantage of a high on-current. This is because the LDD effectively relaxes the electric field at the drain edge and reduces the effect of the electric field from the surrounded gate of the GAT. Furthermore, the GAT can suppress individual performance variations. The suppression mechanism of the individual performance variation in a GAT was investigated using a poly-Si TFT simulator. The thinner the channel poly-Si, the smaller the individual performance variation of the TFT. The GAT is more effective in decreasing the individual performance variation for thin channels than the SGT because the GAT can achieve the full depletion of the channel poly-Si with a channel thickness twice as large as the SGT. The GAT is eminently suitable for use in high-density, low-voltage operations, and low-power SRAM's     

On-current modeling of large-grain polycrystalline siliconthin-film transistors

Large-grain excimer laser-annealed polysilicon TFTs are studied. Due to the large grain size of the polysilicon film (about 2.5 μm), we propose a model for the on-current (above threshold voltage) taking into account the number of grain boundaries within the channel. This linear-region model considers grain and grain boundaries as two noncorrelated regions within the channel of a polysilicon TFT. The trap density at the grain boundaries and the device parameters involved in this model are determined by fitting the experimental transfer characteristic in the linear regime. Moreover, we show that the proposed model provides reliable results within a temperature range from 150 K to 300 K. Finally, it serves to optimize the energy density of laser annealing and to make predictions about polysilicon TFT technology, since TFTs performances versus grain size plots can be obtained