共查询到19条相似文献,搜索用时 62 毫秒
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一种面向多核处理器的通用可调试性架构 总被引:1,自引:0,他引:1
硅后调试对于当代集成电路设计变得日益重要,用于辅助硅后调试的可调式性设计(DFD)应运而生.由于多核处理器往往包含多种不同类型的部件,每个部件都有各自的调试功能需求,极大地提高了可调式性设计的复杂度.针对上述问题,提出一种面向片上多核处理器的通用可调试性架构.该架构使用简单的监测器来监测和控制处理器中用于互连的片上网络,通过专门的调试总线将各个监测器与调试总控模块连接在一起,并使用EJTAG通用调试接口与外部调试主机传递信息.与传统的可调试性架构相比,该架构无需片上RAM,硬件代价低,具有模块化的特性.此外,文中提出的架构采用了工业界通用的EJTAG调试接口,因此通用性较高,已经被应用于龙芯-3B多核处理器中.实验结果显示,该架构可以在高频高数据带宽的环境下工作. 相似文献
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VLSI芯片的可测试性、可调试性、可制造性和可维护性设计 总被引:6,自引:0,他引:6
沈理 《计算机工程与科学》2003,25(1):92-97
CMOS器件进入深亚微米阶段,VLSI集成电路(IC)继续向高集成度,高速度,低功耗发展,使得IC在制造、设计、封装,测试上都面临新的挑战,测试已从IC设计流程的后端移至前端,VLSI芯片可测试性设计已成为IC设计中必不可少的一部分,本文介绍近几年来VLSI芯片可测试性设计的趋势,提出广义可测试性设计(TDMS技术)概念,即可测试试性,可调试性,可制造性和可维护性设计,并对可调试性设计方法学和广义可测试性设计的系统化方法作了简单介绍。 相似文献
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从设计工具、设计方法和设计流程三个方面对集成电路正向设计进行了简要的叙述。介绍了目前流行的几种正向设计工具及在实际设计中应注意的一些问题。 相似文献
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首先论述了可测性设计的概念,分析了时序电路测试生成面临的困境。然后介绍了可测性设计的专门方法,并举例说明了它在实际中的应用。 相似文献
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《计算机辅助设计与图形学学报》2014,(1)
为了缩短硅通孔的测试时间,针对符合JESD229和IEEE1149.1边界扫描协议的"存储+逻辑"3D集成电路,提出一种硅通孔可测试性设计.首先在逻辑晶片上增加控制模块,用于控制存储晶片的边界扫描链;然后通过修改逻辑晶片上原有边界扫描链结构,实现串联和并联2种与存储晶片边界扫描链连接的模式;最后在逻辑晶片上增加寄存器,以保存测试过程所使用的配置比特,控制整体测试流程.实验数据表明,该设计仅比原有的IEEE1149.1边界扫描电路增加了0.4%的面积开销,而测试时间缩短为已有工作的1?6. 相似文献
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集成电路可布性评估在集成电路物理设计中针对布局结果进行有效的评估,作为对布局的反馈信息,并指导后续布线阶段的工作,避免了当后续布线无法完成时再回到前面布局阶段进行重新布局的被动局面,减少了物理设计的迭代周期.提出一种快速可布性评估算法,采用新的基于概率模型的估计算法,利用边界框进行拥挤度的预估,并在概率指导下进行实际布线.文中算法可以在很短的运行时间内对拥挤情况进行较为准确、客观的分析,线长较短. 相似文献
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针对多核处理器硅后调试技术进行综述和分析.首先,介绍了多核处理器硅后调试技术面临的困难,特别是非确定性错误带来的新挑战;然后,概括介绍了国内外多核处理器硅后调试研究的最新进展,并分析了已有方法存在的问题;最后,对多核处理器硅后调试研究热点和趋势进行了分析,并指出该领域未来可能的研究方向. 相似文献
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多核并行程序的调试是一个公认的困难问题,困难主要来自于程序执行的不确定性.可重现调试(replay debug)提供了消除程序中不确定性的能力,但是现有的可重现调试解决方案都无法应用于商用的软硬件平台中,且进行调试所带来的性能损失会随着并发度的增加而超线性地增长.提出了一种基于运行快照的新型并行程序调试方法SDT(snapshot debug tool).该方法以离线的断点设置、运行快照捕捉和运行快照细化为基础,提出了一套可以指导用户由粗到细发现错误的调试过程,并在通用的软硬件平台上进行了实现.实验结果显示,在8线程的并发条件下,使用SDT调试所带来的时间性能损耗平均为5188%;同时当线程数增长4倍时,使用SDT所带来的额外时间消耗最多增长1倍,具有很好的可扩展性.记录快照的数据量是影响SDT性能的重要挑战,实验证明通过使用增量式的快照记录方式可以有效地降低需要记录的数据量,减少记录快照花费的时间,提高SDT的整体性能. 相似文献
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Program debugging is an important part of the domain expertise required for intelligent tutoring systems that teach programming languages. This article explores the process by which student programs can be automatically debugged in order to increase the instructional capabilities of these systems. The research presented provides a methodology and implementation for the diagnosis and correction of nontrivial recursive programs. In this approach, recursive programs are debugged by repairing induction proofs in the Boyer-Moore logic. The induction proofs constructed and debugged assert the computational équivalence of student programs to correct exemplar solutions. Exemplar solutions not only specify correct implementations but also provide correct code to replace buggy student code. Bugs in student code are repaired with heuristics that attempt to minimize the scope of repair. The automated debugging of student code is greatly complicated by the tremendous variability that arises in student solutions to nontrivial tasks. This variability can be coped with, and debugging performance improved, by explicit reasoning about computational semantics during the debugging process. This article supports these claims by discussing the design, implementation, and evaluation of Talus, an automatic debugger for LISP programs, and by examining related work in automated program debugging. Talus relies on its abilities to reason about computational semantics to perform algorithm recognition, infer code teleology, and to automatically detect and correct nonsyntactic errors in student programs written in a restricted, but nontrivial, subset of LISP. Solutions can vary significantly in algorithm, functional decomposition, role of variables, data flow, control flow, values returned by functions, LISP primitives used, and identifiers used. Solutions can consist of multiple functions, each containing multiple bugs. Empiricial evaluation demonstrates that Talus achieves high performance in debugging widely varying student solutions to challenging tasks. 相似文献
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The analysis of bug databases reveals that some software components are far more failure-prone than others. Yet it is hard to find properties that are universally shared by failure-prone components. We have mined the Eclipse bug and version databases to map failures to Eclipse components. The resulting data set lists the defect density of all Eclipse components, and may thus help to find features that predict how defect-prone a component will be. 相似文献
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Parallel execution of a programR (intuitively regarded as a partial order) is usually modeled by sequentially executing one of the total orders (interleavings)
into which it can be embedded. Our work deviates from this serialization principle by usingtrue concurrency to model parallel execution. True concurrency is represented via completions ofR tosemi total orders, called time diagrams. These orders are characterized via a set of conditions (denoted byCt), yielding orders or time diagrams which preserve some degree of the intended parallelism inR. Another way to express semi total orders is to use re-writing or derivation rules (denoted byCx) which for any programR generates a set of semi-total orders. This paper includes a classification of parallel execution into three classes according
to three different types ofCt conditions. For each class a suitableCx is found and a proof of equivalence between the set of all time diagrams satisfyingCt and the set of all terminalCx derivations ofR is devised. This equivalence between time diagram conditions and derivation rules is used to define a novel notion of correctness
for parallel programs. This notion is demonstrated by showing that a specific asynchronous program enforces synchronous execution,
which always halts, showing that true concurrency can be useful in the context of parallel program verification. 相似文献
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王敬宇 《计算机工程与科学》2003,25(3):86-89
并行调试在并行程序开发环境中非常重要。本文基于当前流行的并行计算机体系结构,为并行调试工具研究一种"一对多调试"组件,以此克服传统方法面对越来越大的MPP系统的不适应。 相似文献