The study of threshold voltage extraction of nitride spacer NMOS transistors in early stage hot carrier stress

Threshold voltage V/sub t/ extracted by g/sub m/-maximum extrapolation method under early stage hot carrier stress is proven to be an inappropriate method once electrons are trapped in a nitride spacer. The trapping of electrons in a nitride spacer increases the series drain resistance, reducing the transconductance g/sub m/ and the corresponding gate-to-source voltage V/sub gs/ at which peak g/sub m/ occurs. It ultimately decreases the threshold voltage V/sub t/ extracted by the g/sub m/-maximum extrapolation method. A novel algorithm is derived to determine the relationship between the measured data and the true threshold voltage of such a device under hot carrier stress by considering the effect of series resistance in g/sub m/-maximum extrapolation method.     

Characterization of bipolar snapback and breakdown voltage inthin-film SOI transistors by two-dimensional simulation

A two-dimensional finite-difference simulator for silicon-on-insulator (SOI) MOSFETs is presented. The simulator is derived from the MINIMOS4 simulator and incorporates additional features which permit the characterization of the bipolar snapback effect, which has been observed as a limiting feature in ultra-thin-film transistors. The snapback effect is illustrated as a hysteresis mechanism whereby, for a given bias condition, there are two different solutions to the semiconductor equations, depending on the starting condition. Examples of the application of the simulator to predict breakdown voltage in submicrometer devices are considered. Excellent agreement with measured values of breakdown voltage has been achieved for submicrometer n-channel transistors, both with and without the use of lightly doped drains     

Impact of preanneal process on threshold voltage of MOS transistors for trench DRAM

As the first step of DRAM manufacture, preanneal process plays an important role in determining the threshold voltage variation. It is found that the higher trans-1,2-dichloroethene flow in pad oxide growth and the higher nitrogen flow in high-temperature annealing step would respectively engender a lower boron segregation coefficient and higher nitridation of the oxide, both modify the boron distribution in the substrate and consequently the behavior of the threshold voltage. As the feature size of DRAM devices enter nanometer regime, besides gate oxidation, ion implantation and related thermal processes, the impact of preanneal process condition should be prudentially taken into consideration for rigorous control of the threshold voltage in the advanced DRAM production.     

Radiation effects of e-beam fabricated submicron NMOS transistors

This paper reports radiation effects of submicron NMOS devices fabricated by e-beam lithography. This study was initiated because e-beam lithography creates neutral traps in the gate oxides of MOS devices, which may make these devices more sensitive to radiation. Indeed, we have found that for radiation doses above 10 Krad, the threshold shift for an e-beam fabricated device is twice that for the corresponding device made by optical lithography. However, with the submicron process used here the threshold shift for both types of device is quite low (<100mV below 10 Krad), Moreover, there was no correlation observed between radiation sensitivity and device gate length.     

Relaxation effects in NMOS transistors after hot-carrier stressing

Aging studies on NMOS transistors with dry oxides at room temperature have revealed that the creation of interface traps and the trapping of positive charge in the oxide associated with hot-electron effects are not permanent, but can be reversed to some extent if the transistor drain is grounded and left for some time. The relaxation is a substantial fraction of the original degradation at low degradation values and suggests that there is an annealing of some of the traps created by stressing. This annealing follows first-order kinetics for both created interface traps and trapped oxide charge, and is characterized by relaxation times τrof 600-900 s.     

The influence of constructive parameters on the threshold voltage of nanodimensional p-Channel SOI MOS transistors

The influence of the thickness of the silicon film and hole concentration in the p-channel nanodimensional MOS transistor based on the SOI structure is considered. The formulas for the computation of these dependences are derived and graphic dependences are presented.     

Effects of high field stresses on threshold voltage of CMOS transistors

In this paper, the threshold voltage instabilities of CMOS transistors under gate bias stress at high gate oxide electric fields have been investigated. It is shown that in presence of the negative gate bias stress threshold voltage of n-channel MOSTs decreases, while threshold voltage of p-channel MOSTs increases. These results are explained by positive fixed oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps. On the other hand, it is shown that in the presence of the positive gate bias stress threshold voltage of n-channel MOSTs decreases at the beginning as well, but after a certain time period starts to increase, while threshold voltage of p-channel MOSTs continuously increases. The initial threshold voltage behaviour is explained by positive fixed oxide charge increase as well; however, in this case it is caused by the electron tunneling from oxide electron traps into oxide conduction band. The later threshold voltage increase of n-channel MOSTs is explained by surface state charge increase due to tunnel current flowing through the oxide.     

Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment

High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping level makes it possible to attain a threshold voltage of GaN transistors close to V _th = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to V _th = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.     

Quantum size impacts on the threshold voltage in nanocrystalline silicon thin film transistors

Based on the analysis of Poisson equation, an analytical threshold voltage model including quantum size effect of nc-TFTs (nanocrystalline silicon thin film transistor) has been proposed in this paper. The results demonstrate that the proposed simplified expression of threshold voltage agree perfectly with numerical calculation. The threshold voltage in nc-TFTs strongly depends on the size of silicon grain when the size of silicon grain is less than 20 nm. Such a strong dependent relation results from the large changes in the bandgap and dielectric constant due to quantum size effects when the size of silicon grain is in the regime of nano-scale. The theoretical investigation also demonstrates that the grain boundary trap density compared to the active dopant density gives a main contribution to the threshold voltage. This implies that the grain size must be larger than 30 nm in order to avoid threshold voltage variation from different technological processes.     

硅化物阻挡层对高压漏扩展MOS晶体管的影响

Silicide-block-film effects on drain-extended MOS （DEMOS） transistors were comparatively investigated, by means of different film stack stoichiometric SiO2 and silicon-rich oxide （SRO）. The electrical properties of the as-deposited films were evaluated by extracting source/drain series resistance. It was found that the block film plays a role like a field plate, which has significant influence on the electric field beneath. Similar to hot-carrier- injection （HCI） induced degradation for devices, the block film initially charged in fabrication process also strongly affects the device characteristics and limits the safe operating area.     

Silicide-block-film effects on high voltage drain-extended MOS transistors

Silicide-block-film effects on drain-extended MOS (DEMOS) transistors were comparatively investi-gated, by means of different film stack stoichiometric SiO2 and silicon-rich oxide (SRO). The electrical properties of the as-deposited films were evaluated by extracting source/drain series resistance. It was found that the block film plays a role like a field plate, which has significant influence on the electric field beneath. Similar to hot-cartier-injection (HCI) induced degradation for devices, the block film initially charged in fabrication process also strongly affects the device characteristics and limits the safe operating area.     

An SRAM design using dual threshold voltage transistors and low-power quenchers

Static random access memories (SRAM) are widely used in computer systems and many portable devices. In this paper, we propose an SRAM cell with dual threshold voltage transistors. Low threshold voltage transistors are mainly used in driving bit-lines while high threshold voltage transistors are used in latching data voltages. The advantages of dual threshold voltage transistors can be used to reduce the access time and maintain data retention at the same time. Also, the unwanted oscillation of the output bitlines of memories caused by large currents in bitlines is reduced by adding two back-to-back quenchers. The proposed quenchers not only prevent oscillation, but also reduce the idle power consumption when the memory cells are not activated by wordline signals. Meanwhile, a large noise margin is provided such that the gain of the sense amplifier will not be reduced to avoid the oscillation. Hence, high-speed and low-power readout operations of the SRAMs are feasible.     

Tradeoff between threshold voltage and breakdown in high-voltage double-diffused MOS transistors

The design of junction isolated DMOS transistors suitable for monolithic integration has been studied. The purpose of this correspondence is to describe one of the key tradeoffs when designing these devices for high breakdown voltages (200 V for our example). It is a tradeoff primarily between threshold voltage and the punchthrough voltage of the channel diffusion, however, the avalanche breakdown voltage, on-resistance, and source-to-substrate punchthrough voltage are also affected. As an example, the design of a device for 200-V operation is described. The discussion is, however, general and can be applied to other DMOS designs as well.     

Model for the temperature dependence of the threshold voltage of modulation-doped field-effect transistors

A model for the temperature dependence Of the threshold voltage of modulation-doped FET's caused by traps in doped AlGaAs is presented. The model takes into account the charge distribution in the depletion region determined by the temperature and time-dependent occupation of traps. The theory shows excellent agreement with experiment in the temperature range 77 to 400 K.     

Schottky-clamped NMOS transistors implemented in a conventional0.8-μm CMOS process

An 0.8-μm n-channel MOSFET with a TiSi₂-Si Schottky clamped drain-to-body junction (SCDR) and an n⁺ implanted standard source structure have been fabricated in a conventional 0.8-μm salicide CMOS process without any process modifications. The SCDR should be useful for reducing susceptibility for latch-up in integrated CMOS RF power amplifiers and switches where drain to p-substrate junctions can be forward biased during normal operations. Output I-V characteristics of the devices are the same as those of conventional MOSFETs, while parasitic lateral n⁺-drain/p-substrate/n⁺-source bipolar transistor measurements showed significantly reduced current gains because the Schottky barrier diode which does not inject minority carriers (electrons) to the p-substrate base clamps the n⁺ drain-to-p-substrate guard-ring diode connected in parallel     

Drain-voltage effects on the threshold voltage of a small-geometry MOSFET

Closed form analytical expressions are developed to predict the threshold voltage of a small geometry MOSFET with a nonzero drain voltage. Two expressions are developed. The first expression is for an abrupt oxide transition from the thin gate to thick field oxide with uniform doping and the second expression includes the effects of a tapered recessed field oxide, and field doping encroachment at the channel edges. The theory is compared with experimental results obtained from n-channel small geometry MOSFETs.     

Effect of Halo structure variations on the threshold voltage of a 22 nm gate length NMOS transistor

This paper reports on the effects of the Halo structure variations on threshold voltage (V_th) in a 22 nm gate length high-k/metal gate planar NMOS transistor. Since the V_th is one of the important physical parameter for determining the functionality of complementary metal-oxide–semiconductor device, this experiment will focus on finding the best combination on process parameter to achieve the best value of V_th. The Halo structure variable process parameters are the Halo implantation dose, the Halo implantation tilting angle, the Source/Drain implantation dose and the compensation implantation dose. The design of the planar device consists of a combination of high permittivity material (high-k) and a metal gate. Titanium dioxide was used as the high-k material instead of the traditional SiO₂ dielectric and tungsten silicide was used as the metal gate. The optimization process was executed using Taguchi's L₉ array to obtain a robust design. Taguchi's Nominal-the-Best signal-to-noise ratio was used in an effort to minimize the variance of V_th. The results show that the V_th values have least variance and the mean value can be adjusted to 0.289 V±12.7% which is in line with projections made by the International Technology Roadmap for Semiconductors.     

Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs

Quantum-mechanical (QM), or carrier energy-quantization, effects on the subthreshold characteristics, including the threshold voltage (V/sub t/), of generic undoped double-gate (DG) CMOS devices with ultrathin (Si) bodies (UTBs) are physically modeled. The analytic model, with dependences on the UTB thickness (t/sub Si/), the transverse electric field, and the UTB surface orientation, shows how V/sub t/ is increased, and reveals that 1) the subthreshold carrier population in higher-energy subbands is significant, 2) the QM effects in DG devices with {110}-Si surfaces, common in FinFETs, are comparable to those for {100}-Si surfaces for t/sub Si/>/spl sim/4 nm, 3) the QM effects can increase the gate swing, and (iv) the QM effects, especially for t/sub Si/相似文献