High-quality schottky and ohmic contacts in planar 4H-SiC metal semiconductor field-effect transistors and device performance

We have fabricated planar 4H-SiC, metal-semiconductor field-effect transistors (MESFETs) with high-quality metal/SiC contacts. To eliminate potential damage to the gate region caused by etching and simplify the device fabrication process, gate Schottky contacts were formed without any recess gate etching, and an ideality factor of 1.03 was obtained for these gate contacts. The interface state density between the contact metal and SiC was 5.7×10¹² cm⁻²eV⁻¹, which was found from the relationship between the barrier height and the metal work function. These results indicate that the interface was well controlled. Thus, a transconductance of 30 mS/mm was achieved with a 3-μm gate length as the performance figure of these MESFETs with high-quality metal/SiC contacts. Also, a low ohmic contact resistance of 1.2×10⁻⁶ Θcm² was obtained for the source and drain ohmic contacts by using ion implantation.     

Breakdown Voltage Enhancement of AlGaN/GaN High-Electron-Mobility Transistors via Selective-Area Growth for Ohmic Contacts over Ion Implantation

Selective-area growth (SAG) based on plasma-assisted molecular-beam epitaxy (PAMBE) was shown to facilitate improvement of Ohmic contacts and direct-current (DC) characteristics for GaN-based field-effect transistors (FETs) over the widely accepted ion-implantation technique. Twofold improvements in breakdown voltage were also demonstrated for samples grown on both sapphire and silicon substrates. An AlGaN/GaN high-electron-mobility transistor (HEMT) fabricated with PAMBE-SAG exhibited a low specific contact resistivity of 5.86 × 10⁻⁷ Ω cm², peak drain current of 420 mA/mm, and high breakdown voltage of 77 V. These results demonstrate that PAMBE-SAG is suited to fabricating HEMTs for high-power applications.     

Thin layer oxide in the drift region of Laterally double-diffused metal oxide semiconductor on silicon-on-insulator: A novel device structure enabling reliable high-temperature power transistors

In this paper a new lateral double diffused metal oxide semiconductor (LDMOS) transistor on silicon-on-insulator (SOI) technology is reported. In the proposed structure a trench oxide in the drift region is reformed to reduce surface temperature. In the LDMOS devices one way for achieving high breakdown voltage is incorporating the trench oxide in the drift region. But, this strategy causes high lattice temperature in the device. So, the middle of the trench oxide in the drift region is etched and filled with the silicon to have higher thermal conductivity material and reduce the lattice temperature in the drift region. The simulation with two-dimensional ATLAS simulator shows that the novel thin trench oxide in the n-drift region of LDMOS transistor (TT-LDMOS) have lower maximum lattice temperature with an acceptable breakdown voltage in respect to the conventional LDMOS (C-LDMOS) structure with the trench oxide in the drift region. So, TT-LDMOS can be a reliable device for power transistors.     

Properties of electrical contacts on bulk and epitaxial n-type ZnO

The electrical properties of several metal contacts to n-type ZnO (0001) were studied. The ZnO samples consisted of bulk single-crystal material, epitaxial layers on sapphire grown by molecular beam epitaxy (MBE), and polycrystalline thin films on sapphire obtained by pulsed laser deposition (PLD). Ohmic and rectifying contacts were observed dependent upon both the metal material and the ZnO surface. Ohmic contacts were characterized using the circular transmission line method (c-TLM), where contact resistivity was found to be in the range of 10⁻⁴−10⁻⁵ Ω-cm². Schottky behavior was observed using Ag contacts exhibiting varying leakage current and breakdown voltage dependent on the polarity of the ZnO surface.     

Large‐Area Schottky Barrier Transistors Based on Vertically Stacked Graphene–Metal Oxide Heterostructures

The fabrication of all‐transparent flexible vertical Schottky barrier (SB) transistors and logic gates based on graphene–metal oxide–metal heterostructures and ion gel gate dielectrics is demonstrated. The vertical SB transistor structure is formed by (i) vertically sandwiching a solution‐processed indium‐gallium‐zinc‐oxide (IGZO) semiconductor layer between graphene (source) and metallic (drain) electrodes and (ii) employing a separate coplanar gate electrode bridged with a vertical channel through an ion gel. The channel current is modulated by tuning the Schottky barrier height across the graphene–IGZO junction under an applied external gate bias. The ion gel gate dielectric with high specific capacitance enables modulation of the Schottky barrier height at the graphene–IGZO junction over 0.87 eV using a voltage below 2 V. The resulting vertical devices show high current densities (18.9 A cm^?2) and on–off current ratios (>10⁴) at low voltages. The simple structure of the unit transistor enables the successful fabrication of low‐power logic gates based on device assemblies, such as the NOT, NAND, and NOR gates, prepared on a flexible substrate. The facile, large‐area, and room‐temperature deposition of both semiconducting metal oxide and gate insulators integrates with transparent and flexible graphene opens up new opportunities for realizing graphene‐based future electronics.     

Bulk silicon technology for complementary MESFETs

A technology for fabrication of complementary silicon MESFETs on bulk silicon substrates has been developed. The technology is similar to CMOS technology, and utilises n-silicon substrates. P-wells are used for the n-channel devices. Device isolation was achieved by trench etching. The silicides of Er and Pt were used as gate Schottky contacts. P- and n-channel characteristics are presented together with subthreshold behaviour and preliminary results regarding radiation hardness. Also, results from two-dimensional simulations of the devices are presented.<>     

The future of power semiconductor device technology

Power electronic systems have benefited greatly during the past ten years from the revolutionary advances that have occurred in power discrete devices. The introduction of power metal-oxide-semiconductor field-effect transistors (MOSFETs) in the 1970s and the insulated gate bipolar transistors (IGBTs) in the 1980s enabled design of very compact high-efficiency systems due to the greatly enhanced power gain resulting from the high input impedance of these structures. Recently, significant improvements in the performance of silicon-power MOSFETs has been achieved by using innovative vertical structures with charge coupled regions. Meanwhile, silicon IGBTs continue to dominate the medium- and high-voltage application space sue to scaling of their voltage ratings and refinements to their gate structure achieved by using very large scale integration (VLSI) technology and trench gate regions. Research on a variety of MOS-gated thyristors has also been conducted, resulting in some promising improvements in the tradeoff between on-state power loss, switching power loss, and the safe-operating-area. Concurrent improvements in power rectifiers have been achieved at low-voltage ratings using Schottky rectifier structures containing trenches and at high-voltage ratings using structures that combine junction and Schottky barrier contacts. On the longer term, silicon carbide Schottky rectifiers and power MOSFETs offer at least another tenfold improvement in performance. Although the projected performance enhancements have been experimentally demonstrated, the defect density and cost of the starting material are determining the pace of commercialization of this technology at present     

The electrical characteristics of 4H-SiC schottky diodes after inductively coupled plasma etching

The electrical characteristics of metal contacts fabricated on 4H-SiC have been investigated. Sputtered nickel ohmic contacts have been successfully produced on untreated 4H-SiC substrates and 4H-SiC surfaces cleaned with aggressive chemicals and ion sputtering. The current-voltage (I–V) characteristics of asdeposited contacts are observed to be nonohmic on all surfaces. After annealing at 1,000°C in a N₂ atmosphere, the contacts are seen to become ohmic with considerably less annealing time being required for the samples exposed to aggressive cleaning stages. Schottky diodes were then produced on the silicon carbide (SiC) surface after etching in an SF₆/O₂ inductively coupled plasma (ICP) for 3 min at varying substrate bias voltages and also on an untreated surface used as a control sample. The ideality factors of all diodes formed on the etched surfaces increased in comparison to the control sample. The highest ideality factor was observed for the diodes produced after etching at −0-V and −245-V bias voltage. A two-diode and resistor model was applied to the results that successfully accounted for the excess leakage paths. The defect density of each SiC surface was calculated using both the measured and the simulated ideality factors. An annealing stage was successful at reducing the ideality factors of all the diodes formed. The defect density calculated using the measured ideality factors of the annealed diodes was seen to have been reduced by an order of magnitude.     

High-voltage operation of field-effect transistors in siliconcarbide

Buried-gate field-effect transistors with blocking voltages up to 600-700 V have been fabricated in 6H polytype silicon carbide using a trench technology. The devices achieve drain currents of up to 60 mA for a channel width of 0.72 mm and have a turn off gate voltage of about 40 V. We report on the device characteristics and analyze the performance under high-voltage device operation     

SiC power-switching devices-the second electronics revolution?

Silicon carbide (SiC) offers significant advantages for power-switching devices because the critical field for avalanche breakdown is about ten times higher than in silicon. SiC power devices have made remarkable progress in the past five years, demonstrating currents in excess of 100 A and blocking voltages in excess of 19000 V. In this paper we describe the latest progress in three classes of SiC devices: diodes (p-i-n and Schottky), transistors (junction field-effect transistor, metal-oxide-semiconductor field-effect transistor, and bipolar junction transistor), and thyristors (gate turn-off).     

The characteristics of an enhancement mode VFET

This paper describes a junction FET fabricated by adjusting the depth of a V-Groove anisotropically etched in a thick epitaxial silicon layer to obtain an enhancement mode device. A simple theory and experimental characteristics of the device are presented. The technique can be extended to the fabrication of Schottky barrier enhancement MESFETs for micropower digital applications.     

Influence of Field Plates and Surface Traps on Microwave Silicon Carbide MESFETs

The influence of field plates and surface traps on silicon carbide MESFETs for microwave operation was investigated. By increasing the length of gate-connected field plates from 50 to 800 nm, it was possible to increase the gate–drain breakdown voltage of the devices from 125 to 170 V. At the same time, the current slump effect of traps in the passivation oxide was reduced. By using a combination of field plates and a passivation oxide with low interface trap density, it was possible to reach an output power density of 8 W/mm at 3 GHz.      

High-breakdown characteristics of the InP-based heterostructurefield-effect transistor withIn0.34Al0.66As0.85Sb0.15Schottky layer

We report improved breakdown characteristics of InP-based heterostructure field-effect transistors (HFET's) utilizing In_0.34 Al_0.66As_0.85Sb_0.15 Schottky layer grown by low-pressure metalorganic chemical vapor deposition. Due to high energy bandgap and high Schottky barrier height (>0.73 eV) of the In_0.34Al_0.66As_0.85Sb_0.15 Schottky layer, high two-terminal gate-to-drain breakdown voltage of 40 V, three-terminal off-state breakdown voltage of 40 V three-terminal threshold-state breakdown voltage of 31 V, and three-terminal on-state breakdown voltage of 18 V at 300 K for In_0.75Ga_0.25As channel, are achieved. Moreover, the temperature dependence of two-terminal reverse leakage current is also investigated. The two-terminal gate-to-drain breakdown voltage is up to 36 V at 420 K. A maximum extrinsic transconductance of 216 mS/mm is obtained with a gate length of 1.5 μm     

SiC and GaN transistors - is there one winner for microwave power applications?

Wide bandgap semiconductors show promise for high-power microwave electronic devices. Primarily due to low breakdown voltage, it has not been possible to design and fabricate solid-state transistors that can yield radio-frequency (RF) output power on the order of hundreds to thousands of watts. This has severely limited their use in power applications. Recent improvements in the growth of wide bandgap semiconductor materials, such as SiC and the GaN-based alloys, provide the opportunity to now design and fabricate microwave transistors that demonstrate performance previously available only from microwave tubes. The most promising electronic devices for fabrication in wide bandgap semiconductors for these applications are metal-semiconductor field-effect transistors (MESFETs) fabricated from the 4H-SiC polytype and heterojunction field-effect transistors (HFETs) fabricated using the AlGaN/GaN heterojunction. These devices can provide RF output power on the order of 5-6 W/mm and 10-12 W/mm of gate periphery, respectively. 4H-SiC MESFETs should produce useful performance at least through X band and AlGaN/GaN HFETs should produce useful performance well into the millimeter-wave region, and potentially as high as 100 GHz.     

Fabrication of self-aligned graded junction termination extensions with applications to 4H-SiC P-N diodes

The properties of SiC make this wide band-gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices, such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc., all of which require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power-handling capabilities. In this paper, we describe a technique for fabricating a graded junction termination extension (GJTE) that is effective and self-aligned, a feature that simplifies the implantation process during fabrication and, therefore, has the potential to reduce production costs. Implanted anode p-n diodes fabricated using this technique on 10-μm thick n⁻ epitaxial layer had a maximum breakdown voltage of 1830 V. This was comparable to the ideal parallel-plane breakdown of 1900 V predicted by numerical simulation.     

Thin film deposition and microelectronic and optoelectronic devicefabrication and characterization in monocrystalline alpha and betasilicon carbide

The deposition of silicon carbide thin films and the associated technologies of impurity incorporation, etching, surface chemistry, and electrical contacts for fabrication of solid-state devices capable of operation at temperatures to 925 K are addressed. The results of several research programs in the United States, Japan and the Soviet Union, and the remaining challenges related to the development of silicon carbide for microelectronics are presented and discussed. It is concluded that the combination of α-SiC on α-SiC appears especially viable for device fabrication. In addition, considerable progress in the understanding of the surface science, ohmic and Schottky contacts, and dry etching have recently been made. The combination of these advances has allowed continual improvement in Schottky diode p-n junction, MESFET, MOSFET, HBT, and LED devices     

Fabrication approaches to ZnO nanowire devices

To date, most of the work on ZnO nanostructures has focused on the synthesis methods and there have been only a few reports of the electrical characteristics. We report on fabrication methods for obtaining device functionality from single ZnO nanorods. A key aspect is the use of sonication to facilitate transfer of the nanorods from the initial substrate on which they are grown to another substrate for device fabrication. Examples of devices fabricated using this method are briefly described, including metal-oxide semiconductor field effect depletion-mode transistors with good saturation behavior, a threshold voltage of ∼−3 V, and a maximum transconductance of order 0.3 mS/mm and Pt Schottky diodes with excellent ideality factors of 1.1 at 25°C and very low (1.5×10⁻¹⁰ A, equivalent to 2.35 Acm⁻², at −10 V) reverse currents. The photoresponse showed only a minor component with long decay times (tens of seconds) thought to originate from surface states. These results show the ability to manipulate the electron transport in nanoscale ZnO devices.     

A Novel Process for Fabricating High Density Trench MOSFETs for DC‐DC Converters

We propose a new process technique for fabricating very high‐density trench MOSFETs using 3 mask layers with oxide spacers and a self‐aligned technique. This technique reduces the device size in trench width, source, and p‐body region with a resulting increase in cell density and current driving capability as well as cost‐effective production capability. We were able to obtain a higher breakdown voltage with uniform oxide grown along the trench surface. The channel density of the trench DMOSFET with a cell pitch of 2.3‐2.4 µm was 100 Mcell/in² and a specific on‐resistance of 0.41 mΩ·cm² was obtained under a blocking voltage of 43 V.     

Junction breakdown instabilities in deep trench isolationstructures

Junction breakdown voltage instability in a p-n junction formed in bulk silicon adjacent to a deep trench filled with polysilicon was investigated. The structure investigated consists of a 5-μm-deep trench filled with heavily p-doped polysilicon. The trench is open at the bottom and is consequently shorted to the p-substrate. The time-dependent behavior of the walkout or the breakdown voltage instability is similar to that reported for planar p-n junctions terminating on surface oxide. Results suggest that trapping of holes in the trench sidewall dielectric is responsible for this phenomenon. The product of trapping center concentration and capture cross section N σ is estimated to be 90 cm^-1