SOI/bulk hybrid technology on SIMOX wafers for high performancecircuits with good ESD immunity

A new SOI/bulk hybrid technology with devices on both the thin film and the bottom substrate of SIMOX wafers has been studied. By fabricating ESD protection circuits on the substrate of SIMOX wafers, ESD reliability of high performance CMOS SOI circuits can be significantly improved. Despite the higher surface defect density and micro-roughness on the bottom substrate of SIMOX wafers compared to ordinary bulk wafers, similar electron mobility, intrinsic thermal oxide properties and hot-carrier degradation are observed among MOSFET's fabricated on the different substrates. Thus, the hybrid technology is capable of combining the advantages both of SOI and bulk technology in fabricating high performance circuits     

Body-contacted SOI MOSFET structure and its application to DRAM

A body-contacted (BC) SOI MOSFET structure without the floating-body effect is proposed and successfully demonstrated. The key idea of the proposed structure is that the field oxide does not consume the silicon film on buried oxide completely, so that the well contact can suppress the body potential increase in SOI MOSFET through the remaining silicon film between the field oxide and buried oxide. The junction capacitance of the proposed structure which ensures high-speed operation can also maintain that of the conventional thin-film SOI MOSFET at about 0.5 V. The measured device characteristics show the suppressed floating-body effect as expected. A 64 Mb SOI DRAM chip with the proposed BC-SOI structure has been also fabricated successfully. As compared with bulk MOSFET's, the proposed SOI MOSFET's have a unique degradation-rate coefficient that increases with increasing stress voltage and have better ESD susceptibility. In addition, it should be noted that the proposed SOI MOSFET's have a fully bulk CMOS compatible layout and process     

Hot-carrier effects in thin-film fully depleted SOI MOSFET's

Previous conflicting reports concerning fully depleted SOI device hot electron reliability may result from overestimation of channel electric field (E_m). Experimental results using SOI MOSFET's with body contacts indicate that E_m is just a weak function of thin-film SOI thickness (T_si and that E_m can be significantly lower than in a bulk device with drain junction depth (X _j) comparable to SOI's T_si. The theoretical correlation between SOI MOSFET's gate current and substrate current are experimentally confirmed. This provides a means (I_G) of studying E_m in SOI device without body contacts. Thin-film SOI MOSFET's have better prospects for meeting breakdown voltage and hot-electron reliability requirements than previously thought     

Measurement of I-V curves of silicon-on-insulator (SOI) MOSFET'swithout self-heating

A new method for measuring the output (I_D-V_D) characteristics of SOI MOSFET's without self-heating is described. The method uses short pulses with a low repetition rate, and a reverse transient loadline construction. The technique is demonstrated by measuring 0.25 μm bulk and SOI MOSFET's with 5-nm gate oxide. Application of the method to the extraction of device temperature as a function of DC power is also illustrated     

SOI NMOSFET沟道热载流子的应力损伤

研究了沟道热载流子应力所引起的SOI NMOSFET的损伤．发现在中栅压应力（Vg≈Vd／2）和高栅压应力（Vg≈Vd）条件下,器件损伤表现出单一的幂律规律;而在低栅压应力（Vgs≈Vth）下,多特性的退化规律便会表现出来．同时,应力漏电压的升高、应力时间的延续都会导致退化特性的改变．这使预测SOI器件的寿命变得非常困难．     

Deep-submicrometer channel design in silicon-on-insulator (SOI)MOSFET's

Short-channel effects in deep-submicrometer SOI MOSFET's are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness must be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 μm regime may favor partially depleted devices     

Deep-submicrometer channel design in silicon-on-insulator (SOI)MOSFET's

Short-channel effects in deep-submicrometer SOI MOSFET's are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness most be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 μm regime may favor partially depleted devices     

SOI MOSFET effective channel mobility

The standard bulk MOSFET definition for effective electric field is modified for SOI devices to account for nonzero electric field at the back oxide interface. The effective channel mobility in fully-depleted n-channel SOI MOSFET's is shown to be independent of applied backgate bias when the modified E_eff definition is used. The effective channel mobility as a function of E_eff is also shown to be independent of film thickness for fully-depleted devices     

Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).     

Lifetime reliability of thin-film SOI nMOSFET's

The dc device lifetime reliability of thin-film SOI MOSFET's is investigated over a wide range of drain stress from just below the SOI breakdown voltage up to typical accelerated stress voltages. Unique hot-carrier degradation behaviors were observed for different ranges of applied drain stress. The degradation behavior and mechanism are found to dynamically change from one type observed under low drain stress (realistic operation range) to a different type observed under high drain stress (strong breakdown operation). This causes the SOI MOSFET to exhibit a two slope lifetime versus reciprocal drain voltage behavior which could have strong implications on the hot-carrier stressing methodology and reliability study of these devices     

New hot-carrier-degradation mode in thin-film SOI nMOSFET's

A new hot-carrier degradation mode peculiar to MOSFET's fabricated on thin-film SOI is described. This degradation mode, which occurs in nMOSFET's more easily than in pMOSFET's, is due to suppression of parasitic bipolar action caused by recombination of excess carriers through hot-carrier-induced front interface-traps. Threshold voltage is significantly shifted by this phenomenon. The reliability lifetime defined by threshold voltage shift and drain current degradation is also discussed, considering the new degradation mode     

全耗尽SOI MOSFET及CMOS／SOI电路的研究

采用ＳＩＭＯＸ材料，研制了一种全耗尽ＣＭＯＳ／ＳＯＩ模拟开关电路，研究了全耗尽ＳＯＩ ＭＯＳ场效应晶体管的阈值电压与背栅偏置的依赖关系，对漏源击穿的Ｓｎａｐｂａｃｋ特性进行分析，介绍了薄层ＣＭＯＳ／ＳＩＭＯＸ制作工艺，给出了全耗尽ＣＭＯＳ／ＳＯＩ电路的测试结果。     

Transconductance of Silicon-on-insulator (SOI) MOSFET's

Transconductance of n-channel Silicon-on-Insulator (SOI) MOSFET's has been measured with backside gate (substrate) bias as a parameter. For negative values of the backside gate bias, transconductance of SOI transistors is similar to that of bulk devices. On the other hand, transconductance exhibits an unusual behavior when backside gate is positively biased. This is caused by mutual influence between the front-and the backside gate-related depletion zones. Modeling of transconductance using numerical solution of Poisson's equation show good agreement with experimental results.     

AC floating body effects and the resultant analog circuit issues insubmicron floating body and body-grounded SOI MOSFET's

We report the extensive study on ac floating body effects of different SOI MOSFET technologies. Besides the severe kink and resultant noise overshoot and degraded-distortion in partially depleted (PD) floating body SOI MOSFET's, we have investigated the residue ac floating body effects in fully depleted (FD) floating body SOI MOSFET's, and the different body contacts on PD SOI technologies. It is important to note that there is a universal correlation between ac kink effect and Lorentzian-like noise overshoot regardless of whether the body is floating or grounded. In addition, it was found that third-order harmonic distortion is very sensitive to floating body induced kink or deviation on output conductance due to the finite voltage drop of body resistance. These results provide device design guidelines for SOI MOSFET technologies to achieve comparable low-frequency noise and linearity with Bulk MOSFET's     

A new SOI inverter using dynamic threshold for low-powerapplications

A new SOI inverter using the dynamic threshold (DT) that lowers threshold voltage of MOSFET only in active operation of a logic circuit is proposed for high-speed and low-power applications. The dynamic threshold scheme is realized by dynamically biasing the body of MOSFET's. The SOI MOSFET's have been designed and fabricated to take full advantage of the reverse body effect which is affected by many device parameters. From the measurements and simulations, the proposed scheme is shown to be useful in the buffer with large load conditions and low supply voltage if the SOI MOSFET's are properly designed     

Advanced technologies for optimized sub-quarter-micrometer SOI CMOSdevices

Two manufacturable technologies of fully-depleted (FD) thin-film silicon-on-insulator (SOI) MOSFET's for low-power applications are proposed in this paper. To maintain high current drive while aggressively thinning down the SOI film, silicide is to be formed on Ge-damaged silicon layers. Ge preamorphization facilitates silicide formation at low temperature (~450°C) and effectively controls the silicide depth without void formation. It also reduces the floating body effect. In addition, a reliable gate work-function engineering is introduced for good threshold voltage management. A p⁺SiGe/Si stack gate alleviates the threshold voltage instability of SOI due to film thickness nonuniformity and broadens the design window for channel doping. These advanced technologies, compatible with existing bulk CMOS technology, are integrated into SOI CMOS process. Excellent electrical device results are presented     

An AC conductance technique for measuring self-heating in SOIMOSFET's

In this paper, we present a new technique for isolating the electrical behavior of an SOI MOSFET's from the self-heating effect using an AC conductance method. This method reconstructs an I-V curve by integrating high frequency output conductance data. The heating effect is eliminated when the frequency is much higher than the inverse of the thermal time constant of the SOI device. We present measurement results from SOI MOSFET's that demonstrate that heating can indeed be significant in SOI devices     

Electron and hole mobility enhancement in strained-Si MOSFET's onSiGe-on-insulator substrates fabricated by SIMOX technology

We have newly developed strained-Si MOSFET's on a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology. Their electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFET's. Using an epitaxial regrowth technique of a strained-Si film on a relaxed-Si_0.9Ge_0.1 layer and the conventional SIMOX process, strained-Si (20 nm thickness) layer on fully relaxed-SiGe (340 nm thickness)-on-buried oxide (100 nm thickness) was formed, and n-and p-channel strained-Si MOSFET's were successfully fabricated. For the first time, the good FET characteristics were obtained in both n-and p-strained-SOI devices. It was found that both electron and hole mobilities in strained-SOI MOSFET's were enhanced, compared to those of control SOI MOSFET's and the universal mobility in Si inversion layer     

A low thermal budget self-aligned Ti silicide technology usinggermanium implantation for thin-film SOI MOSFET's

In this paper, a titanium salicide technology with a very low thermal annealing temperature using germanium implantation for thin film SOI MOSFET's is investigated in detail. Ti silicide formation on the amorphous silicon generated by germanium implantation is studied. Compared to the conventional Ti salicide process, the Ti silicidation temperature is significantly lowered and the silicide depth is well controlled through the pre-amorphized layer. Therefore, the potential problems of the salicide process for SOI MOSFET's such as lateral voids, dopant segregation, thermal agglomeration, and increase of resistance on narrow gate are suppressed by germanium implantation. With the Ge pre-amorphization salicide process, a very low silicide contact resistance is obtained and sub-0.25-μm SOI MOSFET's are fabricated with good device characteristics     

A thorough investigation of the degradation induced by hot-carrierinjection in deep submicron N- and P-channel partially and fullydepleted unibond and SIMOX MOSFETs

A thorough investigation of hot-carrier effects in deep submicron N- and P-channel SOI MOSFET's is reported in this paper. First, a comparison of device aging among three types of SOI devices fabricated by various technologies is shown. The carrier type, the quality of oxides, and the device structure are key parameters for the degradation mechanisms in these devices. On the other hand, the worst-case aging (V _d=V_t,V_d/2 or V_d) also depends on these device distinctions. For fully depleted SOI MOSFETs, the variation of the main electrical parameters is determined with and without the influence of defects in the buried oxide. The device lifetime of NMOS/SOI in the worst-case condition is carefully predicted using accurate methods that take into account the degradation saturation and the region of defect creation (Si/SiO₂ interface and/or oxide volume). Finally, an investigation of the aging/recovery mechanisms is carried out in P-channel SOI MOSFETs under an alternating stress