A synchronous microsystem process using a dual-cylinder tool for the surface microstructures from solar cell silicon wafers

The low yield of active epoxy and Si₃N₄ microstructure layers is an important factor in semiconductor production. This study investigates a synchronous removal process using a newly designed dual-cylinder micro electromachining (μ-ECM) tool. This method of removing defective layers from solar cell silicon wafers can replace the current ones that employ strong acid and mechanical grinding. Grinding can damage the physical structure of silicon wafers and acid treatment is a source of environmental pollution. A high rate of epoxy film removal can be achieved with a short dual-cylinder anode used with a small gap between the tool and the silicon wafer surface. A thin anode also corresponds to a higher rate of epoxy film removal. Small diameter cathode cylinders also provide more discharge space and with a higher current give a better removal effect. The precise engineering technology used in this approach provides a clean and efficient recycling process that removes surface microstructure from defective solar cell silicon wafers to put them back into production with a resulting reduction of cost and environmental pollution.     

Wavelet-based defect detection in solar wafer images with inhomogeneous texture

Solar power is an attractive alternative source of electricity. Multicrystalline solar cells dominate the market share owing to their lower manufacturing costs. The surface quality of a solar wafer determines the conversion efficiency of the solar cell. A multicrystalline solar wafer surface contains numerous crystal grains of random shapes and sizes in random positions and directions with different illumination reflections, therefore resulting in an inhomogeneous texture in the sensed image. This texture makes the defect detection task extremely difficult. This paper proposes a wavelet-based discriminant measure for defect inspection in multicrystalline solar wafer images.The traditional wavelet transform techniques for texture analysis and surface inspection rely mainly on the discriminant features extracted in individual decomposition levels. However, these techniques cannot be directly applied to solar wafers with inhomogeneous grain patterns. The defects found in a solar wafer surface generally involve scattering and blurred edges with respect to clear and sharp edges of crystal grains in the background. The proposed method uses the wavelet coefficients in individual decomposition levels as features and the difference of the coefficient values between two consecutive resolution levels as the weights to distinguish local defects from the crystal grain background, and generates a better discriminant measure for identifying various defects in the multicrystalline solar wafers. Experimental results have shown the proposed method performs effectively for detecting fingerprint, contaminant, and saw-mark defects in solar wafer surfaces.     

硅片键合界面的应力研究

本文主要研究硅片直接键合界面结构与应力大小.当抛光硅片直接键合时,界面出现极薄的过渡区,并存在微小的晶向差,但不引起多余应力.当热生长了二氧化硅层的硅片相键合时,界面存在二氧化硅层,并引起张应力,其大小与硅二氧化硅系统应力大小相当.     

Causal modelling of semiconductor fabrication

Semiconductor fabrication is the manufacturing process by which wafers of silicon are turned into integrated circuits. Reasoning about how wafers are affected by fabrication operations is an important aspect in getting computers to aid in the diagnosis of manufacturing faults and in the design of new fabrication processes. Our research has been aimed at characterizing the knowledge needed to construct qualitative, causal models that can support diagnosis and design of the processes by which semiconductors are manufactured. This article presents our models of wafer structure and the operations that are used in semiconductor fabrication, and describes how a domain-independent simulator uses these models to determine how the operations affect the wafer structure. We also demonstrate how the causal dependencies recorded by the simulator can be used to diagnose manufacturing faults. We conclude with a comparison of our method of using discrete, causal models to other methods of modelling semiconductor fabrication.     

Glass Blowing on a Wafer Level

A fabrication process for the simultaneous shaping of arrays of glass shells on a wafer level is introduced in this paper. The process is based on etching cavities in silicon, followed by anodic bonding of a thin glass wafer to the etched silicon wafer. The bonded wafers are then heated inside a furnace at a temperature above the softening point of the glass, and due to the expansion of the trapped gas in the silicon cavities the glass is blown into three-dimensional spherical shells. An analytical model which can be used to predict the shape of the glass shells is described and demonstrated to match the experimental data. The ability to blow glass on a wafer level may enable novel capabilities including mass-production of microscopic spherical gas confinement chambers, microlenses, and complex microfluidic networks     

Micro-crack inspection in heterogeneously textured solar wafers using anisotropic diffusion

This paper proposes a machine vision scheme for detecting micro-crack defects in solar wafer manufacturing. The surface of a polycrystalline silicon wafer shows heterogeneous textures, and the shape of a micro-crack is similar to the multi-grain background. They make the automated visual inspection task extremely difficult.     

Room-Temperature Sealing of Microcavities by Cold Metal Welding

In this paper, we present a wafer-to-wafer attachment and sealing method for wafer-level manufacturing of microcavities using a room-temperature bonding process. The proposed attachment and sealing method is based on plastic deformation and cold welding of overlapping metal rings to create metal-to-metal bonding and sealing. We present the results from experiments using various bonding process parameters and metal sealing ring designs including their impact on the resulting bond quality. The sealing properties against liquids and vapor of different sealing ring structures have been evaluated for glass wafers that are bonded to silicon wafers. In addition, wafer-level vacuum sealing of microcavities was demonstrated when bonding a silicon wafer to another silicon wafer with the proposed room-temperature sealing and bonding technique.$hfill$ [2008-0053]      

基于局部与非局部线性判别分析和高斯混合模型动态集成的晶圆表面缺陷探测与识别

在复杂的半导体制造过程中,晶圆生产经过薄膜沉积、蚀刻、抛光等多项复杂的工序,制造过程中的异常波动都可能导致晶圆缺陷产生.晶圆表面的缺陷模式通常反映了半导体制造过程的各种异常问题,生产线上通过探测和识别晶圆表面缺陷,可及时判断制造过程故障源并进行在线调整,降低晶圆成品率损失.本文提出了基于一种流形学习算法与高斯混合模型动态集成的晶圆表面缺陷在线探测与识别模型.首先该模型开发了一种新型流形学习算法——局部与非局部线性判别分析法(Local and nonlocal linear discriminant analysis, LNLDA),通过融合数据局部/非局部信息以及局部/非局部惩罚信息,有效地提取高维晶圆特征数据的内在流形结构信息,以最大化数据不同簇样本的低维映射距离,保持特征数据中相同簇的低维几何结构.针对线上晶圆缺陷产生的随机性和复杂性,该模型对每种晶圆缺陷模式构建相应的高斯混合模型(Gaussian mixture model, GMM),提出了基于高斯混合模型动态集成的晶圆缺陷在线探测与识别方法.本文提出的模型成功地应用到实际半导体制造过程的晶圆表面缺陷在线探测与识别,在WM-811K晶圆数据库的实验结果验证了该模型的有效性与实用性.     

Ultra thin ICs and MEMS elements: techniques for wafer thinning,stress-free separation,assembly and interconnection

 Ultra thin chips with a thickness below 30 μm offer low system height, low topography and show enhanced mechanical flexibility. These properties enable diverse use possibilities and new applications. However, advanced wafer thinning, adapted assembly and interconnection methods are required for this technology. A new process scheme is proposed that allows manufacturing of ultra thin fully processed wafers. Secure handling is achieved by means of carrier substrates using reversible adhesive tapes for connection of support and device wafers. Well established backgrinding and etching techniques are used for wafer thinning. To avoid mechanical damage of thin ICs the “Dicing-by-Thinning” (DbyT) concept is introduced to process flow. Best results are obtained when preparing dry etched chip grooves at front side of device wafer and opening these trenches during backside thinning. The new process scheme was also applied to wafers with highly topographic surfaces. Results of 40 μm thin wafers with 15 μm high Nickel bumps are presented. Three different assembly methods are described, interconnection through the thin chip, face down assembly and isoplanar contacting. Received: 6 July 2001/Accepted: 26 February 2002 The authors would like to thank M. Küchler (IZM Chemnitz) for preparing and performing trench etching process and A. Ostmann (IZM Berlin) for performance of nickel bumping process. This paper was presented at the Conference of Micro System Technologies 2001 in March 2001.     

Nanoscale Pattern Definition on Nonplanar Surfaces Using Ion Beam Proximity Lithography and Conformal Plasma-Deposited Resist

Ion beam proximity lithography (IBL) is a technique where a broad beam of energetic light ions floods a stencil mask and transmitted beamlets transfer the mask pattern to resist on a substrate. With a depth-of-field up to 20000 times larger than the minimum feature size and the high-throughput potential of a parallel exposure tool, IBL is very attractive for prototyping and manufacturing nanoelectromechanical systems over the steep topography of micromachined silicon wafers. This paper reports a conformal resist coating process that unlocks this potential. This negative-tone resist, plasma-polymerized methyl methacry- late, has a sensitivity of 27 muC/cm² and a contrast of 1.3 for 30-keV He⁺ ion exposures and amyl acetate developer. Sub-100-nm features have been printed down the sidewall and across a membrane at the bottom of a 500-mum-deep anisotropically etched pit in a silicon wafer. Pattern fidelity is near 2 nm for 10-nm features. Lines have also been formed on unpolished substrates, including rolled titanium foils and coarse-ground silicon wafers. Patterns on ground silicon have been etched into the surface using a nickel hard mask and SF₆/O₂ reactive ion etching.     

Low temperature silicon direct bonding for application in micromechanics: bonding energies for different combinations of oxides

Plain or structured hydrophillic silicon wafers covered with native oxide or with thermally grown oxide layers have been directly bonded at room temperature; afterwards, the samples were annealed at 100°C to 400°C. There is a significant difference in the observed bonding energy depending on the wafer pairing chosen. If one or both wafers are covered with a native oxide layer, high bonding strengths are reached even at low temperatures. This can be explained by the different diffusion behaviour of water molecules through a thick thermal oxide layer on one hand, and through a thin native oxide layer on the other hand. Two different methods for the activation of the wafer surfaces just prior to bonding are described.     

Arrays of monocrystalline silicon micromirrors fabricated using CMOS compatible transfer bonding

In this paper, we present CMOS compatible fabrication of monocrystalline silicon micromirror arrays using membrane transfer bonding. To fabricate the micromirrors, a thin monocrystalline silicon device layer is transferred from a standard silicon-on-insulator (SOI) wafer to a target wafer (e.g., a CMOS wafer) using low-temperature adhesive wafer bonding. In this way, very flat, uniform and low-stress micromirror membranes made of monocrystalline silicon can be directly fabricated on top of CMOS circuits. The mirror fabrication does not contain any bond alignment between the wafers, thus, the mirror dimensions and alignment accuracies are only limited by the photolithographic steps. Micromirror arrays with 4/spl times/4 pixels and a pitch size of 16 /spl mu/m/spl times/16 /spl mu/m have been fabricated. The monocrystalline silicon micromirrors are 0.34 /spl mu/m thick and have feature sizes as small as 0.6 /spl mu/m. The distance between the addressing electrodes and the mirror membranes is 0.8 /spl mu/m. Torsional micromirror arrays are used as spatial light modulators, and have potential applications in projection display systems, pattern generators for maskless lithography systems, optical spectroscopy, and optical communication systems. In principle, the membrane transfer bonding technique can be applied for integration of CMOS circuits with any type of transducer that consists of membranes and that benefits from the use of high temperature annealed or monocrystalline materials. These types of devices include thermal infrared detectors, RF-MEMS devices, tuneable vertical cavity surface emitting lasers (VCSEL) and other optical transducers.     

Alternative technology used to manufacture semitransparent monocrystalline silicon solar cells

This paper presents the manufacturing technology of a new semitransparent solar cell that can be used for building integrated applications. Diluted tetramethylammonium hydroxide and isopropyl alcohol mixture is used to create uniform and reproducible pyramidal textures on the silicon wafers, thus reducing surface reflectance. Arbitrary pattern of holes can be etched using 5 wt % tetramethylammonium hydroxide solution. Ammonium persulfate powder has to be dissolved in the bulk etchant in order to maintain a stable 1.34 μm/min etching rate over the 3.5 h etching process. The ARC layer is the 90 nm thick silicon dioxide remaining after the anisotropic etching. The efficiency of the semitransparent solar cell is 6.12 % including grid contact and silicon through-hole areas, the transparency reached is 6.7 %, weighted surface reflectance is 4.31 %.     

Development of expert decision model to monitor precision of solar silicon wafer machine line

In this study, we develop a two-stage decision model for managing uncertainty and imprecision of solar silicon wafer slicing evaluations during a wafer manufacturing process. Stage 1 is the evaluation process, which is performed by a procedure based on a combination of the fuzzy analytic hierarchy process (AHP) and the TOPSIS method. Stage 2 is the verification process, in which process capability indices are calculated to verify the feasibility and effectiveness of the proposed methods.     

Development of expert decision model to monitor precision of solar silicon wafer machine line

In this study, we develop a two-stage decision model for managing uncertainty and imprecision of solar silicon wafer slicing evaluations during a wafer manufacturing process. Stage 1 is the evaluation process, which is performed by a procedure based on a combination of the fuzzy analytic hierarchy process (AHP) and the TOPSIS method. Stage 2 is the verification process, in which process capability indices are calculated to verify the feasibility and effectiveness of the proposed methods.     

Bonded thick film SOI with pre-etched cavities

We have studied direct bonding and thinning of pre-etched silicon wafers. Silicon-on-insulator (SOI) substrates with pre-etched cavities provide freedom to MEMS design and enable manufacturing of advanced sensor structures (sensor structures that would be difficult or impossible with conventional substrates). Cavities with different shapes and sizes were etched on to the handle wafers. The etched handle wafers were bonded to unpatterned cap wafers in air or in vacuum. The bonding quality was evaluated with scanning acoustic microscopy and with HF-etching test. After bonding, the cap wafers were thinned down with grinding and polishing. The thickness variation of silicon diaphragm over the cavities was evaluated with cross-sectional SEM. The deflection of the Si film was measured with surface profilometry. To decrease the deflection and the thickness variation of the film, different support structures were placed inside the cavities.The bonding experiments carried out with patterned wafers showed that vacuum bonding results in slightly higher bonding energy than bonding in air. With large cavity fraction (80% of total wafer area), the air bonded samples had large void on the bonded interface. With smaller cavity fractions or with vacuum bonded samples, no such voids were found. Thinning studies showed that the thickness variation of the silicon diaphragm increases with increasing cavity dimensions and with decreasing SOI layer thickness. Thickness variation can be reduced with support structures under the Si membrane.     

Flexible integration of MEMS and IC for low-cost production of wireless sensor nodes

In this paper, we proposed a flexible process for size-free MEMS and IC integration with high efficiency for MEMS ubiquitous applications in wireless sensor network. In this approach, MEMS and IC can be fabricated individually by different wafers. MEMS and IC known-good-dies (KGD) are temporarily bonded onto carrier wafer with rapid and high-accurate self-alignment by using fine pattern of hydrophobic surface assembled monolayer and capillary force of H₂O; and then KGD are de-bonded from carrier wafer and transferred to target wafer by wafer level permanent bonding with plasma surface activation to reduce bonding temperature and load force. By applying above 2-step process, size of both wafer and chip could be flexible selected. Besides, CMOS processed wafer or silicon interposer can be used as the target wafer. This approach offers us excellent process flexibilities for low-cost production of wireless sensor nodes.     

Room temperature bonding for vacuum applications: climatic and long time tests

A detailed and quantitative motivation for the necessity of room temperature (RT) bonding for wafer level packaging of silicon micro-mirrors will be given. Results on RT 6 inch wafer bonding with vacuum encapsulation on test structures are presented. Structured as well as unstructured wafers have been bonded at RT using a Mitsubishi Heavy Industries bonder. Unstructured wafers were used for the determination of the bonding strength, whereas the structured wafers were used for the evaluation of vacuum level and its stability with time.     

Through wafer via holes manufacturing by variable isotropy Deep RIE process for RF applications

This paper reports a method on the manufacturing of through silicon wafer via holes with tapered walls by Deep Reactive Ion Etching using the opportunity to change the isotropy in the DRIE equipments during processing. By using consecutively anisotropic and isotropic etching steps it is possible to enlarge the dimension of via holes on one side of the wafer, while on the other side dimension is set by the initial etching window. The optimized process was used to obtain via’s with a good control over the walls angles for two etching windows sizes (100 and 20?μm respectively) on 300?μm thick silicon wafers. After process optimization, a deviation smaller than 10% of the manufactured via holes across the wafers was observed for the designed walls angles of 11.3° and 21.8°. Barrier and seed layers were deposited in via’s performed by Physical Vapor Deposition techniques with a very good coverage of the walls. Finally, gold electroplating was used to fill the narrow part of via’s.     

Mechanical and electrical bonding between silicon wafer and glass wafer with etched channels containing metal tracks

In this paper a novel process to bond and, at the same time, to electrically connect a silicon wafer to a glass wafer is presented. It consists of a low temperature anodic bonding process between silicon and glass by using a glass wafer with etched channels in order to contain metal tracks. The glass-to-silicon anodic bonding process at low temperatures (not exceeding 300°C) assures a strong mechanical link (Berthold et al. in Transducers 1999, June:7–10, 1999). The electrical contacts between the metal pads on the backside of a silicon wafer and the metal pads on the glass wafer are achieved by sintering and diffusion of metals due to a kind of thermo compression bonding. This bonding method permits a high vertical control due to a well-controlled etching of the cavity depth and to the thickness precision of both metallization (pads on silicon wafers and metal tracks on glass wafer). This IC-processing compatible approach opens up the way to a new electrical connection concept keeping, at the same time, a strong mechanical bond between glass and silicon wafers for an easier fabrication of a more complex micro-system.