Use of WN/sub X/ as the diffusion barrier for interconnect copper metallization of InGaP-GaAs HBTs

Use of WN/sub X/ as the diffusion barrier for interconnect copper metallization of InGaP-GaAs heterojunction bipolar transistors (HBTs) was studied. The WN/sub X/ (40 nm) and Cu (400 nm) films were deposited sequentially on the InGaP-GaAs HBT wafers as the diffusion barrier and interconnect metallization layer, respectively, using the sputtering method. As judged from the data of scanning electron microscopy, X-ray diffraction, Auger electron spectroscopy, and sheet resistance, the Cu--WN/sub X/--SiN and Cu--WN/sub X/--Au structures were very stable up to 550/spl deg/C and 400/spl deg/C annealing, respectively. Current accelerated stress test was conducted on the Cu--WN/sub X/ metallized HBTs with V/sub CE/=2 V, J/sub C/=140 kA/cm/sup 2/ and stressed for 55 h, the current gain (/spl beta/) of these HBTs showed no degradation and was still higher than 100 after the stress test. The Cu--WN/sub X/ metallized HBTs were also thermally annealed at 250/spl deg/C for 25 h and showed no degradation in the device characteristics after the annealing. For comparison, HBTs with Au interconnect metallization were also processed, and these two kinds of devices showed similar characteristics after the stress tests. From these results, it is demonstrated that WN/sub X/ is a good diffusion barrier for the interconnection copper metallization of GaAs HBTs.     

Si interlayer passivation on germanium MOS capacitors with high-/spl kappa/ dielectric and metal gate

We have demonstrated the advantages of silicon interlayer passivation on germanium MOS devices, with CVD HfO/sub 2/ as the high-/spl kappa/ dielectric and PVD TaN as the gate electrode. A silicon interlayer between a germanium substrate and a high-/spl kappa/ dielectric, deposited using SiH/sub 4/ gas at 580/spl deg/C, significantly improved the electrical characteristics of germanium devices in terms of low D/sub it/ (7/spl times/10/sup 10//cm/sup 2/-eV), less C- V hysteresis and frequency dispersion. Low leakage current density of 5/spl times/10/sup -7/ A/cm/sup 2/ at 1 V bias with EOT of 12.4 /spl Aring/ was achieved. Post-metallization annealing caused continuing V/sub fb/ positive shift and J/sub g/ increase with increased annealing temperature, which was possibly attributed to Ge diffusion into the dielectric during annealing.     

Cu contact on NiSi/Si with thin Ru/TaN barrier

Thin Ru(5 nm)/TaN(15 nm) bi-layer was sputtered on the NiSi/Si substrate as a diffusion barrier in the copper contact structure. The barrier properties were investigated through X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM), energy dispersive X-ray (EDX) and electrical measurement. The whole Cu/Ru/TaN/NiSi/Si structure has a good thermal stability until after annealing at 450 °C. The Schottky barrier measurement shows that the leakage current increases after 450 °C annealing and after 500 °C annealing the barrier fails. Failure mechanism of the barrier stack is discussed.     

Enhancing the reliability of n-p junction diodes using plasma treated tantalum barrier film

The properties of Ta barrier films treated with various plasma nitridations have been investigated by Cu/barrier/Si. An amorphous layer is formed on Ta barrier film after plasma treatments. The thickness of the amorphous layer is about 3 nm. Plasma treated Ta films possess better barrier performance than sputtered Ta and TaN films. It is attributed to the formation of a new amorphous layer on Ta surface after the plasma treatment. Cu/Ta(N,H)/Ta (10 nm)/Si remained stable after annealing at 750 °C. Ta(N,H)/Ta possesses the best thermal stability and excellent electrical properties. Cu/Ta/n⁺-p and Cu/Ta(N,O)/Ta/n⁺-p diodes resulted in large reverse-bias junction leakage current after annealing at 500 °C and 600 °C, respectively. On the other hand, Ta(N,H)/Ta and Ta(N)/Ta diffusion barriers improve the thermal stability of junction diodes to 650 °C. Ta(N,H)/Ta barrier film possesses lowest resistivity among Ta, Ta(N,O)/Ta, and Ta(N)/Ta films. Hydrogen plays an important role in enhancement of barrier properties. It is believed that hydrogen not only induces amorphization on Ta, but also eliminates the oxygen in the film. It is believed that the enhancement of ability against the copper diffusion is due to the combined effects of the hydrogen reaction and nitridation.     

Effect of the composition on the electrical properties of TaSi/sub x/N/sub y/ metal gate electrodes

In this letter, the effect of silicon and nitrogen on the electrical properties of TaSi/sub x/N/sub y/ gate electrode were investigated. The TaSi/sub x/N/sub y/ films were deposited on SiO/sub 2/ using reactive cosputtering of Ta and Si target in Ar and N/sub 2/ ambient. The thermal stability of TaSi/sub x/N/sub y//SiO/sub 2//p-type Si stacks was evaluated by measuring the flatband voltage and equivalent oxide thickness at 400/spl deg/C and 900/spl deg/C in Ar. It was found that under high temperature anneals, Si-rich TaSi/sub x/N/sub y/ films increased and this was attributed to the formation of a reaction layer at the electrode-dielectric interface. Reducing the Si content alone did not prevent the formation of this reaction layer while removing Si completely by utilizing TaN resulted in work functions that were too high. The presence of both Si and N was deemed necessary and their content was critical in obtaining optimized TaSi/sub x/N/sub y/ gates that are suitable for NMOS devices.     

Fully silicided NiSi gate on La/sub 2/O/sub 3/ MOSFETs

We have fabricated the fully silicided NiSi on La/sub 2/O/sub 3/ for n- and p-MOSFETs. For 900/spl deg/C fully silicided CoSi/sub 2/ on La/sub 2/O/sub 3/ gate dielectric with 1.5 nm EOT, the gate dielectric has large leakage current by possible excess Co diffusion at high silicidation temperature. In sharp contrast, very low gate leakage current density of 2/spl times/10/sup -4/ A/cm/sup 2/ at 1 V is measured for 400/spl deg/C formed fully silicided NiSi and comparable with Al gate. The extracted work function of NiSi was 4.42 eV, and the corresponding threshold voltages are 0.12 and -0.70 V for respective n- and p-MOSFETs. Electron and hole mobilities of 156 and 44 cm/sup 2//V-s are obtained for respective n- and p-MOSFETs, which are comparable with the HfO/sub 2/ MOSFETs without using H/sub 2/ annealing.     

Reliability of multistacked tantalum-based structure as the barrier film in ultralarge-scale integrated metallization

Diffusion barrier properties of Ta films with and without plasma treatments have been investigated in the study. The nitrogen-incorporated Ta films were prepared by NH₃ plasma treatment or reactive sputtering. Barrier properties were evaluated by sheet resistance, X-ray diffraction, transmission electron microscopy, X-ray photoelectron spectroscopy and reverse-biased junction leakage current. An amorphous-like TaN_x layer was formed on Ta barrier film after plasma treatments. The thickness of the amorphous TaN_x layer is about 3 nm and NH₃ plasma-treated Ta films (TaN_x/Ta) possess lower resistivity and smaller grain sizes. The Cu/TaN_x/Ta(10 nm)/Si remained stable after annealing at 750 °C for 1 h. NH₃ plasma-treated Ta films (TaN_x/Ta) possess better thermal stability than Ta and TaN films. It is attributed to the formation of a new amorphous layer on the surface of Ta film after the plasma treatments. For thermal stability of Cu/Ta(-N)/n⁺-p diodes, Cu/Ta/n⁺-p and Cu/TaN/n⁺-p junction diodes resulted in large reverse-bias junction leakage current after annealing at 500 and 525 °C, respectively. On the other hand, TaN_x/Ta diffusion barriers will improve the integrity of Cu/Ta(-N)/n⁺-p junction diodes to 650 °C.     

Integrity of copper–hafnium,hafnium nitride and multilayered amorphous-like hafnium nitride metallization under various thickness

The barrier properties and failure mechanism of sputtered Hf, HfN and multilayered HfN/HfN thin films were studied for the application as a Cu diffusion barrier in metallization schemes. The barrier capability and thermal stability of Hf, HfN and HfN/HfN films were determined using X-ray diffraction (XRD), leakage current density, sheet resistance (R_s) and cross-sectional transmission electron microscopy (XTEM). The thin multi-amorphous-like HfN thin film (10 nm) possesses the best barrier capability than Hf (50 nm) and amorphous-like HfN (50 nm). Nitrogen incorporated Hf films possess better barrier performance than sputtered Hf films. The Cu/Hf/n⁺–p junction diodes with the Hf barrier of 50 nm thickness were able to sustain a 30-min thermal annealing at temperature up to 500 °C. Copper silicide forms after annealing. The Hf barrier fails due to the reaction of Cu and the Hf barrier, in which Cu atoms penetrate into the Si substrate after annealing at high temperature. The thermal stabilities of Cu/Hf/n⁺–p junction diodes are enhanced by nitrogen incorporation. Nitrogen incorporated Hf (HfN, 50 nm) diffusion barriers retained the integrity of junction diodes up to 550 °C with lower leakage current densities. Multilayered amorphous-like HfN (10 nm) barriers also retained the integrity of junction diodes up to 550 °C even if the thickness is thin. No copper–hafnium and copper silicide compounds are found. Nitrogen incorporated hafnium diffusion barrier can suppress the formation of copper–hafnium compounds and copper penetration, and thus improve the thermal stability of barrier layer. Diffusion resistance of nitrogen-incorporated Hf barrier is more effective. In all characterization techniques, nitrogen in the film, inducing the microstructure variation appears to play an important role in thermal stability and resistance against Cu diffusion. Amorphousization effects of nitrogen variation are believed to be capable of lengthening grain structures to alleviate Cu diffusion effectively. In addition, a thin multilayered amorphous-like HfN film not only has lengthening grain structures to alleviate Cu diffusion, but block and discontinue fast diffusion paths as well. Hence, a thin multilayered amorphous-like HfN/HfN barrier shows the excellent barrier property to suppress the formation of high resistance η′-(Cu,Si) compound phase to 700 °C.     

RF performance and modeling of Si/SiGe resonant interband tunneling diodes

The RF performance of two different Si-based resonant interband tunneling diodes (RITD) grown by low-temperature molecular beam epitaxy (LT-MBE) were studied. An RITD with an active region of B /spl delta/-doping plane/2 nm i-Si/sub 0.5/Ge/sub 0.5//1 nm i-Si/P /spl delta/-doping plane yielded a peak-to-valley current ratio (PVCR) of 1.14, resistive cutoff frequency (f/sub r0/) of 5.6 GHz, and a speed index of 23.3 mV/ps after rapid thermal annealing at 650/spl deg/C for 1 min. To the authors' knowledge, these are the highest reported values for any epitaxially grown Si-based tunnel diode. Another RITD design with an active region of 1 nm p+ Si/sub 0.6/Ge/sub 0.4//B /spl delta/-doping plane/4-nm iSi/sub 0.6/Ge/sub 0.4//2 nm i-Si/P /spl delta/-doping plane and annealed at 825/spl deg/C for 1 min had a PVCR of 2.9, an f/sub r0/ of 0.4 GHz, and a speed index of 0.2 mV/ps. A small signal model was established to fit the measured S/sub 11/ data for both device designs. Approaches to increase f/sub r0/ are suggested based on the comparison between these two diodes. The two devices exhibit substantially different junction capacitance/bias relationships, which may suggest the confined states in the /spl delta/-doped quantum well are preserved after annealing at lower temperatures but are reduced at higher temperature annealing. A comprehensive dc/RF semi-physical model was developed and implemented in Agilent advanced design system (ADS) software. Instabilities in the negative differential resistance (NDR) region during dc measurements were then simulated.     

Backside copper metallization of GaAs MESFETs using TaN as thediffusion barrier

Backside copper metallization of GaAs MESFETs using TaN as the diffusion barrier was studied. A thin TaN layer of 40 nm was sputtered on the GaAs substrate before copper film metallization, as judged from the data of X-ray diffraction (XRD), Auger electron spectroscopy (AES), and cross-sectional transmission electron microscopy (TEM), the Cu/TaN films with GaAs were very stable without interfacial interaction up to 550°C annealing; the copper metallized MESFETs were thermally stressed at 300°C. The devices showed very little change in the device characteristics (<3%) after thermal stress, and the changes of the electrical parameters and RF characteristics of the devices after thermal stress were of the same order as those devices without Cu metallization, these results show that TaN is a good diffusion barrier for Cu in GaAs devices and the Cu/TaN films can be used for the backside copper metallization of GaAs MESFETs     

Electrical characterization and material evaluation of zirconium oxynitride gate dielectric in TaN-gated NMOSFETs with high-temperature forming gas annealing

The electrical, material, and reliability characteristics of zirconium oxynitride (Zr-oxynitride) gate dielectrics were evaluated. The nitrogen (/spl sim/1.7%) in Zr-oxynitride was primarily located at the Zr-oxynitride/Si interface and helped to preserve the composition of the nitrogen-doped Zr-silicate interfacial layer (IL) during annealing as compared to the ZrO/sub 2/ IL - resulting in improved thermal stability of the Zr-oxynitride. In addition, the Zr-oxynitride demonstrated a higher crystallization temperature (/spl sim/600/spl deg/C) as compared to ZrO/sub 2/ (/spl sim/400/spl deg/C). Reliability characterization was performed after TaN-gated nMOSFET fabrication of Zr-oxynitride and ZrO/sub 2/ devices with equivalent oxide thickness (EOTs) of 10.3 /spl Aring/ and 13.8 /spl Aring/, respectively. Time-zero dielectric breakdown and time-dependent dielectric breakdown (TDDB) characteristics revealed higher dielectric strength and effective breakdown field for the Zr-oxynitride. High-temperature forming gas (HTFG) annealing on TaN/Zr-oxynitride nMOSFETs with an EOT of 11.6 /spl Aring/ demonstrated reduced D/sub it/, which resulted in reduced swing (69 mV/decade), reduced off-state leakage current, higher transconductance, and higher mobility. The peak mobility was increased by almost fourfold from 97 cm/sup 2//V/spl middot/s to 383 cm/sup 2//V/spl middot/s after 600/spl deg/C HTFG annealing.     

Thermally robust TaTb/sub x/N metal gate electrode for n-MOSFETs applications

In this letter, we study Terbium (Tb)-incorporated TaN (TaTb/sub x/N) as a thermally robust N-type metal gate electrode for the first time. The work function of the Ta/sub 0.94/Tb/sub 0.06/N/sub y/ metal gate is determined to be /spl sim/4.23 eV after rapid thermal anneal at 1000/spl deg/C for 30 s, and can be further tuned by varying the Tb concentration. Moreover, the TaTb/sub x/N-SiO/sub 2/ gate stack exhibits excellent thermal stability up to 1000/spl deg/C with no degradation to the equivalent oxide thickness, gate leakage, and time-dependent dielectric breakdown (TDDB) characteristics. These results suggest that Tb-incorporated TaN (TaTb/sub x/N) could be a promising metal gate candidate for n-MOSFET in a dual-metal gate Si CMOS process.     

Cu contact on NiSi substrate with a Ta/TaN barrier stack

The thermal and electrical stabilities of Cu contact on NiSi substrate with and without a Ta/TaN barrier stack in between were investigated. Four-point probe (FPP), X-ray diffraction (XRD), scanning electron microscopy (SEM), depth-profiling X-ray photoelectron spectroscopy (XPS), and Schottky barrier height (SBH) measurement were carried out to characterize the diffusion barrier properties. The SBH measurement provides a very sensitive method to characterize the diffusion barrier properties for the copper contact on NiSi/Si. The results show that the Ta/TaN stack can be both thermally and electrically stable after annealing at 450 °C for 30 min and it will have a potential application as a diffusion barrier for Cu contact on NiSi.     

Three-Layer laminated metal gate electrodes with tunable work functions for CMOS applications

This letter presents a novel technique for tuning the work function of a metal gate electrode. Laminated metal gate electrodes consisting of three ultrathin (/spl sim/1-nm) layers, with metal nitrides (HfN, TiN, or TaN) as the bottom and top layers and element metals (Hf, Ti, or Ta) as the middle layer, were sequentially deposited on SiO/sub 2/, followed by rapid thermal annealing annealing. Annealing of the laminated metal gate stacks at high temperatures (800/spl deg/C-1000/spl deg/C) drastically increased their work functions (as much as 1 eV for HfN-Ti-TaN at 1000/spl deg/C). On the contrary, the bulk metal gate electrodes (HfN, TiN and TaN) exhibited consistent midgap work functions with only slight variation under identical annealing conditions. The work function change of the laminated metal electrodes is attributed to the crystallization and the grain boundary effect of the laminated structures after annealing. This change is stable and not affected by subsequent high-temperature process. The three-layer laminated metal gate technique provides PMOS-compatible work functions and excellent thermal stability even after annealing at 1000/spl deg/C.     

Manufacturing enhancements for CoSi/sub 2/ self-aligned silicide at the 0.12-/spl mu/m CMOS technology node

As integrated circuit manufacturing moves to the 0.12-/spl mu/m and finer-line technologies, a more comprehensive understanding of the manufacturability of the cobalt silicide (CoSi/sub 2/) module is needed. In this paper, a detailed study of the manufacturability of cobalt self-aligned silicide (Salicide) for the 0.12-/spl mu/m and finer technology nodes is discussed. Experimental design for the CoSi/sub 2/ processing steps included cobalt (Co), titanium (Ti), and titanium nitride (TiN) depositions; the first and second rapid thermal anneals (RTA1 and RTA2) and the selective metal etch. Grain structure (by X-ray diffraction), surface roughness (by atomic force microscopy), sheet resistance, thickness uniformity and leakage current measurements were taken to characterize the SAlicide process module. The results show that by using a TiN rather than Ti capping layer: a) the CoSi/sub 2/ sheet resistance nonuniformity has been improved; b) the CoSi/sub 2/ thickness is independent of the capping layer thickness; and c) CoSi/sub 2/ to silicon interface roughness is reduced, thus reducing junction leakage currents. Anneal studies indicate the RTA1 temperature dominates the CoSi/sub 2/ grain structure and grain size with higher annealing temperatures resulting in rougher CoSi/sub 2/ surfaces and higher junction leakage currents.     

Robust high-quality HfN-HfO/sub 2/ gate stack for advanced MOS device applications

In this letter, a thermally stable and high-quality HfN-HfO/sub 2/ gate stack for advanced MOS applications is reported for the first time. Negligible changes in both equivalent oxide thickness (EOT) and work function of HfN-HfO/sub 2/ gate stack are demonstrated even after 1000/spl deg/C postmetal annealing (PMA), which is attributed to the superior oxygen diffusion barrier property of HfN as well as the thermal stability of the HfN-HfO/sub 2/ interface. Therefore, even without surface nitridation prior to HfO/sub 2/ deposition, the EOT of HfN-HfO/sub 2/ gate stack can be successfully scaled down to less than 10 /spl Aring/ after 1000/spl deg/C PMA with excellent leakage and long-term reliability.     

Leakage suppression of gated diodes fabricated under low-temperature annealing with substitutional carbon Si/sub 1-y/C/sub y/ incorporation

We have demonstrated the fabrication of n/sup +/-p gated diodes using low-temperature annealing of 700/spl deg/C for 30 s with a significantly reduced junction leakage current. This is achieved with the incorporation of an epitaxially grown Si/sub 1-y/C/sub y/(y=0.0007) layer in the substrate located at the end-of-range (EOR) of arsenic implantations. The carbon devices show effectively suppressed EOR defects in the cross-sectional transmission electron microscopy images and leakage characteristics similar to the controlled silicon device fabricated under high-temperature annealing of 950/spl deg/C for 30 s. Arrhenius measurement of the leakage profiles has indicated identical leakage mechanism for both the pure silicon and carbon devices, thus signifying the substantial elimination of the secondary EOR defects resulted from the implantations despite the low-temperature annealing of the latter.     

Failure mechanisms of PVD Ta and ALD TaN barrier layers for Cu contact applications

PVD Ta-based and ALD TaN layers were studied as Cu diffusion barriers on poly-silicon, NiSi and CoSi₂ for Cu contact applications. The effectiveness of nanometer-thick layers, deposited in manufacturing compatible chambers on 200 and 300 mm wafers, is evaluated by detection of Cu-silicidation temperature using high temperature in situ XRD. It is found that Si diffuses into the α-Ta lattice for PVD barriers between 300 and 500 °C, and induces Ta silicidation at 600 °C. The agglomeration of TaSi₂ seems to be responsible for the damage of barrier continuity and cause subsequent Cu-silicidation. The growth of ALD TaN on different surfaces of NiSi was studied by XRF, RBS and XRR. The growth curves show excellent linearity as a function of thickness. TOF-SIMS shows closed layers after 60 ALD cycles. In situ XRD reveals that the failure temperature of 4 nm thick ALD layers is higher than 500 °C. It is found that the failure of 3 and 4 nm ALD TaN layers in Cu/barrier/NiSi stacks is a diffusion controlled process, with an activation energy Q of ∼2.2 eV and a pre-exponential factor D₀ of ∼3.8 × 10⁻³ cm²/s.     

Electrical properties of amorphous high-/spl kappa/ HfTaTiO gate dielectric with dielectric constants of 40-60

High-quality Hf-based gate dielectrics with dielectric constants of 40-60 have been demonstrated. Laminated stacks of Hf, Ta, and Ti with a thickness of /spl sim/10 /spl Aring/ each was deposited on Si followed by rapid thermal anneal. X-ray diffraction analysis showed that the crystallization temperature of the laminated dielectric stack is increased up to 900/spl deg/C. The excellent electrical properties of HfTaTiO dielectrics with TaN electrode have been demonstrated, including low interface state density (D/sub it/), leakage current, and trap density. The effect of binary and ternary laminated metals on the enhancement of dielectric constant and electrical properties has been studied.     

Effect of Mg doping on the superconducting properties of Cu/sub 1-x/Tl/sub x/Ba/sub 2/Ca/sub 3-y/Mg/sub y/Cu/sub 4/O/sub 12-/spl delta//

Superconducting properties of Cu/sub 1-x/Tl/sub x/Ba/sub 2/Ca/sub 3-y/Mg/sub y/Cu/sub 4/O/sub 12-/spl delta// (Cu/sub 1-x/Tl/sub x/Mg/sub y/-1234) material have been studied in the composition range y=0,1.5,2.25. The zero resistivity critical temperature [T/sub c/(R=0)] was found to increase with the increased concentration of Mg in the unit cell; for y=1.5 [T/sub c/(R=0)]=131 K was achieved which is hitherto highest in Cu/sub 1-x/Tl/sub x/-based superconductors. The X-ray diffraction analyses have shown the formation of a predominant single phase of Cu/sub 0.5/Tl/sub 0.5/Ba/sub 2/Ca/sub 3-y/Mg/sub y/Cu/sub 4/O/sub 12-/spl delta// superconductor with an inclusion of impurity phase. It is observed from the convex shape of the resistivity versus temperature measurements that our as-prepared material was in the region of carrier over-doping, and the number of carriers was optimized by postannealing experiments in air at 400/spl deg/C, 500/spl deg/C, and 600/spl deg/C. The T/sub c/(R=0) was found to increase with postannealing and the best postannealing temperature was found to be 600/spl deg/C. The mechanism of increased T/sub c/(R=0) is understood by carrying out infrared absorption measurements. It was observed through softening of Cu(2)-O/sub A/-Tl apical oxygen mode that improved interplane coupling was a possible source of enhancement of T/sub c/(R=0) to 131 K.