一种适于Rail-to-Rail输入的2.5 V CMOS模拟采样电路

文本分析了影响低压CMOS采样电路性能的主要因素，设计了一种适合在2．5V电源下工作的CMOS自举开关采样电路。其输入信号的动态范围为0—2．5V，并给出了0．6μm标准CMOS工艺条件下的Hspice模拟结果。     

A novel robust FPGA routing switch box design for ultra low power applications

Fabrication cost of application-specific integrated circuits (ASICs) is exponentially rising in deep submicron region due to rapidly rising non-recurring engineering cost. Field programmable gate arrays (FPGAs) provide an attractive alternative to ASICs but consume an order of magnitude higher power. There is a need to explore ways of reducing FPGA power consumption so that they can also be employed in ultra low power (ULP) applications instead of ASICs. Subthreshold region of operation is an ideal choice for ULP low-throughput FPGAs. The routing of an FPGA consumes most of the chip area and primarily determines the circuit delay and power consumption. There is a need to design moderate-speed ULP routing switches for subthreshold FPGA. This article proposes a novel subthreshold FPGA routing switch box (SB) that utilises the leakage voltage through transistor as biasing voltage which shows 69%, 61.2% and 30% improvement in delay, power delay product and delay variation, respectively, over conventional routing SB.     

一种高隔离度低损耗CMOS射频收发开关设计方法

本文采用了LC并联谐振的办法设计了高性能的CMOS收发开关,由于消除了CMOS晶体管的寄生电容的影响,降低了开关电路的插入损耗、提高隔离性能。同时利用直流偏置和交流浮动技术来提高开关的功率容纳能力。采用TSMC0.35 m RF-CMOS工艺设计的收发开关,模拟结果表明谐振频率工作点的插入损耗为1.03dB,收发端隔离39.277dB,输入1dB压缩点(P1dB)功率26.28dBm。     

12位100 MSPS CMOS双采样/保持电路

提出了一种基于时间交织原理的双采样/保持电路;分析了其相比于传统单采样技术实现高速度、高精度,同时降低功耗的优点。设计的栅压自举开关有效提高了采样的线性度。另外,为满足双采样技术的特殊应用,设计了带双边型开关电容共模反馈的全差分运放。采用SMIC0.18μmCMOS工艺仿真设计的双采样/保持电路可实现12位采样精度、100 MSPS采样速率、92.34 dB线性度和29 mW功耗的高性能。     

一种用于高速高精度A/D转换器的自举采样电路

介绍了一种新型的CMOS自举采样电路。该电路适用于12位100 MHz采样频率的A/D转换器。采用P型栅压自举开关补偿技术,可以有效地克服采样管导通电阻变化引入的非线性失真,提高采样精度。仿真结果表明,采样时钟频率为100 MHz时,输入10 MHz信号,可得信噪失真比(SNDR)为102 dB,无杂散动态范围(SFDR)为103 dB。信号频率达到采样频率时,仍有超过85 dB的SNDR和87 dB的SFDR,满足高速高精度流水线A/D转换器对采样开关线性度和输入带宽的要求。电路采用SMIC 0.18μm CMOS数模混合工艺库实现,电源电压为1.8 V。     

一种CMOS高速采样/保持放大器

文章分析了采样／保持电路的基本原理，设计了一种CMOS高速采样／保持放大器，采样频率可达到50MHz，并用TSMC的0．35μm标准CMOS工艺库模拟了整体电路和分块电路的性能。     

新型CMOS采样/保持电路的设计研究

讨论了目前各种先进的采样／保持电路结构，基于底极板(BottomPlate)采样技术和引导开关技术，设计了一种新型的全差分开关电容双采样保持放大器，有效地消除了电荷注入和时钟馈通效应，并保证了较高的单位增益频率、采样速率和信号建立时间。电路设计基于TSMC 0．35μm CMOS工艺Bsim3模型，并采用Hspice工具对设计进行了仿真验证。     

基于PIN管的多路大功率宽带高线性射频开关的研制

设计制作了一款工作于100~400MHz的大功率宽带高线性单刀多掷PIN管收发开关。该开关采用1分6再分6的串联型结构,通过对PIN管的选取和微带线布局来实现对开关插损、隔离度和驻波比的要求。由于采用串联结构而非串并结构,该开关驱动部分大为简化。测试结果表明,该开关插损小于0.3 dB,隔离度大于50 dB,驻波比小于1.2,功率容量为100 W,二次谐波抑制大于70 dBc。     

A compact tunable CMOS transconductor with high linearity

A novel CMOS linear transconductor is presented. The use of simple and accurate voltage buffers to drive two MOS transistors operating in the triode region leads to a highly linear voltage-to-current conversion. Transconductance gain can be continuously and precisely adjusted using dc level shifters. Measurement results of a balanced transconductor fabricated in a 0.5-/spl mu/m CMOS technology show a total harmonic distortion of -54 dB at 100 kHz for an 80-/spl mu/A peak-to-peak output, using a supply voltage of 2 V. It requires 0.07-mm/sup 2/ of silicon (Si) area and features 0.96 mW of static power consumption.     

DB-driver: a low power CMOS bootstrapped differential cross-coupled driver

This paper for the first time reports the design of a high speed and low power differential cross-coupled bootstrapped CMOS driver circuit. The circuit design style, based on the proposed differential cross-coupled bootstrapped driver achieves high performance low core area, and fast full-swing operation, even in spite of the fact that the magnitude of the threshold voltage of the CMOS devices cannot be scaled down with the scaling of the power supply voltage. The proposed driver is implemented on 0.13?µm CMOS technology with a power supply of 1.2?V. It is 34% faster and provides 8% less core area when compared to a base-line circuit using an indirect bootstrap technique. In addition, the proposed driver reduces the power consumption by 35%. The superior performance of the proposed circuit over the other differential cross-coupled bootstrapped CMOS driver circuit, for the applications that require high performance, has been verified with post-layout simulation.     

A CMOS threshold voltage reference source for very-low-voltage applications

This paper describes a CMOS voltage reference that makes use of weak inversion CMOS transistors and linear resistors, without the need for bipolar transistors. Its operation is analogous to the bandgap reference voltage, but the reference voltage is based on the threshold voltage of an nMOS transistor. The circuit implemented using 0.35 μm n-well CMOS TSMC process generates a reference of 741 mV under just 390 nW for a power supply of only 950 mV. The circuit presented a variation of 39 ppm/°C (after individual resistor trimming) for the −20 to +80 °C temperature range, and produced a line regulation of 25 mV/V for a power supply of up to 3 V.     

A wide band differentially switch-tuned CMOS monolithic quadrature VCO with a low Kvco and high linearity

A wide band, differentially switch-tuned CMOS monolithic LC-VCO is presented in this paper, as well as a frequency divider for high linearity, low Kvco quadrature signal generation. A linearity control logic is proposed. The Kvco linearity is improved to be lower than 17.68 MHz/V. By using the proposed CML DFF, the operating frequency of the frequency divider is increased by 20% with a power consumption of 3.6 mW. The proposed design has been fabricated and verified in a 0.18 μm CMOS process. The QVCO is tuned in a combined way of continuous technology and 4 bit binary switch capacitor array (SCA) discrete tuning technology. The measurement indicates that the QVCO has a 19.7% tuning range from 1.816 to 2.213 GHz. The measured phase noise is −112.25 dBc/Hz at 1 MHz offset from the 1.819 GHz carrier and draws a current of 4.0 mA around at a 1.8 V supply.     

论低压开关中永磁控制技术的应用

为了克服传统低压开关电动控制系统中所存在的诸如接触器主触头被烧、短路情况下断路器无法正常将电路分断、电机保护功能难以充分发挥等问题,可以通过永磁控制技术的应用加以实现.本文重点就低压开关的电磁控制技术进行探讨,以供参考.     

采用多次离子注入调整亚微米CMOS电路的阈电压

采用多次离子注入来调整亚微米CMOS的NMOS和PMOS管的阈值电压是研究亚微米CMOS电路的关键.浅离子注入调节表面掺杂浓度以达到调整阈值电压的目的.深离子注入调整源漏穿通电压.与LDD、硅化物工艺相合,已研制出0.5μm的CMOS 27级环振电路,门延迟为130ps.     

Techniques for evaluating harmonic distortion in class-AB output stages: A tutorial

In this paper, we discuss and provide a detailed tutorial of four different methods for analytically evaluating the harmonic distortion in class-AB stages. All the methods are suitable for pencil-and-paper analysis and are based on modeling the stage with a specific non-linear function. We analyze them in details and extend some of them for predicting harmonic distortion behavior in a wide range of input signal amplitude. Comparisons made by means of simulations, reveal that some methods are more precise than others but require more computational effort. On the contrary, some of them are simple to use but are less precise. Moreover, some are more appropriate for predicting HD₂ and others for HD₃, only. Results of the present paper may be used by designers to choose the more efficient method for analyzing distortion in class-AB stages. Gianluca Giustolisi was born in Catania, Italy, in 1971. He received the Laurea degree (cum laude) in electronic engineering and the Ph.D. degree in electrical engineering from University of Catania, Catania, Italy, in 1995 and 1999, respectively. Currently he is associate professor at Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi (DIEES), University of Catania. His research interests include analysis, modelling and design of analog integrated circuits and systems with particular emphasis on non-linear and low-voltage applications. Gianluca Giustolisi is IEEE Member. Gaetano Palumbo was born in Catania, Italy, in 1964. He received the laurea degree in Electrical Engineering in 1988 and a Ph.D. degree from the University of Catania in 1993. Since 1993 he conducts courses on Electronic Devices, Electronics for Digital Systems and basic Electronics. In 1994 he joined the DEES (Dipartimento Elettrico Elettronico e Sistemistico), now DIEES (Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi), at the University of Catania as a researcher, subsequently becoming associate professor in 1998. Since 2000 he is a full professor in the same department. His primary research interest has been analog circuits with particular emphasis on feedback circuits, compensation techniques, current-mode approach, low-voltage circuits. Then, his research has also embraced digital circuits with emphasis on bipolar and MOS current-mode digital circuits, adiabatic circuits, and high-performance building blocks focused on achieving optimum speed within the constraint of low power operation. In all these fields he is developing some the research activities in collaboration with STMicroelectronics of Catania. He was the co-author of three books “CMOS Current Amplifiers” and ”Feedback Amplifiers: theory and design” and “Model and Design of Bipolar and MOS Current-Mode Logic (CML, ECL and SCL Digital Circuits)” all by Kluwer Academic Publishers, in 1999, 2001 and 2004, respectively. He is a contributor to the Wiley Encyclopedia of Electrical and Electronics Engineering. He is the author of more than 250 scientific papers on referred international journals (over 100) and in conferences. Moreover he is co-author of several patents. In 1999/2001 and 2004/2005 he served as Associated Editor of the IEEE Transactions on Circuits and Systems part I for the topic “Analog Circuits and Filters” and “Digital Circuits and Systems”, respectively. In 2005 he was one of the 12 panelists in the scientific-disciplinare area 09 - industrial and information engineering of the CIVR (Committee for Evaluation of Italian Research), which has the aim to evaluate the Italian research in the above area for the period 2001–2003. In 2003 he received the Darlington award. Since 2006 he is serving as Associated Editor of the IEEE Transactions on Circuits and Systems part I. Prof. Palumbo is an IEEE Senior Member.     

一种基于电荷泵改进型CMOS模拟开关电路

提出了一种基于电荷泵的模拟开关结构.该结构使用电荷泵抬升MOS管的栅电压,从而大大改善开关的导通能力、线性度和动态传输范围.通过仿真验证了开关电路性能,结果表明设计的开关电路在电压0-5V范围内,导通电阻很小且信号损耗很小无失真.因而特别适用于低压系统.     

射频MEMS膜开关的力学解析模型

MEMS开关以其固有的低功耗、低插损和低交叉调制损耗等特性 ,在微波领域表现出巨大的应用潜力。但是目前大部分的研究工作都集中在设计新型开关结构和开关制作工艺上 ,对开关力学模型的研究较少。本文根据材料力学 ,通过合理的假设和简化 ,推导出MEMS开关的静电力解析模型 ,并详细探讨开关阈值电压和开关几何尺寸及材料特性之间的关系。这对MEMS开关的设计有一定的指导意义     

电流叠加型CMOS基准电压源

介绍了一种CMOS基准电压源,该电路由NMOS管阈值电压的温度系数及NMOS管迁移率温度系数形成温度补偿,产生低温度系数的基准电压。与传统的带隙基准比较而言,不需要三极管;另外,通过结构的改进,变成正负温度系数电流叠加型的基准电压源,可以按需要任意调节输出基准电压的值,而且可以同时提供多个基准电压。电流叠加型基准电压源电路已经在3μmCMOS工艺线上实现,基准电压源输出中心值在2.2 V左右,温度系数为80 ppm/℃。     

CM7510系列CMOS高压模拟开关电路的研究

本文介绍CM7510系列CMOS高压模拟开关电路的设计,版图设计,工艺及电路性能。从理论和实验中分析了常规工艺中影响击穿电压的几个关键工艺参数。