一种新型高线性度CMOS自举采样开关

分析了采样开关中非线性的来源,以及传统自举采样开关的弊端,提出了一种新型高线性度CMOS自举采样开关电路结构.相比传统自举采样开关,新型电路可以将阈值电压随输入信号变化引入的非线性减至最小.采用0.18μm标准CMOS工艺,在Cadence Spectre环境下仿真.结果显示,当输入频率为15 MHz、峰峰值为0.84 V的正弦波,且采样时钟频率为30 MHz时,采样开关的无杂散动态范围达到93 dB,较之传统自举采样开关提高了近20 dB.     

A novel robust FPGA routing switch box design for ultra low power applications

Fabrication cost of application-specific integrated circuits (ASICs) is exponentially rising in deep submicron region due to rapidly rising non-recurring engineering cost. Field programmable gate arrays (FPGAs) provide an attractive alternative to ASICs but consume an order of magnitude higher power. There is a need to explore ways of reducing FPGA power consumption so that they can also be employed in ultra low power (ULP) applications instead of ASICs. Subthreshold region of operation is an ideal choice for ULP low-throughput FPGAs. The routing of an FPGA consumes most of the chip area and primarily determines the circuit delay and power consumption. There is a need to design moderate-speed ULP routing switches for subthreshold FPGA. This article proposes a novel subthreshold FPGA routing switch box (SB) that utilises the leakage voltage through transistor as biasing voltage which shows 69%, 61.2% and 30% improvement in delay, power delay product and delay variation, respectively, over conventional routing SB.     

一种适于Rail-to-Rail输入的2.5 V CMOS模拟采样电路

文本分析了影响低压CMOS采样电路性能的主要因素，设计了一种适合在2．5V电源下工作的CMOS自举开关采样电路。其输入信号的动态范围为0—2．5V，并给出了0．6μm标准CMOS工艺条件下的Hspice模拟结果。     

一种高隔离度低损耗CMOS射频收发开关设计方法

本文采用了LC并联谐振的办法设计了高性能的CMOS收发开关,由于消除了CMOS晶体管的寄生电容的影响,降低了开关电路的插入损耗、提高隔离性能。同时利用直流偏置和交流浮动技术来提高开关的功率容纳能力。采用TSMC0.35 m RF-CMOS工艺设计的收发开关,模拟结果表明谐振频率工作点的插入损耗为1.03dB,收发端隔离39.277dB,输入1dB压缩点(P1dB)功率26.28dBm。     

12位100 MSPS CMOS双采样/保持电路

提出了一种基于时间交织原理的双采样/保持电路;分析了其相比于传统单采样技术实现高速度、高精度,同时降低功耗的优点。设计的栅压自举开关有效提高了采样的线性度。另外,为满足双采样技术的特殊应用,设计了带双边型开关电容共模反馈的全差分运放。采用SMIC0.18μmCMOS工艺仿真设计的双采样/保持电路可实现12位采样精度、100 MSPS采样速率、92.34 dB线性度和29 mW功耗的高性能。     

一种用于高速高精度A/D转换器的自举采样电路

介绍了一种新型的CMOS自举采样电路。该电路适用于12位100 MHz采样频率的A/D转换器。采用P型栅压自举开关补偿技术,可以有效地克服采样管导通电阻变化引入的非线性失真,提高采样精度。仿真结果表明,采样时钟频率为100 MHz时,输入10 MHz信号,可得信噪失真比(SNDR)为102 dB,无杂散动态范围(SFDR)为103 dB。信号频率达到采样频率时,仍有超过85 dB的SNDR和87 dB的SFDR,满足高速高精度流水线A/D转换器对采样开关线性度和输入带宽的要求。电路采用SMIC 0.18μm CMOS数模混合工艺库实现,电源电压为1.8 V。     

一种采用新型时钟馈通补偿技术的栅电压自举开关

Nonlinearity caused by the clock feed-through of a bootstrapped switch and its compensation techniques are analyzed. All kinds of clock feed-through compensation configurations and their drawbacks are also investigated. It is pointed out that the delay path match of the clock boosting circuit is the critical factor that affects the effectiveness of clock feed-through compensation. Based on that, a new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with the UMC mixed-mode/RF 0.18 μm 1P6M P-sub twin-well CMOS process by orientating and elaborately designing the switch MOSFETs that influence the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feedthrough compensation configuration can not only enhance the sampling accuracy under variations of process, power supply voltage, temperature and capacitors but also decrease the even harmonic, high-order odd harmonic and THD on the whole effectively.     

一种CMOS高速采样/保持放大器

文章分析了采样／保持电路的基本原理，设计了一种CMOS高速采样／保持放大器，采样频率可达到50MHz，并用TSMC的0．35μm标准CMOS工艺库模拟了整体电路和分块电路的性能。     

A bootstrapped switch employing a new clock feed-through compensation technique

Nonlinearity caused by the clock feed-through of a bootstrapped switch and its compensation techniques are analyzed. All kinds of clock feed-through compensation configurations and their drawbacks are also investigated.It is pointed out that the delay path match of the clock boosting circuit is the critical factor that affects the effective-ness of clock feed-through compensation. Based on that, a new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with the UMC mixed-mode/RF 0.18μm 1P6M P-sub twin-well CMOS process by orientating and elaborately designing the switch MOSFETs that influence the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feed-through compensation configuration can not only enhance the sampling accuracy under variations of process, power supply voltage, temperature and capacitors but also decrease the even harmonic, high-order odd harmonic and THD on the whole effectively.     

一个单通道10位160兆每秒的逐次逼近式模数转换器

This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register （SAR） analog-to-digital converter （ADC） in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 ×200 μm^2 is occupied.     

新型CMOS采样/保持电路的设计研究

讨论了目前各种先进的采样／保持电路结构，基于底极板(BottomPlate)采样技术和引导开关技术，设计了一种新型的全差分开关电容双采样保持放大器，有效地消除了电荷注入和时钟馈通效应，并保证了较高的单位增益频率、采样速率和信号建立时间。电路设计基于TSMC 0．35μm CMOS工艺Bsim3模型，并采用Hspice工具对设计进行了仿真验证。     

基于PIN管的多路大功率宽带高线性射频开关的研制

设计制作了一款工作于100~400MHz的大功率宽带高线性单刀多掷PIN管收发开关。该开关采用1分6再分6的串联型结构,通过对PIN管的选取和微带线布局来实现对开关插损、隔离度和驻波比的要求。由于采用串联结构而非串并结构,该开关驱动部分大为简化。测试结果表明,该开关插损小于0.3 dB,隔离度大于50 dB,驻波比小于1.2,功率容量为100 W,二次谐波抑制大于70 dBc。     

A compact tunable CMOS transconductor with high linearity

A novel CMOS linear transconductor is presented. The use of simple and accurate voltage buffers to drive two MOS transistors operating in the triode region leads to a highly linear voltage-to-current conversion. Transconductance gain can be continuously and precisely adjusted using dc level shifters. Measurement results of a balanced transconductor fabricated in a 0.5-/spl mu/m CMOS technology show a total harmonic distortion of -54 dB at 100 kHz for an 80-/spl mu/A peak-to-peak output, using a supply voltage of 2 V. It requires 0.07-mm/sup 2/ of silicon (Si) area and features 0.96 mW of static power consumption.     

A low complexity pre‐distortion scheme for power amplifier linearization in wideband applications

In this paper, a nonlinear autoregressive with exogenous inputs (NARX) digital pre‐distortion scheme to linearize power amplifiers is proposed. The proposed NARX digital pre‐distortion gives better accuracy and spectral leakage suppression compared with other commonly used Volterra‐based techniques. The stability criterion of the NARX digital pre‐distortion is derived from the frequency domain analysis. Simulation is carried out with a 20 MHz single carrier long‐term evolution signal and two‐carrier long‐term evolution signal and instantaneous to average ratio of 6.2 dB at 0.01% complementary cumulative distribution function (CCDF). The results of simulation analysis show a slight improvement in adjacent channel leakage ratio performance with 30% reduction in the number of floating point operations compared with conventional pre‐distortion techniques. Copyright © 2016 John Wiley & Sons, Ltd.     

A novel loss compensation technique analysis and design for 60 GHz CMOS SPDT switch

A novel loss compensation technique for a series-shunt single-pole double-throw (SPDT) switch is presented operating in the 60 GHz. The feed-forward compensation network which is composed of an NMOS, a couple capacitance and a shunt inductance can reduce the impact of the feed forward capacitance to reduce the insertion loss and improve the isolation of the SPDT switch. The measured insertion loss and isolation characteristics of the switch somewhat deviating from the 60 GHz are analyzed revealing that the inaccuracy of the MOS model can greatly degrade the performance of the switch. The switch is implemented in TSMC 90-nm CMOS process and exhibits an isolation of above 27 dB at transmitter mode, and the insertion loss of 1.8-3 dB at 30-65 GHz by layout simulation. The measured insertion loss is 2.45 dB at 52 GHz and keeps<4 dB at 30-64 GHz. The measured isolation is better than 25 dB at 30-64 GHz and the measured return loss is better than 10 dB at 30-65 GHz. A measured input 1 dB gain compression point of the switch is 13 dBm at 52 GHz and 15 dBm at 60 GHz. The simulated switching speed with rise time and fall time are 720 and 520 ps, respectively. The active chip size of the proposed switch is 0.5×0.95 mm².     

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.     

一款采用SOI CMOS工艺实现的X波段高线性6位数控移相器

本文基于SOI CMOS工艺实现了一款工作于X波段的高线性6位数控移相器,解决了实现高集成度、低成本、小尺寸T/R组件的关键问题。本文中移相器采用高低通网络结构实现,同时集成了ESD电路和驱动电路。在7.5GHz-10.5GHz范围内,测得的EMS相位误差小于7.5度,输入输出VSWR小于2,插损在8-14dB之间,同频率处插损波动最大为4dB。输入1dB压缩点为20dBm。该芯片采用2.5V电压供电,无直流功耗。     

A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer

This paper presents the design of a 10-bit, 50 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an on-chip reference voltage buffer implemented in 65 nm CMOS process. The speed limitation on SAR ADCs with off-chip reference voltage and the necessity of a fast-settling reference voltage buffer are elaborated. Design details of a high-speed reference voltage buffer which ensures precise settling of the DAC output voltage in the presence of bondwire inductances are provided. The ADC uses bootstrapped switches for input sampling, a double-tail high-speed dynamic comparator and split binary-weighted capacitive array charge redistribution DACs. The split binary-weighted array DAC topology helps us to achieve low area and less capacitive load and thus enhances power efficiency. Top-plate sampling is utilized in the DAC to reduce the number of switches. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm².     

DB-driver: a low power CMOS bootstrapped differential cross-coupled driver

This paper for the first time reports the design of a high speed and low power differential cross-coupled bootstrapped CMOS driver circuit. The circuit design style, based on the proposed differential cross-coupled bootstrapped driver achieves high performance low core area, and fast full-swing operation, even in spite of the fact that the magnitude of the threshold voltage of the CMOS devices cannot be scaled down with the scaling of the power supply voltage. The proposed driver is implemented on 0.13?µm CMOS technology with a power supply of 1.2?V. It is 34% faster and provides 8% less core area when compared to a base-line circuit using an indirect bootstrap technique. In addition, the proposed driver reduces the power consumption by 35%. The superior performance of the proposed circuit over the other differential cross-coupled bootstrapped CMOS driver circuit, for the applications that require high performance, has been verified with post-layout simulation.