A new method for the channel-length extraction in MOSFETs with sub-2-nm gate oxide

A simple method to extract the effective channel length in deep-submicrometer devices with sub-2-nm gate oxide thickness is presented. The method uses the measured gate current from accumulation to strong inversion. It is easy to implement, fast, and accurate.     

Suppression of short channel effects by full inversion in deep sub-micron gate SOI MOSFETs

Classical modeling of fully inverted SOI MOSFET (FI MOSFET) has been performed. In FI MOSFETs, the top Si layer is thinner than the thickness of the inversion layer at the conducting state and so the depleted region in the top Si layer is completely eliminated. It was found that the gate electric field induces carriers in the channel more effectively in FI MOSFET than in the fully depleted SOI MOSFETs (FD MOSFET), so that the short channel effects can be suppressed significantly.     

Negative-differential transconductance characteristics at room temperature in 30-nm square-channel SOI nMOSFETs with a degenerately doped body

Negative-differential transconductance characteristics at room temperature with a peak-to-valley ratio of about two were observed in 30-nm square-channel silicon-on-insulator nMOSFETs with degenerately doped bodies. High channel-doping concentration creates the degeneracy in the p-type body of the self-aligned SOI MOSFET and consequently, enables band-to-band tunneling between degenerate body and source-drain. I/sub DS/-V/sub DS/ curves in the negative drain bias region also show band-to-band tunneling current as in the case of forward-biased p-n tunnel junctions.     

AC behavior of gate-induced floating body effects in ultrathin oxide PD SOI MOSFETs

In this letter we present for the first time an ac analysis of the gate-induced floating body effects (GIFBE) occurring in ultrathin gate oxide partially depleted (PD) silicon-on-insulator (SOI ) MOSFETs due to tunneling gate current. A simple equivalent circuit is proposed, which indicates that the ac behavior of GIFBE is related to the small-signal voltage variations of the floating body region. It also shows that due to the high impedance seen by the body region toward the external nodes, the GIFBE frequency dependence is characterized by a very low cut off frequency (< a few kilohertz), which is consistent with experimental data and circuit simulations performed with BSIMSOI.     

Threshold voltage model for deep-submicron fully depleted SOI MOSFETs with back gate substrate induced surface potential effects

A simple analytical threshold voltage model for short-channel fully depleted SOI MOSFETs has been derived. The model is based on the analytical solution of the two-dimensional potential distribution in the silicon film (front silicon), which is taken as the sum of the long-channel solution to the Poisson's equation and the short-channel solution to the Laplace equation, and the solution of the Poisson's equation in the silicon substrate (back silicon). The proposed model accounts for the effects of the back gate substrate induced surface potential at the buried oxide-substrate interface which contributed an additional 15–30% reduction in the threshold voltage for the devices used in this work. Conditions on the back gate supply voltage range are determined upon which the surface potential at the buried oxide-substrate interface is accumulated, depleted, or inverted. The short-channel associated drain induced barrier lowering effects are also included in the model. The model predications are in close agreement with PISCES simulation results. The equivalence between the present model and previously reported models is proven. The proposed model is suitable for use in circuit simulation tools such as Spice.     

Effects of gate structures on the RF performance in PD SOI MOSFETs

The radio-frequency (RF) performance of PD silicon-on-insulator metal oxide semiconductor field effect transistors with T-gate and H-gate structures has been investigated. Our measurement shows that H-gate devices have larger cutoff frequency and smaller minimum noise figure than T-gate devices. This improved RF performance in H-gate devices can be explained mainly by the enhancement of transconductance resulting from the gate extension induced inversion charges and the low gate resistance. We conclude that the H-gate structure is superior to the T-gate structure for the design of the low-noise amplifier (LNA).     

An analytical model for fully depleted single gate SOI MOS transistors including lattice temperature effects

An analytical model for fully depleted SOI MOSFETs is presented. Major small geometry effects such as carrier velocity saturation, mobility degradation, channel length modulation, and drain induced barrier lowering are included. Device self heating due to low thermal conductivity of a buried oxide layer is included in carrier mobility modelling. Thermal effects are also included in threshold voltage expression. Source, drain, and channel resistance effects are also included. Modelled results are then compared to available measured data and are shown to be in very good agreement.     

Exploration of heavy ion irradiation effects on gate oxide reliability in power MOSFETs

Heavy ion irradiation effects on gate oxide reliability in power MOSFETs were explored. Devices were exposed to heavy ion fluences and LETs simulating exposure in spacecraft at bias levels not expected to cause catastrophic failure. Time dependent dielectric breakdown measurements and charge separation techniques resulted in no detectable changes. The gate voltage at which oxide breakdown occurs and the gate I–V curves suggest subtle changes in device characteristics that can be detected at high gate biases. However, there is no indication that heavy ion exposure results in a significant reduction in gate oxide reliability.     

Effect of gate impurity concentration on inversion-layer mobility in MOSFETs with ultrathin gate oxide layer

In this paper, the influence of poly-Si-gate impurity concentration, N/sub poly/, on inversion-layer electron mobility is experimentally investigated in MOSFETs with ultrathin gate oxide layer. The split capacitance-voltage C-V method is modified to directly measure an effective mobility, paying attention to both 1) accurate current-voltage I-V and capacitance-voltage (C-V) measurements with high gate leakage current and 2) correct surface carrier density, N/sub s/, estimation at a finite drain bias. It is demonstrated that the mobility in ultrathin gate oxides becomes low significantly for highly doped gate, strongly suggesting the contribution of remote Coulomb scattering due to the gate impurities, which is quantitatively discriminated from that of Coulomb scattering due to substrate impurities and interface states. It is also found that the mobility lowering becomes significant rapidly at T/sub ox/ of 1.5 nm or less. The mobility-lowering component is weakly dependent on N/sub s/, irrespective of N/sub poly/, which cannot be fully explained by the existing theoretical models of remote impurity scattering.     

A comparison of floating-body potential in H-gate ultrathin gate oxide partially depleted SOI pMOS and nMOS devices based on 90-nm SOI CMOS process

Based on a 90-nm silicon-on-insulator (SOI) CMOS process, the floating-body potential of H-gate partially depleted SOI pMOS and nMOS devices with physical gate oxide of 14 /spl Aring/ is compared. For pMOS devices, because the conduction-band electron (ECB) tunneling barrier is lower (/spl cong/3.1 eV), the ECB direct-tunneling current from the n/sup +/ poly-gate beside the body terminal will contribute to a large amount of electron charges into the neutral region and dominate the floating-body potential under normal operations. Conversely, owing to the higher valence-band hole tunneling barrier (/spl cong/4.5 eV), the floating-body potential of nMOS devices is dominated by the band-to-band-tunneling mechanism at the drain-body junction, not the direct-tunneling mechanism.     

Study of the manufacturing feasibility of 1.5-nm direct-tunnelinggate oxide MOSFETs: uniformity, reliability, and dopant penetration ofthe gate oxide

Although direct tunneling gate oxide MOSFETs are expected to be useful in high-performance applications of future large-scale integrated circuits (LSIs), there are many concerns related to their manufacture. The uniformity, reliability, and dopant penetration of 1.5-nm direct-tunneling gate oxide MOSFETs were investigated for the first time. The variation of oxide thickness in an entire 150-mm wafer was evaluated by TEM and electrical measurements. Satisfactory values of standard deviations in the TEM measurements and threshold voltage measurements for MOSFETs with a gate area of 5 μm×0.75 μm, were obtained. These values improved significantly in the case of MOS capacitors with larger gate areas. The oxide breakdown field and the reliability with respect to charge injection were evaluated for the 1.5-nm gate oxides and found to be better than those of thicker gate oxides. Dopant penetration was not observed in n⁺ polysilicon gates subjected to RTA at 1050°C for 20 s and furnace annealing at 850°C for 30 min. Although much more data will be required to judge the manufacturing feasibility, these results suggest that 1.5-nm direct-tunneling oxide MOSFETs are likely to have many practical applications     

Voltage difference engineering in SOI MOSFETs: A novel side gate device with improved electrical performance

We studied the impact of voltage difference engineering in a silicon-on-insulator metal oxide semiconductor field-effect transistor (SOI-MOSFET) and compared the performance to that of a conventional SOI-MOSFET (C-SOI). Our structure, called a SIG-SOI MOSFET, includes main and side gates with an optimum voltage difference between them. The voltage difference leads to an inverted channel as an electrical drain extension under the side gate. This channel creates a stepped potential distribution along the channel that it cannot be seen in the C-SOI MOSFETs. The voltage difference controls the channel properly and two-dimensional two-carrier device simulations revealed lower threshold voltage variations, larger breakdown voltage, higher voltage gain, lower hot carrier effects, improved drain-induced barrier lowering, lower drain conductance, higher unilateral power gain, and lower leakage current compared to a C-SOI device. Thus, our proposed structure has higher performance than a typical C-SOI structure.     

Hot-carrier-induced degradation for partially depleted SOI 0.25-0.1 /spl mu/m CMOSFET with 2-nm thin gate oxide

Hot-carrier-induced degradation of partially depleted SOI CMOSFETs was investigated with respect to body-contact (BC-SOI) and floating-body (FB-SOI) for channel lengths ranging from 0.25 down to 0.1 /spl mu/m with 2 nm gate oxide. It is found that the valence-band electron tunneling is the main factor of device degradation for the SOI CMOSFET. In the FB-SOI nMOSFET, both the floating body effect (FBE) and the parasitic bipolar transistor effect (PBT) affect the hot-carrier-induced degradation of device characteristics. Without apparent FBE on pMOSFET, the worst hot-carrier stress condition of the 0.1 /spl mu/m FB-SOI pMOSFET is similar to that of the 0.1 /spl mu/m BC-SOI pMOSFET.     

Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain

The influence of tensile mechanical stress on ultrathin oxide gate currents in advanced partially depleted silicon-on-insulator MOSFETs is reported. Strain is applied uniaxially, perpendicular to the direction of current flow by bending of thinned, fully processed wafers with a gate oxide thickness of less than 1.5 nm. The gate currents of the n-channel and p-channel MOSFETS are found to change linearly and in opposite (opposing) directions as a function of uniaxial strain. The nMOS transistors generally exhibit a decrease with applied tensile strain, while the nMOS transistors show increasing gate current with strain. The observed dependences are consistent with a gate current controlled by direct tunneling and perturbed by stress-induced changes in the energy band structure.     

A study of noise in surface and buried channel SiGe MOSFETs with gate oxide grown by low temperature plasma anodization

A study is made of noise in p- and n-channel transistors incorporating SiGe surface and buried channels, over the frequency range f=1 Hz–100 kHz. The gate oxide is grown by low temperature plasma oxidation. Surface n-channel devices are found to exhibit two noise components namely 1/f and generation–recombination (GR) noise. It is shown that the 1/f noise component is due to fluctuations of charge in slow oxide traps whilst bulk centers located in a thin layer of the semiconductor close to the channel, give rise to the GR noise component. The analysis of the noise data gives values for the density D_ot of the oxide traps in the SiGe and Si nMOSFETs of the order 1.8×10¹² and 2.5×10¹⁰ cm⁻² (eV)⁻¹, respectively. The density D_GR of the bulk GR centres is equal to 3×10¹⁰ cm⁻² in both the SiGe and Si devices. The electron and hole capture cross-sections for these centres as well as their energy level and their depth below the oxide/semiconductor interface are also the same in the devices of both types. This suggests that those GR centers are of the same nature in all devices studied. p-Channel devices show different behaviour with only a 1/f noise component apparent in the data over the same frequency range. Buried SiGe channel and Si control devices exhibit quite low and similar slow state densities of the order low to mid 10¹⁰ cm⁻² (eV)⁻¹ whereas surface p-channel devices show even higher slow state densities than n-channel counterparts. The Hooge noise characterized by the Hooge coefficient _H=2×10⁻⁵ is also detected in some buried p-channel SiGe devices.     

Analysis of gate shot noise in MOSFETs with ultrathin gate oxides

The impact of gate shot noise associated with gate leakage current in MOSFETs is studied by means of analytical models and numerical device simulation. The effects of shot noise on the main two-port noise parameters (minimum noise figure, equivalent noise resistance, and optimum source admittance) and their dependence on oxide thickness and on the level of tunneling leakage current are analyzed.     

Gate length dependence of bias temperature instability behavior in short channel SOI MOSFETs

In this work, a comprehensive study of the bias temperature instability (BTI) degradation has been performed on SOI MOSFETs with various gate lengths (from 30 nm to 150 nm). For both nMOSFETs and pMOSFETs, the BTI degradation is alleviated when the gate length decreases. A new model was proposed to explain the observed gate length dependence of the BTI degradation. The decrease in the BTI degradation of MOSFETs with shorter gate length is caused by the decrease in normal electric field across the interface of Si-dielectric, which was concept-proofed by TCAD simulations.     

AC hot-carrier effects in MOSFETs with furnaceN2O-nitrided gate oxides

AC hot-carrier effects in n-MOSFETs with thin (~85 Å) N₂O-nitrided gate oxides have been studied and compared with control devices with gate oxides grown in O₂. Results show that furnace N₂O-nitrided oxide devices exhibit significantly reduced AC-stress-induced degradation. In addition, they show weaker dependences of device degradation on applied gate pulse frequency and pulse width. Results suggest that the improved AC-hot-carrier immunity of the N₂O-nitrided oxide device may be due to the significantly suppressed interface state generation and neutral electron trap generation during stressing     

Charging effect of Si nanocrystals in gate oxide near gate on MOS capacitance

MOS structure with Si nanocrystals embedded in the gate oxide close to the gate has a much larger capacitance compared to a similar MOS structure without the nanocrystals. However, charge trapping in the nanocrystals reduces the capacitance dramatically, and after most of the nanocrystals are charged up the capacitance is much smaller than that of the MOS structure without nanocrystals. An equivalent-capacitance model is proposed to explain the phenomena observed.     

Study of gate oxide leakage and charge trapping in ZMR and SIMOXSOI MOSFETs

Characterization of gate oxides grown on zone-melting-recrystallized (ZMR) and silicon-implanted-with-oxygen (SIMOX) films indicates oxide leakage and charge trapping to be several orders of magnitude greater than their bulk silicon counterparts. Electron trapping is the primary trapping mechanism for constant current injection in the gate oxides of these SOI (silicon-on-insulator) films. Similar type of traps are observed in ZMR and SIMOX oxides