A Thin-Film Filter-Based 1$, times,$2 Reconfigurable Fiber-Optic Add–Drop Module With a Quadruple Fiber-Optic Collimator

Due to a limited optical crosstalk in most thin-film filter (TF)-based fiber-optic modules, we propose and experimentally verify a low optical crosstalk TF-based 1$, times,$2 reconfigurable fiber-optic add–drop structure. Our key idea is to employ a passive noise rejection scheme by introducing a double reflection on the TF as well as a spatial separation through a combination of a quadruple and a single fiber-optic collimators. Our experimental results show a much improved$≪ - $39.1-dB optical crosstalk at the Thru port. In addition, the measured average optical losses at the Drop and the Thru ports are 1.40 and 1.23 dB, respectively, when the TF is in the optical path. When the mirror is in the optical path, all wavelength optical beams are directed to the Thru port with a measured average 2.50-dB optical loss. A low polarization-dependent loss of$≪$0.17 dB is also determined. Furthermore, our design concept can be used to form a low optical crosstalk fixed three-port add–drop filter and a high dynamic-range wavelength-sensitive variable fiber-optic attenuator.     

100-Gb/s 2/sup 7/-1 and 54-Gb/s 2/sup 11/-1 PRBS generators in SiGe bipolar technology

This paper presents two monolithic pseudorandom bit sequence (PRBS) generators. One circuit uses a seven-stage shift register operating with a half-rate clock and provides output signals up to 100 Gb/s. The second circuit contains an eleven-stage shift register operating with a full-rate clock up to 54 Gb/s. Both PRBS generators provide a wide range of data rates down to below 1 Gb/s simply by changing the frequency of the external clock signal without the need of any further adjustments. The integrated circuits provide a trigger output which can be switched between eye and pattern display. Furthermore, they contain additional circuitry to guarantee automatic start after power-on. The circuits are manufactured in a 200-GHz f/sub T/ SiGe bipolar technology. They each have a chip size of 900/spl times/700 /spl mu/m/sup 2/ and consume 1.5 and 1.9 W, respectively.     

A 3$,times,$5-Gb/s Multilane Low-Power 0.18-$mu{hbox {m}}$ CMOS Pseudorandom Bit Sequence Generator

A low-power, three-lane, pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-mum CMOS process to test a multilane multi-Gb/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator was designed to produce three uncorrelated 12-Gb/s PRBS sequences, measurement results included in this paper have been obtained at only 5 Gb/s due to test setup limitations. The prototype employs a CMOS latch optimized to operate at frequencies close to the of the process and a current-mode logic (CML) MUX with modified active inductor loads for better high-speed large-signal behavior. In order to reduce the power consumption, a quarter-clock rate linear feedback shift register (LFSR) core in a power-efficient parallel architecture has been implemented to minimize the use of power-hungry, high-speed circuitry. Further power reduction has been achieved through the clever partitioning of the system into static logic and CML. In addition, the prototype design produces three uncorrelated 12-Gb/s data streams from a single quarter-rate LFSR core, thereby amortizing the power across multiple channels which lowers the power per channel by 3 times. The total measured power consumption at 5 Gb/s is 131 mW per lane and the calculated figure of merit per lane is 0.84 pJ/bit, which is significantly better than previously published designs.     

A Polarization-Independent Subnanosecond 2 $,times,$2 Multicast-Capable Optical Switch Using a Sagnac Interferometer

We design and demonstrate a cost-effective 2times2 ultrafast multicast-capable optical switch (MCOS) based on a Sagnac interferometer. The Sagnac interferometer is composed of a LiNbO₃ phase modulator (PM) with two polarization-maintaining pigtail fibers and a 3-dB polarization-maintaining coupler. The MCOS works at three states: cross, bar, and multicast, in the entire C-band (1525-1565 nm) by controlling the driven voltage of the PM. Polarization- dependence is eliminated by splicing the pigtail fibers of the PM and the 3-dB coupler with 0degand 90deg angles, respectively. The measured switching time is ~0.6 ns. Multiple 2times2 MCOS elements can be constructed into a large nonblocking N x N MCOS matrix.     

Fast Sign Detection for RNS $(2^{n}-1,2^{n},2^{n}+1)$

In this paper, we propose a fast algorithm for sign-extraction of a number given in the Residue Number System $(2^{n}-1,2^{n},2^{n}+1)$ . The algorithm can be implemented using three $n$-bit wide additions, two of which can be done in parallel. It can be used in a wide variety of problems, i.e., in algorithms for dividing numbers in the RNS, or in evaluating the sign of determinant in computational geometry, etc.      

4$,times,$25-Gb/s 40-km PHY at 1310 nm for 100 GbE Using SOA-Based Preamplifier

We present extensive numerical simulations of an optical link deploying four electroabsorption modulated lasers (EMLs) at 25 Gb/s over up to 40 km of standard single-mode fiber. The receiver comprises a semiconductor optical amplifier (SOA) as a preamplifier. We analyze the bit error ratio (BER) along different link lengths under varying conditions such as output power and extinction ratio of the EML transmitters, the noise figure of the SOA preamplifier and the bit and word alignment of the four wavelength channels. We demonstrate that the EML transmitters require a minimum extinction ratio of 8 to 10 dB and a minimum output power of +2 to +4 dBm in order to meet the BER requirements for 100 Gigabit Ethernet (100 GbE) using 4 times 25-Gb/s physical media dependent (PMD) devices. Furthermore, we show that single-channel performance analyses can be used to estimate the behavior for multichannel amplification in the SOA preamplifier.     

A 20-Gb/s silicon bipolar 1:4-demultiplexer IC

This paper presents a 20-Gb/s 1:4-demultiplexer for future fiber-optic transmission systems. It uses an 0.4-μm emitter double polysilicon 21-GHz f_T Si bipolar foundry process. This is the highest data rate of a 1:4-DEMUX reported so far in any technology. The 1:4-DEMUX features a tree-type architecture with one frequency divider and a channel switch circuit. The circuit design was carefully optimized to achieve high speed and moderate power dissipation. It consumes 1.4 W with a single -4.5-V supply     

VLSI Design of Diminished-One Modulo $2^{n}+1$ Adder Using Circular Carry Selection

The diminished-one modulo $2^{n}+1$ addition is an important arithmetic operation for a high-performance residue number system. In this paper, we propose a new circular-carry-selection (CCS) technique for modulo $2^{n}+1$ addition in the diminished-one number domain. The architecture design of CCS modular adder is simple and regular for various bit-width inputs. For actual VLSI implementation, the proposed modular adder can demonstrate its superiority of savings up to 39.5% in AreaxTime and 46.3% in TimexPower performances over those of the previous existing solutions under 180-nm CMOS technology. Finally, the chip area and the clock rate of CCS diminished-one modulo $2^{16}+1$ adder are 26746 $mu{hbox{m}}^{2}$ and 476 MHz, respectively.      

A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check codedecoder

A 1024-b, rate-1/2, soft decision low-density parity-check (LDPC) code decoder has been implemented that matches the coding gain of equivalent turbo codes. The decoder features a parallel architecture that supports a maximum throughput of 1 Gb/s while performing 64 decoder iterations. The parallel architecture enables rapid convergence in the decoding algorithm to be translated into low decoder switching activity resulting in a power dissipation of only 690 mW from a 1.5-V supply     

A 165-Gb/s 4:1 Multiplexer in InP DHBT Technology

This paper presents a 4:1 multiplexer fabricated in InP double heterojunction bipolar transistor (DHBT) technology. The multiplexer works up to 165 Gb/s at a supply voltage of$-hbox3.2~V$consuming 1.6 W. It is a half-rate multiplexer using a multi-phase clock architecture. The main design challenge was to ensure correct timing between clock and data signals.     

A 1-Gb/s, four-state, sliding block Viterbi decoder

To achieve unlimited concurrency and hence throughput in an area-efficient manner, a sliding block Viterbi decoder (SBVD) is implemented that combines the filtering characteristics of a sliding block decoder with the computational efficiency of the Viterbi algorithm. The SBVD approach reduces decode of a continuous input stream to decode of independent overlapping blocks, without constraining the encoding process. A systolic SBVD architecture is presented that combines forward and backward processing of the block interval. The architecture is demonstrated in a four-state, R=1/2, eight-level soft decision Viterbi decoder that has been designed and fabricated in double-metal CMOS. The 9.21 mm×8.77 mm chip containing 150 k transistors is fully functional at a clock rate of 83 MHz and dissipates 3.0 W under typical operating conditions (V_DD=5.0 V, T_A =27°C). This corresponds to a block decode rate of 83 MHz, equivalent to a decode rate of 1 Gb/s. For low-power operation, typical parts are fully functional at a clock rate of greater than 12 MHz, equivalent to a decode rate of 144 Mb/s, and dissipate 24 mW at V_DD =1.5 V, demonstrating extremely low power consumption at such high rates     

A 2$,times,$ 2 Mechanical Optical Switch With a Thin MEMS Mirror

This paper presents the design, fabrication, alignment and experimental tests of a 2times2 mechanical optical switch. The key component of the mirror device is fabricated by the MEMS process that coats both sides with an ultrathin high reflection Au/Cr film (thickness less than 1.8 microns and roughness 5.7 nm) to allow double-sided reflection. The mirror is mounted on a thin metal arm, which is switched by a mechanical relay. Compared to the 4-mirror type of single-sided reflector which is used by other 2times2 optical switches, this configuration significantly reduces the size and number of the components. The optical alignment and the component assembly can rapidly be accomplished by two stages: visual coarse alignment and automatic fine alignment. Due to the feature of an adjustable mirror positioning and orientation, insertion losses can be reduced to a very low level. Experimental results show that the insertion losses, crosstalk, switching time and long-cycle test can all meet the Bellcore 1073 specification requirements.     

A 43-Gb/s full-rate-clock 4:1 multiplexer in InP-based HEMT technology

This paper describes a full-rate-clock 4:1 multiplexer (MUX) in a 0.13-/spl mu/m InP-based HEMT technology for 40-Gb/s and above optical fiber link systems. To reduce output jitter, the serialized data are retimed at the final stage by a retimer, a D-type flip-flop, which has a symmetric layout with an optimized spacing to the ground that minimizes coupling capacitances. A phase adjuster, composed of an exclusive OR and a delay switch, uses external control signals to change each phase of the serialized data and clock entering the retimer and gives a correct timing for the clock to drive the retimer. A clock distributor with a simple wired splitter divides the clock into two clocks with high gain and low current. The MUX integrates 1355 HEMTs formed using electron beam lithography. A chip mounted in a test module operated at up to 47 Gb/s with a power consumption of 7.9 W for a single supply voltage of -5.2 V.     

A Hybrid Electrooptic Microring Resonator-Based $1 times 4times 1$ ROADM for Wafer Scale Optical Interconnects

Pairing high-quality factor $(Q)$ silicon-on-insulator microring resonators with rapidly tunable organic electrooptic claddings has allowed the first demonstration of a silicon-organic hybrid electrooptic reconfigurable optical add/drop multiplexer (ROADM). A coplanar electrode geometry provides up to 0.36 GHz/V of electrooptic voltage tuning for each channel, corresponding to an electrooptic coefficient of $r_{33}=64 hbox{pm/V}$ at wavelengths around 1550 nm. Individual ring resonator devices have 40- $mu{hbox {m}}$ ring radii, 2.7-nm free spectral range, and tuning ranges of 180 GHz. The $1times 4times 1$ ROADM has a footprint of less than 1 ${hbox {mm}}^{2}$ and has been shown to reconfigure in less than a microsecond.      

A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBTlimiting amplifier

A limiting amplifier IC implemented in a silicon-germanium (SiGe) heterojunction bipolar transistor technology for low-cost 10-Gb/s applications is described. The IC employs 20 dB gain limiting cells, input overload protection, split analog-digital grounds, and on-chip isolation interface with transmission lines. A gain enhancement technique has been developed for a parallel-feedback limiting cell. The limiting amplifier sensitivity is less than 3.5 mV_pp at BER=10^-9 with 2-V_pp maximum input (55-dB dynamic range). The total gain is over 60 dB, and S₂₁ bandwidth exceeds 15 GHz at 10-mV_pp input. Parameters S₁₁ and S₂₂ are better than -10 dB in the 10-GHz frequency range. The AM to PM conversion is less than 5 ps across input dynamic range. The output differential voltage can be set from 0.2 to 2 V_pp with IC power dissipation from 250 mW to 1.1 W. The chip area is 1.2×2.6 mm². A 10-Gb/s optical receiver, built with the packaged limiting amplifier, demonstrated -19.6-dBm sensitivity. The IC can be used in 10-Gb/s fiber-optic receivers requiring high sensitivity and wide input dynamic range     

A 5.4 mW/0.07 mm$^{2}$ 2.4 GHz Front-End Receiver in 90 nm CMOS for IEEE 802.15.4 WPAN Standard

An integrated 2.4 GHz CMOS receiver front-end according to the IEEE 802.15.4 standard is presented in this paper. It integrates the overall RF part, from the balun up to the first stage of the channel filter, as well as the cells for the LO signal conditioning. The proposed architecture is based on a 6 MHz low-IF topology, which uses an inductorless LNA and a new clocking scheme for driving a passive mixer. When integrated in a 90 nm CMOS technology, the receiver front-end exhibits an area of only 0.07 mm², or 0.23 mm² when including an input integrated balun. The overall chip consumes 4 mA from a single 1.35 V supply voltage and it achieves a 35 dB conversion gain from input power in dBm to output voltage in dBvpk, a 7.5 dB NF value, -10 dBm of IIP3 and more than 32 dB of image rejection.     

1$,times,$ 16 Pt/4H-SiC Schottky Photodiode Array for Low-Level EUV and UV Spectroscopic Detection

This letter reports on a 1$,times,$ 16 Pt/4H-SiC Schottky photodiode array with a total detection area of 136.5 ${hbox{mm}}^{2}$ operating at the wavelength from 400 nm down to 7.5 nm. The array has an ultra low leakage current of 6.4 and 51 fA at $ - {hbox{0.4}} $ and $ - {hbox{5}}~{hbox{V}}$, respectively. In the vacuum ultraviolet (UV) range from 200 nm down to 10 nm, the quantum efficiency (QE) falls to a minimum of 30% at 160 nm, exceeds 100% at wavelengths shorter than 61 nm, and reaches 10 e-/photon at 10 nm, indicating the array has a high sensitivity. The maximum QE in the near UV range is 78% at 230 nm. The spectral detectivity is higher than 10$ ^{15}~{hbox{cmHz}}^{1/2}/{hbox{W}}$ in the wavelength range from 350 nm down to 7.5 nm. Crosstalk between adjacent pixels is investigated. A UV spectroscopic system using the photodiode array with a fine dispersion resolution of 1.5 nm/pixel has been demonstrated.      

A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-/spl mu/m standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 2/sup 31/-1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10/sup -6/ for 2/sup 31/-1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply.     

A Combined Circuit for Multiplication and Inversion in ${rm GF}(2^{m})$

A combined circuit for multiplication and inversion in ${rm GF}(2^{m})$ is proposed. In order to develop a combined circuit, we start with combining the most significant bit first multiplication algorithm and the modified extended Euclid's algorithm by focusing on the similarities between them. Since almost all hardware components of the circuits are shared by multiplication and inversion, the combined circuit can be implemented with significantly smaller hardware than that necessary to implement both multiplication and inversion separately. By logic synthesis, the area of the proposed circuit is estimated to be approximately over 15% smaller than that of previously proposed combined multiplication/division circuits.      

Full-Field Electronic Dispersion Compensation of a 10 Gbit/s OOK Signal Over 4$,times,$ 124 km Field-Installed Single-Mode Fibre

We experimentally demonstrate the use of full-field electronic dispersion compensation (EDC) to achieve a bit error rate of 5times10^{- 5} at 22.3 dB optical signal-to-noise ratio for single-channel 10 Gbit/s on-off keyed signal after transmission over 496 km field-installed single-mode fibre with an amplifier spacing of 124 km. This performance is achieved by designing the EDC so as to avoid electronic amplification of the noise content of the signal during full-field reconstruction. We also investigate the tolerance of the system to key signal processing parameters, and numerically demonstrate that single-channel 2160 km single mode fibre transmission without in-line optical dispersion compensation can be achieved using this technique with 80 km amplifier spacing and optimized system parameters.