A 3$,times,$5-Gb/s Multilane Low-Power 0.18-$mu{hbox {m}}$ CMOS Pseudorandom Bit Sequence Generator

A low-power, three-lane, pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-mum CMOS process to test a multilane multi-Gb/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator was designed to produce three uncorrelated 12-Gb/s PRBS sequences, measurement results included in this paper have been obtained at only 5 Gb/s due to test setup limitations. The prototype employs a CMOS latch optimized to operate at frequencies close to the of the process and a current-mode logic (CML) MUX with modified active inductor loads for better high-speed large-signal behavior. In order to reduce the power consumption, a quarter-clock rate linear feedback shift register (LFSR) core in a power-efficient parallel architecture has been implemented to minimize the use of power-hungry, high-speed circuitry. Further power reduction has been achieved through the clever partitioning of the system into static logic and CML. In addition, the prototype design produces three uncorrelated 12-Gb/s data streams from a single quarter-rate LFSR core, thereby amortizing the power across multiple channels which lowers the power per channel by 3 times. The total measured power consumption at 5 Gb/s is 131 mW per lane and the calculated figure of merit per lane is 0.84 pJ/bit, which is significantly better than previously published designs.     

2.5 V 43–45 Gb/s CDR Circuit and 55 Gb/s PRBS Generator in SiGe Using a Low-Voltage Logic Family

An alternative design approach for implementing high-speed digital and mixed-signal circuits is proposed. It is based on a family of low-voltage logic gates with reduced transistor stacking compared to series-gated emitter-coupled logic. It includes a latch, an xor gate, and a MUX with mutually compatible interfaces. Topologies and characteristics of the individual gates are discussed. Closed-form propagation delay expressions are introduced and verified with simulations. The proposed design style was used to implement a 43–45 Gb/s CDR circuit with a 600MHz locking range and a 55 Gb/s PRBS generator with a$2^7!-!1$sequence length. The circuits were fabricated in a SiGe BiCMOS technology with$f _T = 120~hboxGHz$. Corresponding measurement results validate the proposed design style and establish it as a viable alternative to emitter-coupled logic in high-speed applications. Both circuits operate from a 2.5 V nominal power supply and consume 650 mW and 550 mW, respectively.     

2.5Gb/s单片时钟恢复数据判决与1:4分接集成电路的设计

用0.25μm CMOS工艺实现一个复杂的高集成度的2.5Gb/s单片时钟数据恢复与1:4分接集成电路.对应于2.5Gb/s的PRBS数据(231-1),恢复并分频后的625MHz时钟的相位噪声为-106.26dBc/Hz@100kHz,同时2.5Gb/s的PRBS数据分接出4路625Mb/s数据.芯片面积仅为0.97mm×0.97mm,电源电压3.3V时核心功耗为550mW.     

Study of a SiGe-HBT-based 1：2 demultiplexer IC up to 100 Gb/s rate

An ultra-high speed 1:2 demultiplexer for optical fiber communication systems is designed utilizing the IHP 0.25 μm SiGe BiCMOS technology. The latch of the demultiplexer core circuit is researched. Based on the current measurement condition, a high-gain and wide-bandwidth clock buffer is designed to drive large load. Transmission line theory for ultra-high speed circuits is used to design matching network to solve the matching problem among the input, output and internal signals. The transient analysis sho...     

2.5Gb/s 16:1MUX IC Design with CMOS

A low-power and high-speed 16:1 MUX IC designed for optical fiber communication based on TSMC 0.25 μm CMOS technology is presented. A tree-type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak-to-peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8 mm2.     

2.5 Gb／s 16：1 MUX IC Design with CMOS

A low--power and high--speed 16.-1 MUX IC designed for optical fiber communication based on TSMC 0.25μm CMOS technology is presented. A tree—type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak—to—peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is 1.8mm^2.     

2.5-Gb/s low-jitter low-power monolithically integrated optical receiver

A high-scale integrated optical receiver including a preamplifier, a limiting amplifier, a clock and data recovery (CDR) block, and a 1:4 demultiplexer (DEMUX) has been realized in a 0.25???m CMOS technology. Using the loop parameter optimization method and the low-jitter circuit design technique, the rms and peak-to-peak jitter of the recovered 625-MHz clock are 9.4 and 46.3?ps, respectively, which meet the jitter specifications stipulated in ITU-T recommendation G.958. The recovered and frequency divided 625?MHz clock has a phase noise of ?83.8 dBc/Hz at 20?kHz offset in response to 2.5?Gb/s PRBS input data (2²³?C1), and the 2.5?Gb/s PRBS data has been demultiplexed into four 625?Mb/s data. The power dissipation is only 0.3?W under a single 3.3 V supply (excluding output buffers).     

A 40–44 Gb/s 3× Oversampling CMOS CDR/1:16 DEMUX

A CMOS CDR and 1:16 DEMUX fabricated in a low-cost 90 nm bulk CMOS process operates at 40-44 Gb/s and dissipates 910 mW. A quarter-rate hybrid phase-tracking/3times blind-oversampling architecture is used to improve jitter tolerance, reduce the need for high-power CML circuits, and enable frequency acquisition without a reference clock. Input data are sampled using a 24-phase distributed VCO, and a digital CDR recovers 16 bits and a 2.5 GHz clock from 48 demultiplexed samples spanning 16 UI. Conformance to the ITU-T G.8251 jitter tolerance mask (BER <10^-12 with a 2³¹-1 PRBS source) is demonstrated using both an on-chip and an external BERT.     

A 20-Gb/s CMOS multichannel transmitter and receiver chip set forultra-high-resolution digital displays

A multichannel transmitter (TX) and receiver (RX) chip set operating at 20 Gb/s (5 Gb/s×4 ch) has been developed by using 0.25-μm CMOS technology. To achieve multichannel data transmission and high-speed operation, the chip set features: (1) circuits for compensating the phase difference between multiple RX chips, which is due to data skew resulting from different lengths of transmission cables, and for compensating the frequency difference between the system clocks of the TX and RX chips; (2) a self-alignment phase detector with parallel output for a high-speed data-recovery circuit; and (3) a fully pipelined 8B10B encoder. At a 2.5-V power supply, the power consumption of the TX chip during 5-Gb/s operation is 500 mW and that of the RX chip is 750 mW. Four of these TX/RX chip sets can provide an aggregate bandwidth of 20 Gb/s     

A 3.3-V 21-Gb/s PRBS generator in AlGaAs/GaAs HBT technology

We present a pseudorandom bit sequence (PRBS) generator that outputs a 2⁷-1 bit pattern at rates up to 21 Gb/s. The circuit is implemented in a 40-GHz AlGaAs/GaAs heterojunction bipolar transistor (HBT) standard production process, operates from a single 3.3-V power supply, and consumes 1.1 W of power. We discuss variations of PRBS architecture and digital circuit topologies which exploit unique characteristics of AlGaAs/GaAs HBT devices. The work demonstrates the feasibility of using AlGaAs/GaAs HBT technology with low-voltage/low-power design techniques in complex high-speed circuits     

A 20-Gb/s 1:2 demultiplexer in 0.18-μm CMOS

A 1:2 demultiplexer (DEMUX) has been designed and fabricated in SMIC's standard 0.18-μm CMOS technology, based on standard CML logic and current-density-centric design philosophy. For the integrity of the DEMUX and the reliability of the internal operations, a data input buffer and a static latch were adopted. At the same time, the static latch enables the IC to work in a broader data rate range than the dynamic latch. Measurement results show that under a 1.8-V supply voltage, the DEMUX can operate reliably at any data rate in the range of 5-20 Gb/s. The chip size is 875 × 640 μm2 and the power consumption is 144 mW, in which the core circuit has a share of less than 28%.     

Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS

Low-power building blocks for a serial transmitter operating up to 86 Gb/s are designed and implemented in a 130-nm SiGe BiCMOS technology with 150-GHz SiGe f_T HBT. Design techniques are presented which aim to minimize high-speed building block power consumption. They include lowering the supply voltage by employing a true BiCMOS high-speed logic family, as well as reducing current consumption by trading off tail currents for inductive peaking. A serial transmitter testchip consuming under 1 W is fabricated and operation is verified up to 86 Gb/s at room temperature (92 Gb/s and 71 Gb/s at 0degC and 100degC, respectively). The circuit operates from a 2.5-V supply voltage, which is the lowest supply voltage for circuits at this data rate in silicon technologies reported to date.     

A 10-Gb/s 16:1 multiplexer and 10-GHz clock synthesizer in0.25-μm SiGe BiCMOS

A 10-Gb/s 16:1 multiplexer, 10-GHz clock generator phase-locked loop (PLL), and 6 × 16 b input data buffer are integrated in a 0.25-μm SiGe BiCMOS technology. The chip multiplexes 16 parallel input data streams each at 622 Mb/s into a 9.953-Gb/s serial output stream. The device also produces a 9.953-GHz output clock from a 622- or 155-MHz reference frequency. The on-board 10-GHz voltage-controlled oscillator (VCO) has a 10% tuning range allowing the chip to accommodate both the SONET/SDH data rate of 9.953 Gb/s and a forward error correction coding rate of 10.664 Gb/s. The 6 × 16 b input data buffer accommodates ±2.4 ns of parallel input data phase drift at 622 Mb/s. A delay-locked loop (DLL) in the input data buffer allows the support of multiple input clocking modes. Using a clock generator PLL bandwidth of 6 MHz, the 9.953-GHz output clock exhibits a generated jitter of less than 0.05 UI_P-P over a 50-kHz to 80-MHz bandwidth and jitter peaking of less than 0.05 dB     

基于0.18μm SiGe BiCMOS工艺的高速比较器分析与设计

基于预放大正反馈锁存比较理论,给出了一种8bit 8Gs/s高速比较器的设计.该比较器采用预放大器结构以提高分辨率、加快比较过程,采用主从锁存器降低亚稳态发生概率,采用输出缓冲器改善输出波形、提供测试接口;在HHNEC 0.18μm SiGe BiCMOS工艺下,采用Cadence Spectre进行仿真,结果显示,该比较器精度为4mV,输出摆幅±300mV,锁存时间37ps,过驱动恢复时间22ps,功耗约57mW,表现出良好的性能.     

A 2.5-3.125-Gb/s quad transceiver with second-order analog DLL-based CDRs

This paper describes a 2.5-3.125-Gb/s quad transceiver with second-order analog delay-locked loop (DLL)-based clock and data recovery (CDR) circuits. A phase-locked loop (PLL) is shared between receive (RX) and transmit (TX) chains. On each RX channel, an amplifier with user-programmable input equalization precedes the CDR. Retimed data then goes to an 1:8/1:10 deserializer. On the TX side, parallel data is serialized into a high-speed bitstream with an 8:1/10:1 multiplexer. The serial data is introduced off-chip through a high-speed CML buffer having single-tap pre-emphasis. Proposed DLL-based CDR can tolerate large frequency offsets with no jitter tolerance degradation due to its second-order PLL-like nature. Also, this study introduces an improved charge-pump and an improved phase-interpolator. Fabricated in a 0.15-/spl mu/m CMOS process, the 1.9-mm/sup 2/ transceiver front-end operates from a single 1.2-V supply and consumes 65-mW/channel of which 32 mW is due to the CDR. CDR jitter generation and high-frequency jitter tolerance are 5.9 ps-rms and 0.5 UI, respectively, for 3.125 Gb/s, 2/sup 23/-1 PRBS input data with 800-ppm frequency offset.     

A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology

We report a receiver for four-level pulse-amplitude modulated (PAM-4) encoded data signals, which was measured to receive data at 22 Gb/s with a bit error rate (BER) <10/sup -12/ at a maximum frequency deviation of 350 ppm and a 2/sup 7/-1 PRBS pattern. We propose a bit-sliced architecture for the data path, and a novel voltage shifting amplifier to introduce a programmable offset to the differential data signal. We present a novel method to characterize sampling latches and include them in the data path. A current-mode logic (CML) biasing scheme using programmable matched resistors limits the effect of process variations. The receiver also features a programmable signal termination, an analog equalizer and offset compensation for each sampling latch. The measured current consumption is 207 mA from a 1.1-V supply, and the active chip area is 0.12 mm/sup 2/.     

Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS

This paper presents low-voltage circuit topologies for 40-Gb/s communications in 90-nm and 65-nm CMOS. A retiming flip-flop implemented in two different 90-nm CMOS technologies employs a MOS-CML Master-Slave latch topology with only two vertically stacked transistors. Operation at 40 Gb/s is achieved by a combination of low and high-V_T MOSFETs in the latch. Full-rate retiming with jitter reduction is demonstrated up to 40 Gb/s. Low-power broadband amplifiers based on resistor-inductor transimpedance feedback are realized in 90-nm and 65-nm CMOS to investigate the portability of high-speed building blocks between technology nodes. Experiments show that the transimpedance amplifier based on the CMOS inverter can reach 40-Gb/s operation with a record power consumption of 0.15 mW/Gb/s. A comparison between CMOS technologies underlines the importance of General Purpose rather than Low Power processes for high-speed digital design.     

A 34 Gb/s Distributed 2:1 MUX and CMU Using 0.18$muhbox m$CMOS

A 34 Gb/s 2:1 serializer consisting of a CMOS MUX and CMU using a 0.18$muhbox m$SiGe BiCMOS process is presented. The serializer is based on distributed amplifier topology realized using spiral inductors. The circuit also includes an on-chip 2-channel$2^7-1$PRBS generator. The 34 Gb/s serial output has single-ended voltage swing of 380 mV with rise/fall time of 13 ps, and measured ISI is less than 5 ps p-p.     

2.5Gb/s/ch 0.18μm CMOS数据恢复电路

设计了一个应用于SFI-5接口的2.5Gb/s/ch数据恢复电路.应用一个延迟锁相环,将数据的眼图中心调整为与参考时钟的上升沿对准,因而同步了并行恢复数据,并降低了误码率.采用TSMC标准的0.18μm CMOS工艺制作了一个单通道的2.5Gb/s/ch数据恢复电路,其面积为0.46mm2.输入231-1伪随机序列,恢复出2.5Gb/s数据的均方抖动为3.3ps.在误码率为10-12的条件下,电路的灵敏度小于20mV.     

A 50-mW/ch 2.5-Gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking

This paper describes a 2.5-Gb/s/ch digital data recovery (DR) circuit for the SFI-5 interface. Although minimizing the circuit area has become critical in multibit interfaces such as the SFI-5, few studies have proposed a practical method of reducing the area of data recovery circuits. We introduce a digital-PLL-type DR circuit design with eye-tracking, which we developed to minimize the circuit area and power consumption without degrading tolerance against jitter. This novel method of data recovery enabled us to simplify the circuit design against process, voltage, and temperature variations. Design considerations on how to eliminate high-frequency jitter and how to track long-term wander are described. The design for 2.5-GHz clock distribution is also discussed. The area of the DR circuit, fabricated with 0.18-/spl mu/m SiGe BiCMOS technology, is 0.02 mm/sup 2//ch, and its power consumption is 50 mW/ch at 1.8 V. The measured tolerance against jitter at 2.5 Gb/s is 0.7 UI peak-to-peak, which satisfies the jitter specifications for the SFI-5.