Advanced fault collapsing [logic circuits testing]

The partitioning of faults into equivalence classes so that only one representative fault per class must be explicitly considered in fault simulation and test generation, called fault collapsing, is addressed. Two types of equivalence, which are relevant to the work reported, are summarized. New theorems on fault equivalence and dominance, forming the basis of an algorithm that collapses all the structurally equivalent faults in a circuit, plus many of the functionally equivalent faults, are presented. Application of the algorithm to a set of benchmark circuits establishes that identification of functionally equivalent faults is feasible, and that, in some cases, they are a large fraction of the faults in a circuit. The collapsing algorithm applies not only to combinational designs but to synchronous sequential circuits as well     

Functional fault models for analog circuits

For devices containing analog integrated circuits, the appropriate fault models are those that describe components at the functional level. Functional models proposed in the past have been too complicated for practical use. The models proposed here form the basis of simpler test selection techniques for analog ICs     

Optical components for digital optical circuits

The present status of all-optical computing for digital logic and information processing is reviewed briefly. Computing architectures that take advantage of the parellelism and interconnect freedom that optics offers are addressed. In particular demonstrator circuits employing optically bistable components are described.     

Fast fault simulation for nonlinear analog circuits

A new method of transient fault simulation uses dc bias grouping of faulty circuits and decreases the number of Newton-Raphson iterations needed to reach a solution. An experimental tool implementing this method achieves a speedup of 20% to 30% on a flat netlist.     

基于VIIS-EM平台的虚拟数字集成电路测试仪的设计

基于模块化虚拟仪器的设计思想,设计出一种以VIIS-EM平台为核心,以LabVIEW为工具进行图形化编程的虚拟数字集成电路测试仪,并论述了其实现方案。重点分析了硬件电路的搭建思路和软件的控制流程,最后给出虚拟数字集成电路测试仪的测试结果。     

Dynamic functional testing for VLSI circuits

The author discusses the two main problems of dynamic testing (i.e. testing while the simulator is running), namely the design of a high-level vector-generation language and the design of the interface between the vector generator and the simulator. He offers guidelines for designing a high-level vector-generation language as well as several examples written in FHDL, a driver language developed at the University of South Florida. The author also describes a solution to interface design that is based on a special interface data structure that supports several styles of vector generators and interactive circuit debugging     

Generating tests for delay faults in nonscan circuits

A delay test method that allows any sequential-circuit test generation program to produce path delay tests for nonscan circuits is presented. Using this method, a given path is tested by augmenting the netlist model of the circuit with a logic block, in which testing for a certain single stuck-at fault is equivalent to testing for a path delay fault. The test sequence for the stuck-at fault performs all the necessary delay fault test functions: initialization, path activation, and fault propagation. Results on benchmarks are presented for nonscan and scan/hold modes of testing     

高速数字电路的串音现象研究

在数字信号的高速传输中,信号完整性的问题已越来越受到硬件工程师的高度关注。串音现象是信号完整性的问题之一,随着印刷电路板的布线密度增加,尤其是长距离并行线的布局,更容易发生串音现象。从上升沿时间、跨分割平面、传输模式、中间保护线是否接地四个方面阐述了影响串音的因素,并提出了相应的解决方法。     

A generalized fault simulator for combinational logic circuits

A generalized approach to the design of fault simulator using a library of simulation primitives is presented in this paper. A comprehensive set of simulation primitives has been developed using C programming language on the IBM PC. This library of simulation primitives has been used in realizing a fault simulator for automatic test pattern generation in combinational logic circuits. The fault simulator employs a combination of random pattern generation, concurrent fault simulation and the FAN algorithm for generating the complete set of test vectors to cover all the faults in the fault dictionary of the circuit under test. The library of simulation primitives is general enough to facilitate the development of fault simulators using any other test algorithms such as DALG or PODEM.     

基于小波网络的模拟电路故障诊断

根据实际应用模拟电路中所存在噪声的问题,提出利用相位差来进行故障诊断的新方法.针对噪声存在于各个频段,利用不同频段的带通滤波器对诊断电路进行滤波,得到各种频率的信号,在正常模式和故障模式下分别对这些信号进行相位差和幅值差的特征提取,建立故障字典;然后利用小波神经网络具有非线性映射的优势.对各种状态下的故障特征进行分类决策,从而实现故障诊断.此方法通过实例证明不但诊断准确,而且很切合实际.     

A comprehensive fault diagnosis technique for reversible logic circuits

Fault diagnosis is a complex and challenging problem in reversible logic circuits. The paper proposes a novel fault diagnosis technique for missing control faults in reversible logic circuits. The main focus of this technique is to extract the unique fault signature for each missing control fault in the circuit. The fault signatures are the sequences of test vectors to identify the location of the faults. Based on these fault signatures a unique fault diagnosis tree is built. Our proposed fault diagnosis algorithm is used to traverse the fault diagnosis tree to find the presence and location of the fault. The traversal process is simple and fast. The algorithm executes in linear time and experimental results for benchmark circuits show the reduction of test patterns compared to earlier works.     

一种大规模模拟电路快速故障诊断新方法

针对传统大规模模拟电路故障诊断方法在多故障条件下的故障定位过程复杂、测前工作量大等问题, 提出了一种新的故障诊断方法——成组撕裂法。将大规模模拟电路按照拓扑特性和成组撕裂准则进行撕裂, 得到低维度的故障特征向量; 基于模式识别思想, 选用具有高度并行分类能力的神经网络作为分类器, 隐含层传递激发函数选择具有快速收敛特性的小波函数。经仿真验证该方法能实现故障特征向量的快速分类并得出故障诊断结果。与目前已有的互校验（multiple-test-condition, MTC）和交叉撕裂搜索法相比, 该方法有测前工作量小、诊断次数和计算量少、对多故障检测能力和工程实践性强等特点。     

Detection of all single and multiple stuck-at faults in combinational digital circuits using index vector testing

A new method for the testing of combinational digital circuits is presented. The method is based on the concept of the ‘index vector’ of a switching function (Gupta 1987), and represents an extension of syndrome testing. A large percentage of syndrome untestable faults are found to be index vector testable. An approach to testing index vector untestable circuits that relies only on the function realized by the circuit and is independent of the circuit topology is presented. The method can be used for the detection of both single and multiple stuck-at faults in a combinational circuit.     

模拟电路故障诊断新方法

提出了一种新颖的基于多小波神经网络的模拟电路故障诊断方法。介绍了多小波的原理,分析了多小波神经网络的结构、逼近性质及多小波神经网络的算法,提出了用多小波来处理故障信号,提取故障特征向量输入给神经网络,从而进行模拟电路故障诊断。由于多小波函数具有连续、对称性及支撑集短等一系列优点,所以用多小波神经网络来进行模拟电路故障诊断比一般的小波神经网络具有诊断精度高、诊断速度快的优点。给出了仿真诊断实例,验证了该方法的有效性。     

A probabilistic approach for testing large-scale integrated circuits

If the statistics available from various process steps involved in the fabrication of large-scale integrated logic circuit chips indicate that the computed probability of each circuit path operating properly is greater than 1/2, then a reliable screening test procedure can be devised. A reliable reference standard from untested chips, or modules, can be constructed, and such a standard reference can be used in all test procedures in which circuit testing is based on comparison.     

Exploiting deterministic TPG for path delay testing

Detection of path delay faults requires two-pattern tests.BIST technique provides a low-cost test solution.This paper proposes an approach to designing a cost-effective deterministic test pattern generator(IPG) for path delay testing.Given a set of pre-generated test-pattern generator(TPG) for path delay testing.Given a set of pre-generated test-pairs with pre-determined fault coverage,a deterministic TPG is synthesized to apply the given test-pair set in a limited test time.To achieve this objective,configuable linear feedback shift register(LFSR)structures are used.Techniques are developed to synthesize such a TPG.which is used to generate an unordered deterministic test-pair set.The resulting TPG is very efficient in terms of hardware size and speed performance.SImulation of academic benchmark circuits has given good results when compared to alternative solutions.     

Robust delay dependent fault estimation for a class of interconnected nonlinear time delay systems

This paper focuses on the problem of fault estimation for a class of interconnected nonlinear systems with time varying delays. In contrast to the common assumption imposed on the problem in most literature, here, there is no need for the delay rate to be less than one. Both actuator and component faults are considered within the general fault model invoked as multiplicative faults in this study. Robust adaptive observers are used to detect and estimate simultaneously the states and the parameter faults in each subsystem. The designed observers ensure a prescribed H _∞ performance level for the fault estimation error, irrespective of the uncertainties which are assumed here to be the unknown interconnections between the subsystems. With the aid of H _∞ performance index, the common assumption regarding the observer matching condition is no longer required. Sufficient conditions for asymptotic stability of the observers are derived via a matrix inequality approach with the aid of LyapunovKrasovskii function. Finally, a simulation example is presented to show the validity and feasibility of the proposed method.

     

Bounded algebra and current-mode digital circuits

This paper proposes two bounded arithmetic operations,which are easily realized with current signals.Based on these two operations,a bounded algebra system suitable for describing current-mode digital circuits is developed and its relationship with the Boolean algebra,which is suitable for representing voltagemode digital circuits,is investigated.Design procedure for current-mode circuits using the proposed algebra system is demonstrated on a number of common circuit elements which are used to realize arithmetic operations,such as adders and multipliers.     

The dynamics of digital circuits with memory for ternary signals

The paper examines a digital automaton with memory operating in the ternary alphabet (0, 1, ). The problem of analytical determination of ternary processes on automaton outputs and inside the automaton from given ternary processes on the automaton inputs is considered. An algorithm is proposed reducing this problem to standard determination of the processes in an automaton with the alphabet (0, 1).Translated from Kibernetika, No. 4, pp. 19–25, July–August, 1989.