Static linearity error analysis of subranging A/D converters

An 8- to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits a reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with individual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate f _sand the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.     

A 15-b pipelined CMOS floating-point A/D converter

A floating-point approach can be used to extend the dynamic range of analog-to-digital (A/D) converters in applications where large signals need not be encoded with a precision greater than that required for small signals. Owing to the nonuniform nature of the quantization in a floating-point A/D converter (FADC), it is possible to sacrifice a large peak signal-to-noise ratio to obtain savings in power dissipation and area while achieving a large dynamic range. A 15-b switched-capacitor pipelined FADC has been designed with a 10-b mantissa and an exponent that provides an additional 5 bits of dynamic range. The increased dynamic range is obtained with a three-stage pipelined variable gain amplifier, while the mantissa is determined by a uniform 10-b pipelined A/D converter. An experimental prototype of the converter has been integrated in a 0.5 μm CMOS technology. It achieves a dynamic range of 90 dB at a conversion rate of 20 MSamples/s with a total power dissipation of 380 mW     

一种全差分双通道采样保持的流水线操作AD变换器

介绍了一种基于双通道采样保持电路的流水线操作 AD变换器。设计结合了并行流水线转换电路的思想 ,从而能够有效提高转换速率 ,但是较之并行流水线结构 ,使用的运放较少 ,功耗低 ,而且可以避免并行结构可能存在的匹配问题。这个电路采用 0 .3 5 μm CMOS工艺实现 ,在 Cadence Spectre S环境下通过仿真验证 ,转换速率 40 MS/s时 ,能达到 1 0位精度     

补偿流水线A/D转换器级间增益误差的后台校正技术

在分析流水线A/D转换器中残差放大器电容匹配性和运放的有限增益引起的误差对信号传输影响的基础上,基于冗余位校正流水线A/D转换器结构,通过在信号通路中加入由伪随机码控制的校正信号测量上述误差的方法,在后台校正输出数字信号中的级间增益误差。通过Mat-lab对A/D转换器进行了系统级仿真。结果表明,12位A/D转换器系统的SFDR提高了31.8dB,SNDR提高了11.5 dB,INL减小了3.43 LSB,DNL减小了0.21 LSB。     

A 10 b 50 MHz pipelined CMOS A/D converter with S/H

A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 μm CMOS technology     

A 3 V Wideband CMOS Switched-Current A/D-Converter Suitable for Time-Interleaved Operation

The simulated and measured performance of an experimental 10-b wideband CMOS A/D converter design is presented. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to implement a 1.5-b/stage pipelined architecture in order to evaluate the switched-current technique for digital radio applications. With f _in = 1.83, the measured spurious-free dynamic range (SFDR) is 60.3 dB and the signal-to-noise-and-distortion ratio (SNDR) = 46.5dB at 3 MS/s. Although this 3 V design was fabricated in a standard digital 5 V, 0.8 m CMOS process, a high bandwidth was achieved. Since the ADC maintains an SNDR 40 dB for input frequencies of more than 20 MHz, it has the highest input bandwidth reported for any CMOS switched-current A/D-converter implementation. Its sample rate can be increased by parallel, time-interleaved, operation. Measurement results are compared with the measured performance of other wideband switched-current A/D converters and found to be competitive also with respect to area and power efficiency.     

A noise-shaping coder topology for 15+ bit converters

A topology for high-precision noise-shaping converters that can be integrated on a standard digital IC process is presented. This topology uses a multibit noise-shaping coder and a novel form of dynamic element matching to achieve high accuracy and long-term stability without requiring precision matching of components. A fourth-order noise-shaping D/A (digital-to-analog) conversion system using a 3-b quantizer and a dynamic element-matching internal D/A converter, fabricated in a standard double-metal 3-μm CMOS process, achieved 16-bit dynamic range and a harmonic distortion below -90 dB. This multibit noise-shaping D/A conversion system achieved performance comparable to that of a 1-bit noise-shaping D/A conversion system that operated at nearly four times its clock rate     

Switched-current delta-sigma A/D converters

Switched-current oversampling A/D converters are the ideal choice for mixed analog/digital design due to their complete compatibility with digital CMOS process and high tolerance to process variation. This paper presents a tutorial discussion on all the aspects of switched-current oversampling A/D converters, including structures, circuits, and practical issues. Three different modulator structures and six different types of switched-current circuits were used with an emphasis on low-voltage operation. Eight 3.3-V oversampling A/D converters were implemented and measured, and another one 1.2-V oversampling A/D converter was also implemented but yet to be measured.     

A 5-bit building block for 20 MHz A/D converters

Describes a monolithic, fully parallel 5-bit A/D converter. The chip is fabricated using a standard metal-gate enhancement depletion NMOS technology with 7 /spl mu/m minimum features. The chip contains 31 strobed comparators, latches, combinational logic, a 5/spl times/31 bit ROM, TTL buffers and a 4-bit DAC. This makes it a building block for two-step parallel 8-bit A/D converters. Maximum conversion rate is 20 MHz and DC linearity is better than /SUP 1///SUB 4/ LSB for 80 mV quantization step size.     

Pipelined multibit oversampled digital-to-analog converters with capacitor averaging

A combination of pipelined architecture and dynamic element matching technique is applied to multibit oversampled D/A (digital to analog) converters. The approach translates the harmonic distortion components of the nonideal internal DAC (digital-to-analog converter) of the oversampled DAC to high-frequency components, which can then be filtered out by the analog low-pass filter for anti-imaging. Computer simulations have confirmed that with this approach a third-order oversampled DAC employing a 3-bit quantizer, a 3-bit pipelined internal DAC with a random mismatch of 0.1%, can achieve a 94-dB dynamic range with an oversampling ratio of 64 while eliminating the harmonic distortion.This work was supported by NSERC (Canada).     

A new high-speed periodic-threshold comparator for use in aJosephson A/D converter

A Josephson comparator based on a nonhysteric one-junction superconducting quantum interference device (SQUID) for use in a periodic-threshold A/D (analog-to-digital) converter is discussed. Simulations show that a 4-bit A/D converter using this comparator could have a sampling rate of >20 GHz with an analog signal bandwidth of >10 GHz. This performance represents a factor-of-greater-than-five improvement over that of other periodic-threshold A/D converters, which are based on two- or three-junction SQUIDs     

A full Nyquist 15 MS/s 8-b differential switched-current A/Dconverter

This paper describes the architecture and circuit design of an experimental 8-b differential 15 MS/s CMOS A/D converter, implemented using the switched-current (SI) technique. Particular emphasis has been given to maintaining analog bandwidth and hence the effective number of bits right across the input Nyquist band. Individual cells have also been optimized for inherent accuracy to achieve good performance in a simple uncorrected conversion algorithm. The converter is fabricated in a standard 0.8 μm 5 V digital CMOS process and occupies 2.4 mm²      

A high-speed and high-resolution CMOS comparator with three-stage preamplifier

The accuracy of A/D and D/A converters depend largely upon their inner comparators. To guarantee 12-bit high resolution for an A/D converter, a precise CMOS comparator consisting of a three-stage differential preamplifier together with a positive feedback latch is proposed. Circuit structure, gain, the principle of input offset voltage storage and latching time constant for the comparator will be analyzed and optimized in this article. With 0.5 μm HYNIX mixed signal technology, the simulation result shows that the circuit has a precision of 400 μV at 20 MHz. The test result shows that the circuit has a precision of 600 μV at 16 MHz, and dissipates only 78 μW of power dissipation at 5 V. The size of the chip is 210 × 180 μm2. The comparator has been successfully used in a 10 MSPS 12-bit A/D converter. The circuit can be also used in a less than 13-bit A/D converter.     

A 12-bit 1-Msample/s capacitor error-averaging pipelined A/Dconverter

A capacitor error-averaging technique is applied to perform an accurate multiply-by-two (×2) function required in high-resolution pipelined analog-to-digital (A/D) converters. Errors resulting from capacitor mismatch and switch feedthrough are corrected in the analog domain without using digital calibration and/or trimming. A differential pipelined A/D converter that achieves a throughput rate of 1 Msample/s with 12 bits of linearity has been made and evaluated. A prototype pipelined A/D converter implemented using a double-poly 1.75-μm CMOS process consumes 400 mW with a 5-V single supply and occupies 14 mm², including all digital logic and output buffers     

A wide-band 10-b 20 Ms/s pipelined ADC using current-mode signals

A 10-b pipelined analog-to-digital converter (ADC) is presented which makes extensive use of differential current-mode signals. The converter samples at 20 MHz and has an analog bandwidth exceeding 100 MHz. The architecture incorporates the design of a wide-bandwidth, fully differential current-in, current-out track-and-hold (T/H) amplifier differential flash A/D converters, and fully segmented D/A converters. A unique reference distribution technique allows precise trimming of the gains of the DACs and flash converters. The converter is built on a 2-μm BiCMOS process with thin film resistors     

Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier

This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSample/s.     

A 10-bit 50-MS/s subsampling pipelined ADC based on SMDAC and opamp sharing

This paper describes a 10-bit,50-MS/s pipelined A/D converter(ADC) with proposed area- and power-efficient architecture.The conventional dedicated sample-hold-amplifier(SHA) is eliminated and the matching requirement between the first multiplying digital-to-analog converter(MDAC) and sub-ADC is also avoided by using the SHA merged with the first MDAC(SMDAC) architecture,which features low power and stabilization.Further reduction of power and area is achieved by sharing an opamp between two successive pi...     

Time interleaved converter arrays

High-speed monolithic converters normally use a variation of the flash technique, which 2/SUP n/ comparators in parallel to obtain a fast n-bit conversion. Although this method allows for high converter bandwidth, it is not very area efficient, and results in large die sizes for even modest resolution converters. In the technique presented here, a number of small but area efficient converters are operated in a time-interleaved fashion to achieve the bandwidth of a flash circuit, but in a substantially smaller area. This technique is analyzed with respect to noise and distortion resulting from nonideal array characteristics, and is demonstrated by way of a four-way array test-chip. This chip consists of four time-interleaved 7-bit weighted-capacitor A/D converters fabricated in a 10 /spl mu/m metal-gate CMOS process. Full 7-bit linearity is maintained up to a 2.5 MHz conversion rate, with operation at reduced linearity continuing to approximately 4 MHz. The design of this chip, and anticipated characteristics if fabricated in a modern 4-5 /spl mu/m process are described.     

一种单片高速八位A／D转换器的设计

本文介绍了一种硅双极型单片大规模集成8位逐次近似A/D转换器X1001的电路设计,这种电路采用了自锁式电压比较器和高速低功耗ECL逻辑电路,转换时间为400ns,是单片集成逐次近似A/D转换器中速度最快的器件。