A new oxidation-resistant self-aligned TiSi2process

This paper presents a thin amorphous Si (a-Si) on Ti as an oxidation-resistant material for a self-aligned TiSi2process. It is shown that a thin a-Si over Ti film will greatly suppress the interaction between Ti and ambient gases (N2and O2) during the thermal TiSi2formation cycle in conventional N2furnance while maintaining satisfactory self-aligned property after silicidation at a temperature below 630°C.     

Solid phase crystallization of amorphous silicon on glass by thin film heater for thin film transistor (TFT) application

A new process for solid phase crystallization (SPC) of amorphous silicon (a-Si) using thin film heater is reported. With this localized Ti silicide thin film heater, we successfully crystallized 500 Å-thick a-Si in a few minutes without any thermal deformation of glass substrate. The size of crystallized silicon grain was abnormally big (30-40 μm). Polycrystalline thin film transistors (TFT) fabricated using this unique thin film heater showed better mobility than those of conventional ones by furnace annealing.     

Manufacturing enhancements for CoSi/sub 2/ self-aligned silicide at the 0.12-/spl mu/m CMOS technology node

As integrated circuit manufacturing moves to the 0.12-/spl mu/m and finer-line technologies, a more comprehensive understanding of the manufacturability of the cobalt silicide (CoSi/sub 2/) module is needed. In this paper, a detailed study of the manufacturability of cobalt self-aligned silicide (Salicide) for the 0.12-/spl mu/m and finer technology nodes is discussed. Experimental design for the CoSi/sub 2/ processing steps included cobalt (Co), titanium (Ti), and titanium nitride (TiN) depositions; the first and second rapid thermal anneals (RTA1 and RTA2) and the selective metal etch. Grain structure (by X-ray diffraction), surface roughness (by atomic force microscopy), sheet resistance, thickness uniformity and leakage current measurements were taken to characterize the SAlicide process module. The results show that by using a TiN rather than Ti capping layer: a) the CoSi/sub 2/ sheet resistance nonuniformity has been improved; b) the CoSi/sub 2/ thickness is independent of the capping layer thickness; and c) CoSi/sub 2/ to silicon interface roughness is reduced, thus reducing junction leakage currents. Anneal studies indicate the RTA1 temperature dominates the CoSi/sub 2/ grain structure and grain size with higher annealing temperatures resulting in rougher CoSi/sub 2/ surfaces and higher junction leakage currents.     

Implementation of fully self-aligned bottom-gate MOS transistor

This letter reports the implementation of a bottom-gate MOSFET, which possesses the following fully self-aligned structural features: 1) self-aligned source-drain to bottom-gate; 2) self-aligned thick source-drain and thin channel; and 3) self-aligned and mask-free lightly doped drain (LDD). The complete self-alignment is realized by combining a conventional ion implantation and a subsequent chemical-mechanical polishing (CMP) step. The process is applied to poly-Si films crystallized from an a-Si film deposited by LPCVD using a metal-induced unilateral crystallization technique, and is grain-enhanced further in a high temperature annealing step. Deep submicron fully self-aligned bottom-gate pMOS transistors with channel length less than 0.5 /spl mu/m are fabricated. The measured performance parameters include threshold voltage of -0.43 V, subthreshold swing of 113 mV/dec, effective hole mobility of 147 cm/sup 2//V-s, off-current of 0.17 pA//spl mu/m, and on-off current ratio of 7.1/spl times/10/sup 8/.     

A self-aligned, electrically separable double-gate MOS transistor technology for dynamic threshold voltage application

In this brief, a self-aligned electrically separable double-gate (SA ESDG) MOS transistor technology is proposed and demonstrated. The SA ESDG structure is implemented by defining a dummy top gate that is self-aligned to the bottom gate and then later replacing the dummy using a real top gate. The proposed process is applied to the single-grain Si film formed by recrystallizing a low-pressure chemical vapor deposition a-Si with a metal induced unilateral crystallization technique and enhancing the grain sizes in a subsequent high temperature annealing step. The ideal device structure resulting from the process is verified by scanning electron microscope imaging. The good current-voltage characteristics and the noticeable dynamic threshold voltage effects are also observed in the implemented SA ESDG device.     

反应生成的TiSi_2薄膜特性及TiSi_2/poly Si栅结构特性、TiSi_2/n~+-Si接触特性和形貌的研究

<正> 一、引言 随着集成电路的发展,集成度的提高,器件尺寸将逐渐缩小,此时RC延迟时间及接触电阻的影响将越来越显著。目前广泛应用的多晶硅栅材料在亚微米技术中已不再适用,取代它的有硅化物/多晶硅栅。由于TiSi_2的电阻率低,形成温度低,因此是人们最重视的硅化物。本文对反应生成的TiSi_2/poly Si栅结构及TiSi_2/n~+-Si的接触特性进行了系统研究,有助于     

Development of the self-aligned titanium silicide process for VLSI applications

A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Ω/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-µm gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, linewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.     

Characterization and implementation of self-alignedTiSi2 in submicrometer CMOS technology

Characterization and process implementation of a self-aligned TiSi ₂ in a submicrometer CMOS process are presented. The effects of different in situ sputter etch configurations prior to Ti deposition on silicidation is discussed. It is shown that bridging is not only first RTP time- and temperature-dependent, but also dependent on the Ti(N) overetch time. The C49 to C54-TiSi₂ phase transformation is found to be dependent on both the C49-TiSi₂ film thickness and the linewidth. A potential degradation phenomenon with high-temperature back-end processing is discussed, and the impact of TiSi₂ on specific contact resistance and circuit performance is presented. Thin film analysis was done by Auger electron spectrometry, Rutherford backscattering spectrometry with 2-MeV He⁺ , transmission electron microscopy, secondary ion mass spectrometry, X-ray diffraction, and X-ray fluorescence spectrometry. Sheet resistance measurements were carried out with a four-point probe     

Titanium silicide-silicon interface degradation during heat treatment

Thin titanium silicide films were grown on different silicon substrates by rapid thermal annealing in a nitrogen ambient. The silicide films were then annealed in a furnace at high temperature in a nitrogen ambient for various times. The effect of such heat treat-ment on the morphology of titanium silicide surface and the titanium silicide-silicon interface was studied. It is proposed that the morphological change is primarily due to the diffusion of silicon and/or dopant impurities via grain boundaries of the silicide. There is a strong correlation between the surface of the titanium silicide film and that of the titanium silicide-silicon interface.     

A low thermal budget self-aligned Ti silicide technology usinggermanium implantation for thin-film SOI MOSFET's

In this paper, a titanium salicide technology with a very low thermal annealing temperature using germanium implantation for thin film SOI MOSFET's is investigated in detail. Ti silicide formation on the amorphous silicon generated by germanium implantation is studied. Compared to the conventional Ti salicide process, the Ti silicidation temperature is significantly lowered and the silicide depth is well controlled through the pre-amorphized layer. Therefore, the potential problems of the salicide process for SOI MOSFET's such as lateral voids, dopant segregation, thermal agglomeration, and increase of resistance on narrow gate are suppressed by germanium implantation. With the Ge pre-amorphization salicide process, a very low silicide contact resistance is obtained and sub-0.25-μm SOI MOSFET's are fabricated with good device characteristics     

Titanium silicide/germanide formation on submicron features for high mobility SiGe channel field effect transistors

The formation of self-aligned Ti(Si_(1−x)Ge_(x))₂ on submicron lines is described. The silicide/germanide is formed by reacting sputtered Ti with epitaxially grown Si_(1−x)Ge_(x) of composition and thickness relevant to high mobility Si_(1−x)Ge_(x) channel field effect transistors. Ti(Si_(1−x)Ge_(x))₂ formation on narrow lines was carried out on phosphorous doped material, because of the well known difficulties of forming silicide on heavily n-doped silicon. A companion set of boron doped blanket films was also processed. The results show that the process temperature required for the minimization of silicide/germanide sheet resistance is reduced as compared to silicide formation on Si alone. However, the silicide/germanide films agglomerate with increased high temperature processing more easily than pure silicide. The thermal stability is degraded more for films with higher Ge content and is a strong function of dopant type. Silicide/germanide formation on phosphorous doped Si_(1−x)Ge_(x) layers with x = 10% have a line width dependence similar to silicide formation. Formation on phosphorous doped Si_(1−x)Ge_(x) layers with x = 27% display an inverse line width dependence, with higher overall sheet resistance. Formation of silicide/germanide on blanket films of boron doped Si_(1−x)Ge_(x) with x = 27% behaved similar to the formation of silicide on silicon.     

Effect of electron cyclotron resonance H+,Ne+, Ar+, and Xe+ plasma precleaning ontitanium silicide formation

A vacuum integrated cluster tool process incorporating electron cyclotron resonance plasma cleaning, Ti sputter deposition, and rapid thermal annealing in N₂ is used to form a TiN_x<1/TiSi_y bilayer on (100) Si where the film composition is controlled by the preclean chemistry. Chemical cleaning with nominal 10 eV H⁺ completely removes native Si oxide resulting in a hydrogen terminated surface that promotes silicidation compared to one cleaned with buffered-oxide-etching (BOE). If the native oxide is only partially reduced, viz., SiO_x<2 surface, for example by shortening the H⁺ exposure time, then silicidation is largely inhibited and a thicker nitride layer is formed. Sputter cleaning with 50 to 250 eV Ar⁺ results in a bilayer that is roughly equivalent to that formed with BOE, whereas 50 to 150 eV Xe⁺ bombardment favors nitridation. Precleaning with >150 eV Ne⁺ promotes silicidation, thereby minimizing nitride thickness. The effects of precleaning are significant as the activation energy for TiSi_y formation is reduced from 1.8 eV characteristic of a BOE cleaned surface to 1.2 eV on Si etched with 250 eV Ne⁺. Mechanistically, the silicide kinetics are shown to be inhibited by the presence of a thin amorphous layer that is formed only when cleaning Si with Ar⁺ and Xe⁺ with the effect that both knock-on oxygen atoms and implanted noble gas atoms trapped within the amorphous layer retard the requisite solid-phase epitaxial regrowth kinetics. Recrystallizing the amorphous Si surface prior to metallization appears to restore the near-normal silicide kinetics that is characteristic of Ne⁺ cleaning     

Novel submicrometer MOS devices by self-aligned nitridation of silicide

A new MOS technology is developed for submicrometer MOS devices. In this new technology, TiSi2is formed on the source and drain diffused layers by self-aligned silicidation to reduce the sheet resistance, and TiN is formed in the contact holes by self-aligned nitridation of TiSi2. This TiN can be used as an effective barrier metal between Al and Si. TiSi2is prepared by a two-step annealing method to prevent a reaction between Ti and the field oxide. PSG cap annealing after TiSi2formation provides excellent p-n junction characteristics and relatively low silicide sheet resistance of 4 ω/□ even after annealing at 950°C for 30 min. TiN is formed by direct thermal nitridation of TiSi2in N2ambient at a temperature higher than 900°C after contact hole formation. The formation of TiN is confirmed by AES, ESCA, and X-ray diffraction analysis. The TiN formed by direct thermal nitridation is found to prevent Al diffusion into the Si substrate even for post-metallization annealing at 500°C for 1 h. The characteristics of devices fabricated by this new technology also are determined.     

Two gates are better than one [double-gate MOSFET process]

A planar self-aligned double-gate MOSFET process has been implemented where a unique sidewall source/drain structure (S/D) permits self-aligned patterning of the back-gate layer after the S/D structure is in place. This allows coupling the silicon thickness control inherent in a planar, unpatterned layer with VLSI self-alignment techniques and also gives independently controlled front and back gates. The demanding structure led to process innovations primarily in front-end CMP, where planarity within 5 nm was achieved on an 8-in diameter wafer as well as in silicided silicon source/drain sidewalls, with minimal encroachment of the silicide. Double-gate FET (DGFET) operation is demonstrated, with good transport at both interfaces. Dense circuit layouts are achieved with multifinger devices, and logic inverters with back-gate-controlled load current as well as NOR logic using the two gates of a single transistor as inputs are demonstrated.     

Reverse short-channel effects on threshold voltage in submicrometersalicide devices

A reverse short-channel effect on threshold voltage caused by the self-aligned silicide process in submicrometer MOSFETs is reported. A physical model of lateral channel dopant redistribution due to the salicide process is proposed. The injection of vacancies and lattice strain during TiSi₂ formation causes defect-enhanced boron diffusion which results in a nonuniform lateral channel dopant redistribution and hence a threshold increase in short-channel devices. In addition to the small gate edge birds beak and the nonuniform oxidation-enhanced diffusion (OED) redistribution of channel dopant due to the polysilicon gate reoxidation, the self-aligned Ti silicide process can be major cause of the observed reverse short-channel effect in submicrometer MOSFET devices     

TiSi_2/N~+-poly Si/SiO_2/Si MOS结构的电学特性

<正> 一、 引言 随着半导体器件向微小型化发展,电路的速度与栅极和互连材料密切相关。目前应用较广的多晶硅栅技术具有自对准形成源漏区、低阈值电压、高温热稳定性好等优点。但多晶硅的电阻率较高,严重影响了电路速度的提高。在多晶硅上生长一层具有高电导率的TiSi_2薄膜取代多晶硅作为栅电极,可以有效地克服多晶硅电阻率高的缺点,提高电路速度。 本实验采用NH_3等离子体增强热退火,使Ti/poly Si固相反应形成TiSi_2,同时表面形成一层很薄的TiN。TiN被证明是一层良好的扩散阻挡层。通过对TiN/TiSi_2复合薄膜的薄层电阻测试和MOS高频C—V测试,证明这种方法是可行的。     

Fully self-aligned tri-layer a-Si:H thin-film transistors withdeposited doped contact layer

We demonstrate a new self-aligned TFT process for hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs). Two backside exposure photolithography steps are used to fabricate fully self-aligned tri-layer TFTs with deposited n⁺ contacts. Since no critical data alignment is required, this simple process is well suited to fabrication of short channel TFTs. We have fabricated fully self-aligned tri-layer a-Si:H TFTs with excellent device performance, and contact overlaps <1 μm. For a 20-μm channel length TFT with an a-Si:H thickness of 13 nm, the linear region (V_DS=0.1 V) and saturation region (V_DS=25 V) extrinsic mobility values are both 1.2 cm²/V-s, the off currents are <1 pA, and the on/off current ratio is >10⁷     

Co/a-GeSi/Ti/Si多层薄膜固相反应外延生长CoSi_2薄膜

研究了在 Co/Ti/Si结构中加入非晶 Ge Si层对 Co Si2 /Si异质固相外延的影响 ,用离子束溅射方法在Si衬底上制备 Co/Ge Si/Ti/Si结构多层薄膜 ,通过快速热退火使多层薄膜发生固相反应。采用四探针电阻仪、AES、XRD、RBS等方法进行测试。实验表明 ,利用 Co/Ge Si/Ti/Si固相反应形成的 Co Si2 薄膜具有良好的外延特性和电学特性 ,Ti中间层和非晶 Ge Si中间层具有促进和改善 Co Si2 外延质量 ,减少衬底耗硅量的作用。Ge原子的存在能够改善外延 Co Si2 薄膜的晶格失配率     

VLSI中钛硅化物肖特基接触特性与退火条件

基于 Ti Si2 低电阻率的优点 ,采用 Ti制作肖特基二极管。在 VL SI工艺中实现同时完成钛硅化物欧姆接触和肖特基势垒二极管 (SBD)的制作。文中用 AES等技术研究不同退火工艺形成的 Ti/ Si界面形态和结构 ,寻找完善的工艺设计和退火条件。此外还测量 Al/ Ti N/ Ti/ Si结构的金属硅化物 SBD的有关特性。通过工艺实验确定 VL SI中的钛硅化物最佳的制作工艺条件     

A novel process to form cobalt silicided p+ poly-Sigates by BF2+ implantation into bilayeredCoSi/a-Si films and subsequent anneal

A novel process that implants BF₂⁺ ions into thin bilayered CoSi/a-Si films has been shown to form cobalt silicided p ⁺ poly-Si gates with excellent gate oxide integrity and very small flatband shift. The effects of not only using the CoSi layer as an implantation barrier but also keeping the a-Si underlayer during the initial silicide formation both significantly suppress the boron penetration through thin gate oxide