A monolithic 3.1-4.8 GHz MB-OFDM UWB transceiver in 0.18-μm CMOS

A monolithic RF transceiver for an MB-OFDM UWB system in 3.1-4.8 GHz is presented.The transceiver adopts direct-conversion architecture and integrates all building blocks including a gain controllable wideband LNA,a I/Q merged quadrature mixer,a fifth-order Gm-C bi-quad Chebyshev LPF/VGA,a fast-settling frequency synthesizer with a poly-phase filter,a linear broadband up-conversion quadrature modulator,an active D2S converter and a variablegain power amplifier.The ESD protected transceiver is fabricated in Jazz Semiconductor's 0.18-μm RF CMOS with an area of 6.1 mm2 and draws a total current of 221 mA from 1.8-V supply.The receiver achieves a maximum voltage gain of 68 dB with a control range of 42 dB in 6 dB/Step,noise figures of 5.5-8.8 dB for three sub-bands,and an inband/out-band IIP3 better than-4 dBm/+9 dBm.The transmitter achieves an output power ranging from-10.7 to-3dBm with gain control,an output P1dB better than-7.7 dBm,a sideband rejection about 32.4 dBc,and LO suppression of 31.1 dBc.The hopping time among sub-bands is less than 2.05 ns.     

0.18μm CMOS 3.1-10.6GHz超宽带低噪声放大器设计

介绍了一种基于0.18μm CMOS工艺、适用于超宽带无线通信系统接收前端的低噪声放大器.在3.1～10.6GHz的频带范围内对它仿真获得如下结果:最高增益12dB;增益波动小于2dB;输入端口反射系数S11小于-10dB;输出端口反射系数S22小于-15dB;噪声系数NF小于4.6dB.采用1.5V电源供电,功耗为10.5mW.与近期公开发表的超宽带低噪声放大器仿真结果相比较,本电路结构具有工作带宽大、功耗低、输入匹配电路简单的优点.     

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single （D2S） converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18μm RF CMOS process with an area of 1.74 mm^2 and only consumes 32 mA current （at 1.8 V） including the test associated parts.     

A 5-GHz programmable frequency divider in 0.18-μm CMOS technology

正A 5-GHz CMOS programmable frequency divider whose modulus can be varied from 2403 to 2480 for 2.4-GHz ZigBee applications is presented.The divider based on a dual-modulus prescaler(DMP) and pulse-swallow counter is designed to reduce power consumption and chip area.Implemented in the 0.18-μm mixed-signal CMOS process,the divider operates over a wide range of 1-7.4 GHz with an input signal of 7.5 dBm;the programmable divider output phase noise is -125.3 dBc/Hz at an offset of 100 kHz.The core circuit without test buffer consumes 4.3 mA current from a 1.8 V power supply and occupies a chip area of approximately 0.015 mm~2.The experimental results indicate that the programmable divider works well for its application in frequency synthesizers.     

基于0.18μm CMOS工艺的3.1~10.6GHz超宽带LNA设计

本文基于特许0.18μm CMOS工艺,提出了一种新型的低复杂3.1~10.6GHz超宽带LNA电路,它由两级简单的放大器通过级间电感连接构成。第一级放大器使用电阻电流复用结构和双电感退化技术来达到宽带输入匹配和低噪声性能,第二级放大器使用带电感峰值技术的共源级放大器来同时达到高平坦增益和好的宽带性能。测试结果表明,在3.1~10.6GHz频段内,提出的超宽带LNA的最大功率增益为15.6dB,S12为-45dB,输入输出隔离度小于-10dB,噪声系数NF为2.8~4.7dB,在6GHz时的输入三阶交调点IIP3为-7.1dBm。芯片在1.5V电源电压下,消耗的功率为14.1mW,芯片总面积为0.8mm0.9mm。     

低功耗2.4GHz 0.18μm CMOS全集成低噪声放大器设计

我们利用0.18μm CM O S工艺设计了低噪声放大器。所有电感采用片上螺旋电感,全集成在单个芯片上,并实现片内50Ω匹配。本次电路设计分析采用ADS仿真软件,电源电压1V,工作电流8mA,增益为15.4dB,噪声系数2.7dB,线性度指标IIP 3为-0.6dB。结论是CM O S工艺在工艺和模型方面的改进,使得CM O S RF电路设计更为精确,可集成度更高。     

基于O.18μm工艺CMOS超宽带低噪声放大器设计

超宽带技术是一种无载波通信技术,利用纳秒至微微秒级的非正弦波窄脉冲传输数据,相对于窄带技术,使用超宽带技术进行无线传输具有很多优势.文章介绍了一种基于0.18 μmCMOS工艺、适用于超宽带无线通信系统接收前端的低噪声放大器.结合计算机辅助设计,可以看出经过优化后其S11和S22在3.1GHz～10.6GHz范围内都小于-10dB,而正向增益S21根据-3dB带宽计算可得其符合要求的频率范围达到2.4GHz～10.4GHz,噪声系数NF在2.8GHz左右达到最低值1dB,平均在2.5dB,可以认为是比较低的.整体而言电路符合UWB技术所运用范围.     

基于O.18μm工艺CMOS超宽带低噪声放大器设计

超宽带技术是一种无载波通信技术,利用纳秒至微微秒级的非正弦波窄脉冲传输数据,相对于窄带技术,使用超宽带技术进行无线传输具有很多优势.文章介绍了一种基于0.18 μmCMOS工艺、适用于超宽带无线通信系统接收前端的低噪声放大器.结合计算机辅助设计,可以看出经过优化后其S11和S22在3.1GHz～10.6GHz范围内都小...     

5.2GHz 0.18μm CMOS射频低噪声放大器的设计

采用TSMC 0.18μm CMOS工艺,设计应用于IEEE 802.11a的无线局域网络的低噪声放大器（LNA）。整个电路采用1.8V单电源供电,输入输出匹配良好。用ADS模拟软件对电路进行分析优化,结果表明：在中心频率5.2GHz处,噪声系数为2.51dB,功率增益为17.373dB。     

A 0.18μm CMOS low noise amplifier using a current reuse technique for 3.1-10.6 GHz UWB receivers

A new,low complexity,ultra-wideband 3.1-10.6 GHz low noise amplifier(LNA),designed in a chartered 0.18μm RFCMOS technology,is presented.The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected.The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure.A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide -3 dB bandwidth of the overall amplifier simultaneously.The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB,and a high reverse isolation of—45 dB,and good input/output return losses are better than -10 dB in the frequency range of 3.1-10.6 GHz.An excellent noise figure(NF) of 2.8-4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V.An input-referred third-order intercept point(IIP3) is -7.1 dBm at 6 GHz.The chip area,including testing pads,is only 0.8×0.9 mm2.     

A 0.18 μm CMOS 3-5 GHz broadband flat gain low noise amplifier

A 3-5 GHz broadband flat gain differential low noise amplifier(LNA) is designed for the impulse radio ultra-wideband(IR-UWB) system.The gain-flatten technique is adopted in this UWB LNA.Serial and shunt peaking techniques are used to achieve broadband input matching and large gain-bandwidth product(GBW).Feedback networks are introduced to further extend the bandwidth and diminish the gain fluctuations.The prototype is fabricated in the SMIC 0.18μm RF CMOS process.Measurement results show a 3-dB gain band...     

A 3.1–4.8-GHz direct-conversion mixer in 0.35-μm CMOS for mode-1 MB-OFDM UWB systems

This paper presents a CMOS direct-conversion mixer for TFI-OFDM receiver of UWB group #1 bands, providing a 110 Mbits/s rate and optimized for 0.35-μm technology. The proposed mixer uses the current-bleeding technique in both the driver and switching stages with wideband impedance matching, consisting of a bandpass filter embedding the RF stage. The 1/f noise of the switching pairs dominates the noise performance for down-converted frequencies below 1 MHz. Above 1 MHz, the insertion of an inductor at the tail of switching pairs reduces uniformly the noise figure by 2.2 dB. Over 3.1–4.8 GHz, the circuit drawing 6 mA from 3-V supply, shows a conversion gain of 14.0 ± 1.0 dB, IIP3 of 0 ± 2 dBm, double-sideband noise figure of 4.5–4.8 dB, and port-to-port isolation above 61.0 dB. The mixer output bandwidth is 460 MHz. The RF power and LO amplitude marginally affect these performances within, respectively, the FCC-power limits and 2.5–3.4 V range.     

5 GHz 0.18-μm CMOS 可编程分频器

提出了一种2.4GHz ZigBee 应用的可编程分频器,其分频模值在2403-2480之间变化。该分频器基于双模分频器和吞咽计数器架构,功耗和面积得到了有效降低。芯片采用0.18-μm CMOS混合信号工艺实现,当输入信号达到7.5dBm时,分频器可正常工作的频率范围覆盖1-7.4 GHz,在100KHz频偏处的输出相位噪声为-125.3dBc/Hz。分频器核心电路消耗电流4.3mA（1.8V电源电压）,核心面积0.015mm2。测试结果表明该可编程分频器能很好的应用在所需的频率综合器中.     

应用于5GHz 0.18μm CMOS差分低噪声放大器的差分平面螺旋电感设计

针对射频应用的5GHz 0.18 μm CMOS差分低噪声放大器,本文提出了一种差分平面螺旋电感的设计方法.通过对提出的电感模型进行参数计算和分析,可以实现差分电感的高准确度物理设计.与此同时,本文还提出几种对于该设计的优化方法:Q值迭代优化、耦合系数近似等.最后,通过Momentum工具进行物理建模和电磁场仿真.测试结果表明应用该设计的低噪声放大器的性能符合指标要求.     

用于802.11a系统的5.8GHz 0.18μm CMOS全集成低噪声放大器设计

通过对输入匹配、噪声和线性度的分析,给出了改进低噪声放大器综合性能的方法.利用软件对电路进行噪声优化,设计出了一个0.18μm CMOS工艺的5.8GHz全集成低噪声放大器.采用工艺厂家提供的电感测试数据进行参数提取,得到精准的电感模型并用于电路仿真.设计结果是整个电路功耗13mW,功率增益为14dBm,噪声系数为2.05dB,线性度指标IIP3为-1dBm.     

A 2.5-Gb/s fully-integrated,low-power clock and recovery circuit in 0.18-μm CMOS

Based on the devised system-level design methodology,a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery(CDR) circuit has been designed and fabricated in SMIC's 0.18-μm CMOS technology.The Pottb(a|¨)cker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted,where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic.The CDR has an active area of 340×440μm~2,and consumes a power of only about 60 mW from a 1...     

A 3.1-4.8 GHz transmitter with a high frequency divider in 0.18 μm CMOS for OFDM-UWB

A fully integrated low power RF transmitter for a WiMedia 3.1-4.8 GHz multiband orthogonal frequency division multiplexing ultra-wideband system is presented. With a separate transconductance stage, the quadrature up-conversion modulator achieves high linearity with low supply voltage. The co-design of different resonant frequencies of the modulator and the differential to single (D2S) converter ensures in-band gain flatness. By means of a series inductor peaking technique, the D2S converter obtains 9 dB more gain without extra power consumption. A divided-by-2 divider is used for carrier signal generation. The measurement results show an output power between -10.7 and -3.1 dBm with 7.6 dB control range, an OIP3 up to 12 dBm, a sideband rejection of 35 dBc and a carrier rejection of 30 dBc. The ESD protected chip is fabricated in the Jazz 0.18/zm RF CMOS process with an area of 1.74 mm~2 and only consumes 32 mA current (at 1.8 V) including the test associated parts.     

0.18μm RF CMOS 3-5 GHz TH-UWB 通信射频发信机

本文给出一种3-5 GHz射频TH-UWB发信机的设计。该发信机由一个4GHz的振荡器,一个带衰减控制的MOS开关和一个输出匹配电路构成。由低速TH-PPM信号控制,该发信机输出中心频率为4GHz的TH-UWB信号,并能直接通过传输线驱动天线。采用0.18μm RF CMOS工艺实现,在1.8V电源下,输出信号峰值幅度在50Ω负载上为65mV。电路输出端口回波损耗S11小于-10dB。芯片占用面积为0.7 mm0.8 mm,功耗为12.3mW。