SiNx/SiOxNy叠层结构防潮能力的研究

研究了等离子体增强化学气相沉积(PECVD)工艺参数对SiN_x及SiO_xN_y防潮能力的影响,并测试了SiN_x/SiO_xN_y叠层薄膜的水汽渗透速率(WVTR)。实验结果表明:单层SiN_x薄膜和SiO_xN_y薄膜都存在临界厚度,当膜厚大于临界值时,继续增大厚度不会明显改善薄膜的WVTR。当沉积温度从50℃提高到250℃,SiN_x薄膜的WVTR从0.031g/(m²·day)降至0.010g/(m²·day)。SiO_xN_y沉积时,增大N₂O通入量对薄膜的WVTR影响不明显,但可以有效改善薄膜的弯曲性能。最后,4个SiN_x/SiO_xN_y叠层膜的WVTR下降到了4.4×10-4g/(m²·day)。叠层膜防潮能力的显著提升归因于叠层结构可以有效解耦层与层之间的缺陷,延长水汽渗透路径。     

具有宽带输入匹配性能和高线性度的31.7 GHz CMOS基毫米波低噪声放大器

本文基于CMOS工艺设计了一种工作于31.7GHz具有良好输入匹配性能和线性性能的低噪声放大器。宽带输入匹配性能的实现基于一种简单的LC网络的组合,使得S11的曲线在-10dB以下出现1个以上的凹谷。为了获得输入阻抗Zin与负载的关系,文中分析了匹配电路的原理,确定了影响Zin的关键因素。文中着重对Zin和负载配置的关系进行了深入探讨,这在以往并未引起太多关注。此外,本文使用级联矩阵建立了输入级噪声模型而非使用传统的噪声理论,这样一来,Zin和NF便可以用统一的公式进行计算。线性分析在本文也有所涉及。最后,本文设计了一个低噪声放大器加以验证。芯片测试结果表明本文设计的低噪声放大器具有9.7dB的功率增益,S11在频率高于29GHz的仪器量程范围内全部在-10dB以下。测得的输入1dB压缩点和3阶交调点分别为-7.8dB和5.8dB。低噪声放大器的制造采用90 nm射频CMOS工艺,包括焊盘在内整个芯片的尺寸为755 um x 670 um。电路在1.3 V电压下的耗散功率为24 mW。     

单片高线性度低噪声宽带解调器设计

设计了一款单片高线性度低噪声宽带解调器.采用共基极输入吉尔伯特单元混频器结构实现宽带和高线性度特性,内部集成螺旋线圈变压器,实现单端向双端转换.电路采用0.18μmSiGe BiCMOS工艺技术,在2～4 GHz频段内实现宽带匹配,反射系数小于-10dB,单边带噪声系数小于14dB,输入1dB压缩点大于10dBm,相位误差小于1.5°,幅度误差小于0.5 dB.     

基于低噪声和高线性度的差分CMOS LNA的设计

基于TSMC 0.18μm CMOS工艺,设计了一种低噪声、高线性度的差分CMOS低噪声放大器。与传统的共源共栅结构相比,该电路在共源晶体管的栅源极并入一个电容以降低共源极的噪声;并在共栅极上引入一对交叉耦合电容和电感,以消除共栅极的噪声并提高电路的线性度。仿真结果表明,在2.4GHz的工作频率下,该电路的噪声系数仅有1.29 dB,该电路能够提供17dB的正向增益,良好的输入输出匹配,该放大器的输入三阶交调点为0.76dBm,功耗小于10mW。     

一种L频段高线性度低噪声放大器的设计

对低噪声放大器线性度提高的方法进行分析。基于导数交叠法,使两个晶体管偏置在不同区域,并利用这两个晶体管源端产生的相位差,抵消了3阶项电流。采用TSMC 90 nm CMOS 工艺,实现了一款L频段高线性度全差分低噪声放大器,测试得到输出3阶交调点达30.6 dBm,增益为14.54 dB,噪声系数为1.63 dB,功耗为45 mA@3.3 V。     

用于相控阵雷达的高线性度低噪声放大器

基于IBM 0.18 μm SiGe BiCMOS工艺,提出了一种用于Ku波段相控阵雷达的高线性度低噪声放大器。该放大器采用2级级联结构,第1级优化可获得最小的噪声性能,第2级优化可提高电路的增益和线性输出功率。为了提高线性度,第2级采用了具有线性补偿功能的线性化偏置电路。仿真结果表明,在中心频率为16.5 GHz,带宽为2 GHz的频带范围内,噪声系数小于3.9 dB,其最小值为3.22 dB,功率增益大于23.5 dB,输出1-dB压缩点在中心频率处大于6.5 dBm。在3.3 V电源电压下,静态功耗为66 mW,芯片面积为(1 245×580) μm²。     

具有高击穿电压的AlN背势垒AlGaN/GaN/AlN HEMT材料

采用金属有机化学气相沉积(MOCVD)技术在4英寸(1英寸=2.54 cm)蓝宝石衬底上制备了1.2μm厚的AlN背势垒的AlGaN/GaN/AlN双异质结高电子迁移率晶体管(HEMT)材料,其AlGaN势垒层表面粗糙度(RMS)、二维电子气(2DEG)迁移率以及HEMT材料的弯曲度都较为接近于常规的高阻GaN背势垒结构的HEMT材料。由于AlN晶格常数较小,具有AlN背势垒的HEMT材料受到了更大的压应力。通过对比分析两种HEMT材料所制备的器件发现,受益于AlN背势垒层更高的禁带宽度和临界电场,由AlN背势垒HEMT材料所制备的器件三端关态击穿电压为常规高阻GaN背势垒HEMT器件的1.5倍,缓冲层漏电流则较常规高阻GaN背势垒HEMT器件低2～3个数量级。     

一种应用于GPS接收机的高线性度SiGe HBT低噪声放大器

A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of ＋7.8 dBm and an input third-order intercept point of ＋1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.     

一种新型的Q值与L值可相互独立调谐的低噪声有源电感

提出了一种新型的品质因数(Q)与电感值(L)可相互独立调谐的低噪声有源电感。该电感主要由双回转器、调制支路、可调反馈电阻、跨导增强支路和噪声抑制单元构成。其中,双回转器是由第一回转回路和第二回转回路并联而成,获得了大电感值;调制支路不仅能减小等效并联电阻,提高Q值,还可实现对电感值的大范围调谐;可调反馈电阻不仅能增大Q值,还能实现对Q值的独立调节,也能补偿因调谐L值引起的Q值的变化;跨导增强支路和噪声抑制单元分别降低了第一回转回路和第二回转回路的噪声,从而降低有源电感的整体噪声。最终,通过上述电路模块的紧密配合及所配置的三个外部调控端电压的深度协作,实现了Q值与L值可相互独立调谐以及低噪声的优异特性。仿真结果表明,该有源电感在3.8 GHz频率下,Q峰值可从674调节到5 083,调谐率为153.2%,而L值变化率仅为0.3%;在3.65 GHz下,L值可由6.1 nH调节到15.5 nH,调谐率高达87%,而与之对应的Q值的变化率仅为3.7%;在2~6 GHz范围内,有源电感的最大和最小输入噪声分别为5.29 nV/Hz和1.75 nV/Hz。     

具有低电压、低“迟滞效应”的C60薄膜晶体管

以C60为激活层,同时以聚合物/高K氧化物双绝缘层结构研制了N型有机场效应晶体管。结果表明,采用这种双层结构的绝缘层能够很好的将Ta2O5和PMMA的优点结合在一起,即既利用了Ta2O5的高介电常数又利用了PMMA与半导体层良好的界面接触特性。与采用单一Ta2O5或这PMMA绝缘层的器件相比,这种具有双层结构的器件性能大幅提升。最终研制了能够在10V低电压下正常工作的C60晶体管,其场效应迁移率、阈值电压和开关电流比分别为0.26 cm2/Vs, 3.2V和8.31×104。同时,利用修饰绝缘层PMMA的疏水性大大降低了这种具有双层结构的N型有机晶体管的“迟滞效应”,从而让器件工作时有较好的稳定性。     

一款具有低相噪，宽调频范围和高线性度的压控晶体振荡器芯片

本文实现了一款带有LVCMOS和LVPECL输出的压控晶体振荡器芯片(VCXO-IC),具有低相噪,宽调节范围和高线性度等特点。通过采用一种新颖的差分倍频Colpitts振荡器来得到低噪声的2倍频输出;宽调节范围和高线性度通过采用MOS变容管阵列来实现。测试结果表明,当采用AT切40MHz晶体时,该芯片在1kHz处的相位噪声达到-135dBc/Hz,频率调节范围达到 /- 130ppm,且线性度小于5%。该芯片采用Chartered 0.35μm CMOS 2P3M工艺,芯片总面积为2.4 mm2。     

A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2/HfO2 gate stack nMOSFETs

Charge pumping and low frequency noise measurements for depth profiling have been studied systematically using a set of gate stacks with various combinations of IL and HfO₂ thicknesses. The distribution of generated traps after HCI and PBTI stress was also investigated. The drain-current power spectral density made up all of the traps of IL in 0 < z < T_IL and the traps of HfO₂ in T_IL < z < T_HK. The traps near the Si/SiO₂ interface dominated the 1/f noise at higher frequencies, which is common in SiO₂ dielectrics. For the HfO₂/SiO₂ gate stack, however, the magnitude of the 1/f noise did not significantly change after HCI and PBTI because of more traps in the bulk HfO₂ film than at the bottom of the interface.     

低导通电阻和栅漏电的高性能InAlN/GaN HEMT

本文制备了100nm栅长的InAlN/GaN HEMT。通过氧处理和优化欧姆接触获得了高性能的InAlN/GaN HEMT。所制备的器件在栅压偏置为2V时,漏端输出电流密度达到2.18A/mm。器件的导通电阻为1.49Ω*mm。与常规器件相比,器件的栅漏电下降了两个数量级。器件也获得良好的射频特性,电流截止频率和最高震荡频率分别为81GHz和138GHz。根据现有的报道,这是国内较早报道GaN基HEMT电流密度超过2A/mm。     

Comparative study of AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with Al2O3 and HfO2 gate oxide

AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with Al₂O₃ gate oxide which was deposited by atomic layer deposition (ALD) were fabricated and their performance was then compared with that of AlGaN/GaN MOSHFETs with HfO₂ gate oxide. The capacitance (C)-voltage (V) curve of the Al₂O₃/GaN MOS diodes showed a lower hysteresis and lower interface state density than the C-V curve of the HfO₂/GaN diodes, indicating better quality of the Al₂O₃/GaN interface. The saturation of drain current in the I_D-V_GS relation of the Al₂O₃ AlGaN/GaN MOSHFETs was not as pronounced as that of the HfO₂ AlGaN/GaN MOSHFETs. The gate leakage current of the Al₂O₃ MOSHFET was five to eight orders of magnitude smaller than that of the HfO₂ MOSHFETs.     

Integration of HfxTayN metal gate with SiO2 and HfOxNy gate dielectrics for MOS device applications

Interaction of Hf_xTa_yN metal gate with SiO₂ and HfO_xN_y gate dielectrics has been extensively studied. Metal-oxide-semiconductor (MOS) device formed with SiO₂ gate dielectric and Hf_xTa_yN metal gate shows satisfactory thermal stability. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) analysis results show that the diffusion depths of Hf and Ta are less significant in SiO₂ gate dielectric than that in HfO_xN_y. Compared to HfO_xN_y gate dielectric, SiO₂ shows better electrical properties, such as leakage current, hysteresis, interface trap density and stress-induced flat-band voltage shift. With an increase in post metallization annealing (PMA) temperature, the electrical characteristics of the MOS device with SiO₂ gate dielectric remain almost unchanged, indicating its superior thermal and electrical stability.     

微波法制备高活性H1-xSr2Nb3-xMoxO10 (x = 0, 0.05, 0.1, 0.15 and 0.2) 光催化剂

通过微波辅助法制备出高活性H1-xSr2Nb3-xMoxO10光催化材料,制备过程和时间均被大大缩短。采用X射线粉末衍射（XRD）、扫描电镜（SEM）、紫外-可见吸收吸收光谱（UV-Vis DRS）等表征其材料性能。考察了催化材料在40W汞灯辐照下催化降解甲基橙的催化性能。实验结果表明,MoO3的掺入量为15%（摩尔分数）时,材料的光催化性能最优。     

In0.53Ga0.47As表面氮化和硫钝化对其Al/Al2O3/InGaAs MOS电容特性的影响

本文通过对比频散特性和滞回特性,计算界面态密度D_it和有效边界缺陷密度ΔN_bt,分析界面缺陷和漏电流等方法,系统的研究了In_0.53Ga_0.47As表面氮化和硫钝化对其Al/Al₂O₃/InGaAs结构MOS电容特性的影响。实验结果表明,这两种方法都能够在InGaAs表明形成一层界面钝化层。相比较于未处理的样品,经过氮气等离子体处理的样品表现出较好的界面特性,得到了最小的积累区频散、滞回电压,以及良好的I-V性能。经过(NH₄)₂S_x处理的样品则获得了最小的平带电压区频散以及最低的界面态密度Dit=2.6E11cm_-2eV_-1.     

低温退火对具有HfO2/TiN栅结构的MOS电容电学性能的影响

The effects of low temperature annealing,such as post high-k dielectric deposition annealing(PDA),post metal annealing(PMA)and forming gas annealing(FGA)on the electrical characteristics of a metal–oxide–semiconductor(MOS)capacitor with a TiN metal gate and a HfO2dielectric are systematically investigated.It can be found that the low temperature annealing can improve the capacitance–voltage hysteresis performance significantly at the cost of increasing gate leakage current.Moreover,FGA could effectively decrease the interfacial state density and oxygen vacancy density,and PDA could make the flat band positively shift which is suitable for P-type MOSs.     

Interface optimization using diindenoperylene for C60 thin film transistors with high electron mobility and stability

C₆₀-based organic thin film transistors (OTFTs) with high electron mobility and high operational stability are achieved with (1 1 1) oriented C₆₀ films grown by using template effects of diindenoperylene (DIP) under layer on the SiO₂ gate insulator. The electron mobility of the C₆₀ transistor is significantly increased from 0.21 cm² V⁻¹ s⁻¹ to 2.92 cm² V⁻¹ s⁻¹ by inserting the template-DIP layer. Moreover much higher operational stability is also observed for the DIP-template C₆₀ OTFTs. A grazing incidence X-ray diffraction and ultrahigh-sensitivity photoelectron spectroscopy measurements indicate that the improved electron mobility and stability arise from the decreased density of trap states in the C₆₀ film due to increased (1 1 1) orientation of C₆₀-grains and their crystallinity on the DIP template.