A fully integrated CMOS DCS-1800 frequency synthesizer

A prototype frequency synthesizer for the DCS-1800 system has been integrated in a standard 0.4 μm CMOS process without any external components. A completely monolithic design has been made feasible by using an optimized hollow-coil inductor low-phase-noise voltage-controlled oscillator (VCO). The frequency divider is an eight-modulus phase-switching prescaler that achieves the same speed as asynchronous dividers. The die area was minimized by using a dual-path active loop filter. An indirect linearization technique was implemented for the VCO gain. The resulting architecture is a fourth-order, type-2 charge-pump phase-locked loop. The measured settling time is 300 μs, and the phase noise is up to -123 dBc/Hz at 600 kHz and -138 dBc/Hz at 3 MHz offset     

Design of fully integrated programmable PLL frequency synthesizers for microprocessor clocking at 1–1500 MHz

This paper is concerned with the design of fully integrated programmable PLL frequency synthesizers for microprocessor clocking at 1–1500 MHz. The focus is on the circuit configuration and performance parameters of the basic analog units of the PLL: the stabilized bias unit, phase-frequency detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). The data examined are obtained by measurements on ICs fabricated by a 0.25-or 0.18-μm established CMOS technology. The circuit configurations are presented of VCOs that are tunable up to 1–1.3 GHz or up to over 2 GHz; they are designed to be implemented in a 0.25-or 0.18-μm technology, respectively. Also addressed is the design of the digital section of PLL synthesizers with a tuning range extending from 1 to over 1000 MHz. The PLL frequency and step responses, current consumption, and jitter performance are presented and investigated.     

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer

A 2 V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a standard 0.5 /spl mu/m digital CMOS process for wireless communication. The voltage-controlled oscillator (VCO) required for the low-frequency loop is designed using a ring-type VCO and achieves a tuning range of 89% from 356 to 931 MHz and a phase noise of -109.2 dBc/Hz at 600 kHz offset from 856 MHz. With an active chip area of 2000/spl times/1000 /spl mu/m/sup 2/ and at a 2 V supply voltage, the whole synthesizer achieves a tuning range from 1.8492 to 1.8698 GHz in 200 kHz steps with a measured phase noise of -112 dBc/Hz at 600 kHz offset from 1.86 GHz. The measured settling time is 128 /spl mu/s and the total power consumption is 95 mW.     

A high-frequency CMOS multi-modulus divider for PLL frequency synthesizers

A high-frequency divide-by-256–271 programmable divider is presented with the improved timing of the multi-modulus divider structure and the high-speed embedded flip-flops. The D flip-flop and logic flip-flop are proposed by using a fast pipeline technique, which contains single-phase, edge-triggered, ratioed, and high-speed technologies. The circuits achieve high-speed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements. By the way, it is suitable for realizing high-speed synchronous counters. The programmable divider using proposed flip-flops is measured in 0.25-μm CMOS technology with the operating clock frequency reaching as high as 4.7 GHz under the supply voltage of 3V.     

一个全集成的CMOS脉冲超宽带发射机

本文给出了一个低功耗、全集成的CMOS脉冲式超宽带发射机电路的设计和流片测试结果,其集成了亚纳秒脉冲发生器、脉冲位置调制(PPM)器和天线驱动电路等,可支持多种调制方式并产生最高达1Gp/s的超宽带脉冲序列.设计采用数字驱动信号上升沿触发的新型反馈结构脉冲发生器,可产生稳定的脉冲信号.通过可调的脉冲宽度和PPM调制步长,设计提供了工艺参数和温度变化的补偿手段.     

Phase-domain fractional-N frequency synthesizers

The concept of phase-domain fractional-N frequency synthesis is presented. Synthesizers using this architecture can achieve fast frequency switching without limiting the minimum channel spacing. In this architecture, a numerical phase comparator is used in conjunction with weighting coefficients, as a linear weighted phase-frequency detector. The synthesizer output spur level is determined by two factors. Namely, the delay of the numerical phase comparator, and the accuracy of the digital-to-analog convertor (DAC) used to convert the phase error to the analog domain. A novel second-order timing-error cancelation scheme is proposed to eliminate the effect of the phase comparator delays. Using this technique together with a 10-bit accuracy DAC, a maximum spur level of less than -65 dBc is simulated for a 900-MHz synthesizer. The settling time of the simulated synthesizer is less than 7 /spl mu/s, and is independent of the channel spacing. The details of the synthesizer architecture, design considerations, and system-level simulations are presented. Implementation issues including the DAC accuracy and timing-error effects are discussed extensively throughout the text.     

A low-power and high-gain fully integrated CMOS LNA

In this paper, we present the design of a fully integrated CMOS low noise amplifier (LNA) with on-chip spiral inductors in 0.18 μm CMOS technology for 2.4 GHz frequency range. Using cascode configuration, lower power consumption with higher voltage and power gain are achieved. In this configuration, we managed to have a good trade off among low noise, high gain, and stability. Using common-gate (CG) configuration, we reduced the parasitic effects of C_gd and therefore alleviated the stability and linearity of the amplifier. This configuration provides more reverse isolation that is also important in LNA design. The LNA presented here offers a good noise performance. Complete simulation analysis of the circuit results in center frequency of 2.4 GHz, with 37.6 dB voltage gain, 2.3 dB noise figure (NF), 50 Ω input impedance, 450 MHz 3 dB power bandwidth, 11.2 dB power gain (S₂₁), high reverse isolation (S₁₂)<−60 dB, while dissipating 2.7 mW at 1.8 V power supply.     

CMOS compatible fully integrated Mach-Zehnder interferometer in SOItechnology

We present a fully integrated Mach-Zehnder interferometer in silicon-on-insulator technology. Modulation of the index of refraction is achieved through the plasma dispersion effect resulting in a bandwidth in the 10 MHz range. A particular and innovative design makes this device completely compatible with CMOS technology allowing electronic functions to be integrated on the same substrate. Measurement results, limitations due to thermooptic effect and absorption related to charge injection together with further improvements are discussed     

Design method for fully integrated CMOS RF LNA

An efficient method for fully integrated RF CMOS LNA design is presented. A particular input matching topology enables inductor values to be selected in order to be integrated fully and to minimise the input losses. Moreover, an active device sizing method is used to achieve a 50 /spl Omega/ input impedance with a low noise factor. Simulations show a 3.0 dB noise figure at 2.45 GHz for a power consumption of 10 mW in a 0.28 /spl mu/m RF CMOS process.     

A fully integrated CMOS PM radio receiver for wristwatchcalibration

In this paper, a fully integrated phase modulation radio receiver ASIC is presented. The ASIC is a mixed analog and digital circuit, implemented in a 1.5-μm CMOS technology. The only required external components are the reception antenna and a 32-kHz crystal. The radio receiver is dedicated to the 162-kHz “Allouis” radio transmitter. In addition to the audio information, 40-bit/s digital data are transmitted as phase modulation of the main carrier. These digital data may contain “live” information, such as the exact time. The presented ASIC demodulates and decodes these digital data. The principal features of this radio receiver are a low voltage supply (2.2-4.5 V), low power consumption (less than 150 μA), a large sensitivity range (10 μV-100 mV), and a reduced number of external components. Thanks to all of these performances, the circuit can be built in a wristwatch     

A fully integrated CMOS direct-conversion transmitter front-end for WiMAX

A naturally commutated six-pulse cycloconverter working in the inverting mode is used to feed power to a single phase AC motor at 400 Hz. The motor is connected at the input side of the cycloconverter while the three-phase mains is connected at its output. Three-phase mains feeds power to the input side of the cycloconverter which is arranged as a tuned load at 400 Hz. The effect of the single-phase induction motor on system performance is discussed. The principle of voltage and frequency control for proper operation of the induction motor is presented. The results are experimentally verified.     

A fully integrated CMOS receiver front-end for optic GigabitEthernet

A fully integrated fiber-optic receiver chip in a CMOS technology is presented. The design was done in a low-cost mixed-signal analog pure CMOS technology with 0.35-μm gate length. It incorporates every building block needed for standard fiber-optic receiver application, e.g., transimpedance amplifier, postamplifier, signal detect, and several control circuits. The chip works without any external components, such as capacitors usually needed to ensure the broadband operation down to several tens of kilohertz. Three designs were processed for typical data applications between 155 Mb/s and 1.25 Gb/s. The difference in the designs can be created by changing only one metal mask and programming some bandwidth and noise-relevant components on the chip. The results in sensitivity, dynamic range, and other behaviors are fully compliant with the relevant standards, such as SONET or IEEE 802.3 (Gigabit Ethernet) and future IEEE 1394 plastic optical fiber (POF) communication     

A fully integrated 24-GHz phased-array transmitter in CMOS

This paper presents the first fully integrated 24-GHz phased-array transmitter designed using 0.18-/spl mu/m CMOS transistors. The four-element array includes four on-chip CMOS power amplifiers, with outputs matched to 50 /spl Omega/, that are each capable of generating up to 14.5 dBm of output power at 24 GHz. The heterodyne transmitter has a two-step quadrature up-conversion architecture with local oscillator (LO) frequencies of 4.8 and 19.2 GHz, which are generated by an on-chip frequency synthesizer. Four-bit LO path phase shifting is implemented in each element at 19.2 GHz, and the transmitter achieves a peak-to- ratio of 23 dB with raw beam-steering resolution of 7/spl deg/ for radiation normal to the array. The transmitter can support data rates of 500 Mb/s on each channel (with BPSK modulation) and occupies 6.8 mm /spl times/ 2.1 mm of die area.     

A CMOS fully integrated antilarsen system for digital telephones

An integrated CMOS antilarson system that requires no external components is presented. Speech time constants as long as 100 ms are digitally realized. A 12-dB antilarsen depth and a 6-dB hysteresis are provided for the specific application where the system is involved, but both of them and the voice time constants can be register programmed to different values. The extra area added to the chip for the antilarsen function is only 0.5 mm² in a 1.5-μm CMOS technology     

GHz band frequency hopping PLL-based frequency synthesizers

In this paper we describe a full-integrated circuit containing all building blocks of a completed PLL-based synthesizer except for low pass filter（LPF）. The frequency synthesizer is designed for a frequency hopping （FH） transceiver operating up to 1.5 GHz as a local oscillator. The architecture of Voltage Controlled Oscillator （VCO） is optimized to get better performance, and a phase noise of -111.85-dBc/Hz @ 1 MHz and a tuning range of 250 MHz are gained at a centre frequency of 1.35 GHz. A novel Dual-Modulus Prescaler（DMP） is designed to achieve a very low jitter and a lower power. The settling time of PLL is 80 μs while the reference frequency is 400 KHz. This monolithic frequency synthesizer is to integrate all main building blocks of PLL except for the low pass filter, with a maximum VCO output frequency of 1.5 GHz, and is fabricated with a 0.18 μm mixed signal CMOS process. Low power dissipation, low phase noise, large tuning range and fast settling time are gained in this design.     

A crystal-tolerant fully integrated CMOS low-IF dual-band GPS receiver

This paper presents the design of a dual-band L1/L2 GPS receiver, that can be easily integrated in portable devices (mainly GSM mobile phones). For the ease of integration with GSM wireless systems the receiver can tolerate most of the common GSM crystals, besides the GPS crystals, this will eliminate the need to use another crystal on board. A new frequency plan is presented to satisfy this requirement. A low-IF receiver architecture is used for dual-band operation with analog on-chip image rejection. The receiver is composed of a narrow-band LNA for each band, dual down-conversion mixers, a variable-gain channel filter, a 2-bit analog-to-digital converter, and a fully integrated frequency synthesizer including an on-chip VCO and loop filter. The complex filter can accept IF frequency variation of 10% around 4.092 MHz which allows the use of the commonly used 10/13/26 MHz GSM crystals and all the GPS crystals. The synthesizer generates the LO signals for both L1/L2 bands with an average phase noise of −95 dBc/Hz. The receiver exhibits maximum gain of 112 and 115 dB, noise figures of 4 and 3.6 dB, and input compression points of −76 and −79 dBm for L1 and L2, respectively. An on-chip variable-gain channel filter provides IF image rejection greater than 25 dB and gain control range over 80 dB. The receiver is designed in 0.13 μm CMOS technology and consumes 18 mW from a 1.2-V supply.     

Digital techniques for integrated frequency synthesizers: a tutorial - [integrated circuits for communications]

Frequency synthesizers are essential components of modern, integrated wireless transceivers. Traditional analog and mixed-signal circuit design techniques are proving ineffective in achieving the challenging performance demands placed on these synthesizers, particularly in very fine fabrication technologies. Digital-intensive architectures and related digital signal processing techniques offer a robust, scalable alternative. A tutorial of the basic problems with frequency synthesizers, and a slew of recent digital techniques devoted to improving their performance, is presented.     

A fully integrated CMOS super-regenerative wake-up receiver for EEG applications

A fully integrated super-regenerative wake-up receiver for wireless body area network applications is presented. The super-regeneration receiver is designed to receive OOK-modulated data from the base station. A low power waveform generator is adopted both to provide a quench signal for VCO and to provide a clock signal for the digital module. The receiver is manufactured in 0.18 μm CMOS process and the active area is 0.67 mm². It achieves a sensitivity of -80 dBm for 10^-3 BER with a data rate of 200 kbps. The power consumption of the super-regenerative wake-up receiver is about 2.16 mW.     

A fully integrated, untrimmed CMOS instrumentation amplifier withsubmicrovolt offset

A low-noise CMOS instrumentation amplifier intended for low-frequency thermoelectric microsensor applications is presented that achieves submicrovolt offset and noise. Key to its performance is the chopper modulation technique combined with a bandpass filter and a matching on-chip oscillator. No external components or trimming are required. The achievable offset performance depends on the bandpass filter Q and the oscillator-to-bandpass filter matching accuracy. Constraints are derived for an optimum Q and a given matching accuracy. The improvement of common-mode rejection ratio (CMRR) in chopper amplifiers is discussed. The amplifier features a total gain of 77±0.3 dB and a bandwidth of approximately 600 Hz. The measured low-frequency input noise is 8.5 nV/√Hz and the input offset is 600 nV. The measured low-frequency CMRR is better than 150 dB. The circuit has been implemented in a standard 1-μm single-poly CMOS process     

A fully integrated 0.5-5.5 GHz CMOS distributed amplifier

A fully integrated 0.5-5.5-GHz CMOS-distributed amplifier is presented. The amplifier is a four stage design fabricated in a standard 0.6-μm three-layer metal digital-CMOS process. The amplifier has a unity-gain cutoff frequency of 5.5 GHz, and a gain of 6.5 dB, with a gain flatness of ±1.2 dB over the 0.5-4 GHz band. Input and output are matched to 50 Ω, with worst-case return losses on the input and output of -7 and -10 dB, respectively. Power dissipation is 83.4 mW from a 3.0 V supply, input-referred 1-dB compression point varies from +6 dBm at 1 GHz to 8.8 dBm at 5 GHz. From a circuit standpoint, the fully integrated nature of the amplifier on the given substrate results in a heavily parasitic-laden design. Discussion emphasis is therefore placed on the practical design, modeling, and CAD optimization techniques used in the design process