A 3-D Low Jitter and Skew Clock Distribution Network Scheme Using LTCC Package Level Interposer With a Planar Cavity Resonator

In this paper, we propose a new three-dimensional (3-D) clock distribution network (CDN) scheme using a low temperature co-fired ceramic (LTCC) package level interposer with a planar cavity resonator to achieve extremely low jitter and skew clock delivery even in severe power supply noise environments, especially for digital chips in 3-D stacked chip packages. It is based on a uniform-phase of the standing wave at the quarter-wavelength planar cavity resonator embedded inside the LTCC interposer. Substantial suppression of the timing jitter and skew was successfully demonstrated through a series of design, fabrication, and measurement processes of test devices and packages.      

硅通孔(TSV)转接板微组装技术研究进展

以硅通孔(TSV)为核心的三维集成技术是半导体工业界近几年的研发热点,特别是2.5D TSV转接板技术的出现,为实现低成本小尺寸芯片系统封装替代高成本系统芯片(So C)提供了解决方案。转接板作为中介层,实现芯片和芯片、芯片与基板之间的三维互连,降低了系统芯片制作成本和功耗。在基于TSV转接板的三维封装结构中,新型封装结构及封装材料的引入,大尺寸、高功率芯片和小尺寸、细节距微凸点的应用,都为转接板的微组装工艺及其可靠性带来了巨大挑战。综述了TSV转接板微组装的研究现状,及在转接板翘曲、芯片与转接板的精确对准、微组装相关材料、工艺选择等方面面临的关键问题和研究进展。     

Optimization for Chip Stack in 3-D Packaging

We have been developing three-dimensional (3-D) packaging technology for forming through-type electrodes in chips that are then directly connected in stacks. The model examined in this study is defined by its simple structure. The structure was optimized for successful connection in a chip stack without degrading the features of the chips. The use of this structure enabled a stable and rigid connection, and a four-layer chip stack assembled on a ceramic substrate exhibited adequate thermal cycle performance. This paper discusses how the structure of terminals was optimized for chip stacking. A finished package assembled from static random access memory (SRAM) with through-type electrodes was confirmed to operate well and exhibit normal functioning.     

Suppression of Power/Ground Inductive Impedance and Simultaneous Switching Noise Using Silicon Through-Via in a 3-D Stacked Chip Package

We have thoroughly investigated the advantages of a silicon through-via (STV) interconnection in decreasing the inductive impedance of a power distribution network (PDN) and suppressing simultaneous switching noise (SSN) in a 3-D stacked chip package. A double-stacked chip package with STV interconnections was fabricated and measured together with a similar double-stacked chip package with conventional bonding-wire interconnections. We successfully demonstrated that significant reduction of the inductive PDN impedance, from 1.66 nH to 0.79 nH, can be achieved by replacing the conventional bonding wires in the multiple-stacked chip package by STV interconnections. Furthermore, we have shown that the STV interconnections can considerably reduce high-frequency SSN, by more than 80%, compared to the conventional bonding-wire interconnections.     

2.5D硅转接板TSV结构研究

针对结构参数对TSV可靠性影响不明确的问题,文中采用有限元分析和模型简化的方法,分析了TSV结构在温度循环条件下的应力应变分布,并进一步研究了铜柱直径、SiO₂层厚度以及TSV节距等结构参数对TSV结构可靠性的影响。结果表明,采用文中的方法简化模型后得出的结果拟合度在0.95以上;在TSV结构上施加温度循环载荷时,在SiO₂界面会出现应力集中,而在钝化层中会出现应变增大;改变铜柱直径、绝缘层厚度和TSV节距将显著影响TSV结构的可靠性;减小填充铜的直径、增加SiO₂层的厚度、增加TSV节距,都将有助于减小TSV结构的最大应力。     

Architectural Implications and Process Development of 3-D VLSI$Z$-Axis Interconnects Using Through Silicon Vias

A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than today's advanced multichip modules. This technology overcomes the resistance–capacitance (RC) delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and three dimensional (3-D) stacking technology have the potential to reduce significantly the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. Although TSVs have great potential, there are many fabrication obstacles that must be overcome. This paper discusses the architectural possibilities enabled by TSVs, and the necessary TSV dimensions for dense$Z$-axis interconnect among logic blocks. It then describes the TSV requirements for the Defense Advanced Research Projects Agency (DARPA)-funded Vertically Integrated Sensor Arrays (VISA) program, and how those requirements differ from a more general purpose TSV technology. Finally, the TSV fabrication process being implemented at the University of Arkansas (UA) is described in detail. Though this process is being developed for the VISA program, it embodies many of the characteristics of a widely applicable TSV technology.     

高可靠大功率微波电路封装研究

本文叙述了高可靠大功率微波电路的封装设计及工艺研究情况。     

FOW在叠层CSP封装中的应用

随着电子封装微型化、多功能化的发展,三维封装已成为封装技术的主要发展方向,叠层CSP封装具有封装密度高、互连性能好等特性,是实现三维封装的重要技术。针对超薄芯片传统叠层CSP封装过程中容易产生圆片翘曲、金线键合过程中容易出现0BOP不良、以及线孤（wireloop）的CPK值达不到工艺要求等问题,文中简要介绍了芯片减薄方法对圆片翘曲的影响,利用有限元（FEA）的方法进行芯片减薄后对悬空功能芯片金线键合（Wirebond）的影响进行分析,Filmon Wire（FOW）的贴片（DieAttach）方法在解决悬空功能芯片金线键合中的应用,以及FOW贴片方式对叠层CSP封装流程的简化。采用FOW贴片技术可以达到30％的成本节约,具有很好的经济效益。     

Packaging and Assembly of 3-D Silicon Stacked Module for Image Sensor Application

This paper is for process development of assembly technologies used to fabricate the 3-D silicon carrier system-in–package (SiP). The five assembly technologies are wafer thinning, thin flip chip attach on silicon carrier, ultra low loop wire bonding, glass cap fabrication and sealing, and silicon carrier stacking. The developed SiP has three silicon carriers with four flip chip and one wire bond die chip attached to them and the carrier is stacked one above the other to form the 3-D silicon carrier SiP. Eight-inch bumped wafer thinning down to less than 100 $mu{hbox {m}}$, lower flip chip interconnect height between the chip and the carrier down to 35 $mu{hbox {m}}$, 40–50- $mu{hbox {m}}$ low loop wire bonding on overhang by direct reverse wire bonding method using 1-mil-diameter Au wire are achieved. And investigation of three types of thin film metallization systems for wirebonding and investigation of two different methods in fabricating glass cap are also studied.      

3-D Stacked Package Technology and Trends

The need to integrate more device technology in a given board space for handheld applications such as mobile phones has driven the adoption of innovative packages which stack such devices in the vertical or third dimension (3-D). Stacking of device chips in small and thin fine-pitch ball grid array packages has evolved into the stacking of packages themselves to achieve the same end. The advantage of stacking packages rather than device chips is that packages can be fully tested good prior to stacking. There are two primary ways to stack packages to achieve such vertical integration: package-on-package (PoP) and package-in-package (PiP). Innovative variations of PoP and PiP are being developed to address specific packaging needs and market trends. This paper will detail some of the key technology supporting PoP and PiP packages currently in production and the development of new variations of such packages to address future trends.      

High-Density Through Silicon Vias for 3-D LSIs

High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chemical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.      

高压硅堆在雷达发射机中的应用

较详细地介绍了高压硅堆在大功率电路中运用的成功经验和失败教训，列举了在高压整流电路、调制器内的充电电路、反峰电路、阻尼电路、高效率ｄｅ－Ｑ装置的回授电路和箝位限幅电路中运用高压硅堆的条件及工作状态的特点。指出了有些电路目前还不能用国产硅堆可靠地取代真空电子二极管的原因     

Microwave Silicon Windows for High-Power Broad-Band Switching Applications

Theoretical and experimental results obtained with a novel silicon window utilizing double-carrier injection to achieve high-power broad-band microwave switching are presented. The device consists of a wafer of high-resistivity silicon inserted across a waveguide with thin-line junction structures oriented orthogonal to the RF electric field. These line junctions provide hole-injecting contacts on one face and electron-injecting contacts on the other. With zero bias, the window appears as a thin low-loss dielectric slab, and the RF signal is transmitted. With forward bias, the window appears as a highly conductive slab due to the injected electron-hole plasma, and the RF signal is reflected. Calculations show that X-band windows 8 mils thick have a switching ratio of 0.5 to 15 dB if the resistivity change is from 300/spl Omega//spl dot/cm to 1/spl Omega//spl dot/cm. X-band windows have been fabricated having an insertion loss as low as 0.3 dB and a VSWR below 1.3 in the transmission state and an isolation as high as 18 dB (5 amperes at 1 volt) in the reflecting state. These characteristics are maintained across the complete waveguide band (8.2 to 12.4 GHz). Windows have been tested to 50-kW peak power without degradation in switching characteristics. The main advantages of the window over conventional p-i-n diodes are an order of magnitude or more increase in power handling (50 kW peak measured while 300 kW is predicted compared to 5 kW for a single p-i-n diode X-band high-power switch), full guide bandwidth operation (compared to 10 percent bandwidth for the conventional p-i-n), simpler bias circuitry (no reverse bias is required in the transmission state), and higher temperature operation (since no reverse voltage is needed).     

基于双面TSV互连技术的超厚硅转接板制备

为了满足异质集成应用中对转接板机械性能方面的需求,提出了一种基于双面硅通孔(TSV)互连技术的超厚硅转接板的制备工艺方案。该方案采用Bosch工艺在转接板正面形成300μm深的TSV,通过结合保型性电镀工艺和底部填充电镀工艺进行TSV填充。在转接板背面工艺中首先通过光刻将双面TSV的重叠部分控制在一个理想的范围内,然后经深反应离子刻蚀(DRIE)工艺形成深度为20μm的TSV并完成绝缘层开窗,最后使用保型性电镀完成TSV互连。通过解决TSV刻蚀中侧壁形貌粗糙、TSV底部金属层过薄和光刻胶显影不洁等关键问题,最终得到了双面互连电阻约为20Ω、厚度约为323μm的硅转接板。     

大功率LED封装散热技术研究

LED被称为第四代照明光源或者绿色光源,广泛地应用于手机闪光灯、大中尺寸显示器光源模块以及特殊用途照明系统,并将被扩展至一般照明系统设备.由于LED结温的高低直接影响到LED的出光效率、器件寿命、发光波长和可靠性等,因此如何提高散热能力是大功率LED实现产业化亟待解决的关键技术之一.介绍并分析了国内外大功率LED散热封装技术的研究现状,总结了其发展趋势并提出减少内部热沉的热阻可能是今后的发展方向.     

一种可用于硅刻蚀工艺模拟的三维表面演化算法

针对硅微加工中的刻蚀工艺模拟应用,提出了一种基于点元网格和单位法向最的三维表面演化算法,在形成的连续曲面上,以高斯积分法得到点元步进的单位法向量,实现三维表面的构建与推进.根据典型的刻蚀工艺及其物理模型,该表面演化算法能够用于硅等离子体刻蚀等与表面演化方向相关的工艺模拟.参照简单的各向同性刻蚀,利用该三维算法实现了不同...     

Reliability of a Silicon Stacked Module for 3-D SiP Microsystem

Solder joint reliability of 3-D silicon carrier module were investigated with temperature cycle and drop impact test. Mechanical simulation was carried out to investigate the solder joint stress using finite element method (FEM), whose 3-D model was generated and solder fatigue model was used. According to the simulation results, the stress involved between flip chip and Si substrate was negligible but stress is more concentrated between Si carriers to printed circuit board (PCB) solder joint area. Test vehicles were fabricated using silicon fabrication processes such as DRIE, Cu via plating, SiO deposition, metal deposition, lithography, and dry or wet etching. After flip chip die and silicon substrate fabrication, they were assembled by flip chip bonding equipment and 3-D silicon stacked modules with three silicon substrate and flip chip dies were fabricated. Daisy chains were formed between flip chip dies and silicon substrate and resistance measurement was carried out with temperature cycle test (C, 2 cycles/h). The tested flip chip test vehicles passed T/C 5000 cycles and showed robust solder joint reliability without any underfill material. Drop test was also carried out by JEDEC standard method. More details on test vehicle fabrication and reliability test results would be presented in the paper.     

DMD芯片在光栅投影三维轮廓测量技术中的应用

光栅投影成像法经常用于物体的非接触形状测量和形变测量。通过莫尔相移法,可以实时获得物体表面的等高轮廓线。但是在测量高速运动物体三维轮廓图像时误差较大,因为相移法需要拍摄几张经过相移后的变形光栅。在加入了DMD芯片后,可以在CCD的一帧图像时间内完成所有的相移后变形光栅的图像拍摄,有效地降低了高速运动物体三维轮廓成像的误差。     

芯片堆叠FPBGA产品翘曲度分析研究

翘曲问题广泛存在于基板类封装产品中,对于堆叠芯片FPBGA产品来说,控制产品的翘曲十分重要。在分析堆叠芯片FPBGA产品翘曲度与材料的热膨胀系数、体积、温度变化量关系的基础上,将翘曲仿真模拟和DOE相结合,确定出模塑料和芯片是影响翘曲度的主要因素,并找到最优化值。测量基板和产品的实际翘曲度,对比印证了仿真模拟的正确性,为设计开发类似产品时减小翘曲度提供了有效参考。