Guest Editorial Special Section on Low-Power Electronics and Design

The eight papers in this special section were published in the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), held in Tegernsee, Germany, October 4-6, 2006. The papers cover various areas related to low-power electronics and design, ranging from circuit and design technology to system level power modeling and optimization. The papers are summarized here.     

一种FPGA低功耗工作的实现方法

FPGA(Field-Programmable Gate Array)即现场可编程门阵列,作为专用集成电路(ASIC)领域中的一种半定制电路,具有成本低、可在线编程等优势,其并行运算的特点适用于大规模信号处理和数据计算等场合.随着近年来FPGA内部逻辑单元数量的提高以及片上系统的出现,应用范围更加广泛,功耗也相应增加.本文提出了一种FPGA低功耗工作的实现方法,利用外部CPU管理FPGA的电源电路,在FPGA程序挂起时降低动态功耗,特别是对需要电池的便携设备电池供电产品,可有效延长工作时间.     

Hardware compression scheme based on low complexity arithmetic encoding for low power image transmission over WSNs

Software implementation costs of most algorithms, designed for image compression in wireless sensor networks, do not justify their use to reduce the energy consumption and delay transmission of images. Even though the hardware solution looks to be very attractive for this problem, a specific care should be paid when designing a low power algorithm for image compression and transmission over these systems. The aim of this paper is to present and evaluate a hardware implementation for user-driven image compression scheme designed to respect the energy constraints of image transmission over wireless sensor networks (WSNs). The proposed encoder will be considered as a co-processor for tasks related with image compression and data packetization. In this paper, we discuss both of the hardware architecture and the features of this encoder circuit when prototyped on FPGA (field-programmable gate array) and ASIC (application-specific integrated circuit) circuits.     

Stateful-NOR based reconfigurable architecture for logic implementation

Most commercial Field Programmable Gate Arrays (FPGAs) have limitations in terms of density, speed, configuration overhead and power consumption mostly due to the use of SRAM cells in Look-Up Tables (LUTs), configuration memory and programmable interconnects. Also, hardwired Application Specific Integrated Circuit (ASIC) blocks designed for high performance arithmetic circuits in FPGA reduce the area available for reconfiguration. In this paper, we propose a novel generalized hybrid CMOS-memristor based architecture using stateful-NOR gates as basic building blocks for implementation of logic functions. These logic functions are implemented on memristor nanocrossbar layers, while the CMOS layer is used for selection and connection of memristors. The proposed pipelined architecture combines the features of ASIC, FPGA and microprocessor based designs. It has high density due to the use of nanocrossbar layer and high throughput especially for arithmetic circuits. The proposed architecture for three input one output logic block is compared with conventional LUT based Configurable Logic Block (CLB) having the same number of inputs and outputs; which shows 1.82×area saving, 1.57×speedup and 3.63×less power consumption. The automation algorithm to implement any logic function using proposed architecture is also presented.     

Phase assignment for synthesis of low-power domino circuits

High performance circuit techniques such as domino logic have migrated from the microprocessor world into more mainstream ASIC designs but domino logic comes at a heavy cost in terms of total power dissipation. A set of results related to automated phase assignment for the synthesis of low-power domino circuits is presented: (1) it is demonstrated that the choice of phase assignment at the primary outputs of a circuit can significantly impact lower dissipation in the domino block, and (2) a method to determine a phase assignment that minimises power consumption in the final circuit implementation is proposed. Preliminary experimental results on a mixture of public domain benchmarks and real industry circuits show potential power savings as high as 34% over the minimum area realisation of the logic. Furthermore, the low-power synthesised circuits still meet timing constraints     

Traceback-Based Optimizations for Maximum a Posteriori Decoding Algorithms

Maximum A Posteriori (MAP) decoding is a crucial enabler of turbo coding and other powerful feedback-based algorithms. To allow pervasive use of these techniques in resources constrained systems, it is important to limit their implementation complexity, without sacrificing the superior performance they are known for. We show that introducing traceback information into the MAP algorithm, thereby leveraging components that are also part of Soft-Output Viterbi Algorithms (SOVA), offers two unique possibilities to simplify the computational requirements. Our proposed enhancements are effective at each individual decoding iteration and therefore provide gains on top of existing techniques such as early termination and memory optimizations. Based on these enhancements, we will present three new architectural variants for the decoder. Each one of these may be preferable depending on the decoder memory hardware requirements and number of trellis states. Computational complexity is reduced significantly, without incurring significant performance penalty.

基于Matlab/Simulink的电力变换电路仿真

由于电力变换电路种类较多,在"电力电子"课程教学中,学生难以理解复杂电路.本文应用Matlab/Simulink强大的仿真功能,对各种电力电子变换电路进行建模仿真,并着重介绍了三相半波整流电路、三相桥式整流电路和直流斩波电路的仿真,并对其中的难点进行了详细分析.使学生对课堂上所学的内容有一个直观的认识,对加深学生的理解和后续学习有较大的作用.     

Ultra-low power FinFET-based domino circuits

Aggressive scaling of single-gate CMOS device face greater challenge in nanometre technology as sub-threshold and gate-oxide leakage currents increase exponentially with reduction of channel length. This paper discusses a double-gate FinFET (DGFET) technology which mitigates leakage current and higher ON state current when scaling is done beyond 32 nm. Here 8 and 16 input OR gate domino logic circuits are simulated on 32 nm FinFET Predictive technology model (PTM) on HSPICE. Simulation results of different 8 input OR gate domino logic circuits like Current-mirror footed domino (CMFD), High-speed clock-delayed (HSCD), Modified-HSCD (M-HSCD), Conditional evaluation domino logic (CEDL) and Conditional stacked keeper domino logic (CSK-DL), all operated in Short Gate (SG) and Low Power (LP) mode, shows tremendous reduction in average power consumption and delay. In this paper, domino logic-based circuit Ultra-Low Power Stack Dual-Phase Clock (ULPS-DPC) is proposed for both CMOS and FinFET (SG and LP modes). Proposed circuit shows maximum reduction in average power consumption of 84.04% when compared with CSK-DL circuit and maximum reduction in delay of 75.4% when compared with M-HSCD circuit at 10 MHz frequency when these circuits are simulated in SG mode.     

一种面向粗粒度可重构阵列的硬件木马检测算法的设计与实现

硬件木马检测已成为当前芯片安全领域的研究热点,现有检测算法大多面向ASIC电路和FPGA电路,且依赖于未感染硬件木马的黄金芯片,难以适应于由大规模可重构单元组成的粗粒度可重构阵列电路。因此,该文针对粗粒度可重构密码阵列的结构特点,提出基于分区和多变体逻辑指纹的硬件木马检测算法。该算法将电路划分为多个区域,采用逻辑指纹特征作为区域的标识符,通过在时空两个维度上比较分区的多变体逻辑指纹,实现了无黄金芯片的硬件木马检测和诊断。实验结果表明,所提检测算法对硬件木马检测有较高的检测成功率和较低的误判率。     

基于SOC的VC-1解码器软硬件协同设计及验证

提出了一种VC-1硬件解码器的SOC／ASIC设计方案,并在具体实现电路的基础上,重点讨论了软硬件协同设计方案及其验证策略的设计考虑。该设计方案已经通过基于FPGA的系统级验证。结果证明,设计方案完全可行。     

Analog Circuit Synthesis Using Linear and Nonlinear Current Amplifiers

Various design techniques are presented for obtaining current-mode filters suitable for operation at high frequencies. For this purpose CMOS and or bipolar current amplifiers are used as active building blocks. The derived circuits simulate LC passive prototype filters. Second order resonators can also be obtained by following the same techniques. The presented circuits are modular in structure, thus, their electronic and layout design is very easy. Low-voltage, low-power design is also feasible. Simulation examples for all-pole filters and filters with transmission zeros are given. George Souliotis received the B.Sc. degree in physics from the University of Ioannina, Ioannina, Greece, in 1993 and the M.Sc. and Ph.D. degrees in electronics from the University of Patras, Patras, Greece, in 1998 and 2003, respectively. From 2000 to 2002, he was with Giga Hellas, an Intel company, designing high-speed electronic circuits for transceivers for optical networks. He is co-inventor of a patent that was developed through that work. He is currently a Post-Doctoral Researcher with the Electronics Laboratory, Department of Physics, University of Patras, Patras, Greece. His research interests include analog and mixed signal integrated circuits for high-speed communication applications, current mode circuits, continuous time active filters and CMOS-BiCMOS VLSI design. Nikos Fragoulis was born in Megara Attikis, Greece, in 1972. He received the B.S. degree in physics and the M.Sc. degree in electronics and Ph.D. in electronics from the Electronics Laboratory, Department of Physics, University of Patras, Patras, Greece, in 1995, 1998 and 2005 respectively. He is currently a post-doctoral researcher with the Electronics Laboratory, Department of Physics, University of Patras, Patras Greece. His research interests include, continuous time filtering, and analog integrated circuits for broadband telecommunication applications. Ioannis Haritantis received the Ph.D. in Electronics, in 1976, from the Physics Department, University of Patras, Patras, Greece, in collaboration with the Electrical Engineering Department, Imperial College, London, UK. For many years he has conducted scientific research on the development and design of circuits, discrete component and/or integrated, which are suitable for analog signal processing. His other fields of interest include, network theory, design and testing of integrated circuits, integrated active devices for telecommunications and medical instrumentation, smart sensors, and e-learning. During the past few years his focus is on the design of low-power, low-voltage, tunable, integrated active filters of high dynamic range that could operate at high frequencies. Professor Haritantis in now the director of the Electronics Laboratory, Division of Electronics and Computers, Department of Physics, University of Patras, Patras, Greece. He is also in the editorial board of the journal “Analog Integrated Circuits and Signal Processing”, Kluwer Academic Publishers.     

Securing Encryption Systems With a Switched Capacitor Current Equalizer

Hardware encryption engines are essential components of secure systems. They are widely used in desktop applications such as the trusted platform module as well as in mobile applications where they offer high energy efficiency compared to their software implementation counterparts. Unfortunately, ASIC encryption engines leak side-channel information through their power supplies. This information can be used by attackers to reveal their secret keys with attacks such as differential power analysis. Dual-rail logic and noise addition circuits increase the security against these attacks, but they add higher than 3x overheads in area, power, and performance to unsecured encryption engines. In this work, we present a switched capacitor circuit that equalizes the current to isolate the critical encryption activity from the external supplies, eliminating the side-channel information leakage. The secure encryption system was implemented in a 0.13 ?m CMOS technology with 7.2% area and 33% power overheads and a 2 × performance degradation. The secret encryption key was not revealed after ten million side-channel attacks.     

A New Differential CMOS Current-Mode Preamplifier for GBps Data Communications

This paper presents a new low-voltage fully differential CMOS current-mode preamplifier for GBps data communications. The number of transistors between the power and ground rails is only two so that the minimum supply voltage is one threshold voltage plus one pinch-off voltage. The preamplifier is a balanced two-stage configuration such that the effect of bias-dependent mismatches is minimized. A new inductive series-peaking technique is introduced to increase the bandwidth by utilizing the resonance characteristics of LC networks. In addition, a new negative differential current feedback technique is proposed to boost the bandwidth and to reduce the value of peaking inductors. The preamplifier has been implemented in TSMC 0.18 μm, 1.8 V, 6-metal mixed-mode CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3v3 device models. For an optical front-end with a 0.3 pF photodiode capacitance, simulation results demonstrate that the preamplifier has bandwidth of 3.5 GHz and provides a transimpedance gain of 66 dBΩ. The total chip area is approximately 1 mm² and the DC power consumption is about 85 mW. Bendong Sun received the B.Eng. degree in electrical engineering from Shanghai Jiaotong University, Shanghai, China, in1992, and the MASc degree in electrical and computer engineering from Ryerson University, Toronto, Ontario, Canada, in 2003. He is currently working towards the Ph.D. degree in electrical and computer engineering at University of Waterloo, Waterloo, Ontario, Canada. During 1992 through 1998 he was a Design Engineer at China Electronics Engineering Design Institute, Beijing, China. From 1998 to 2000 he worked for Bently Nevada Corporation, a GE Power Systems business, as a System Engineer. Since 2001, he has been a Research Assistant with the System-on-Chip Laboratory at Ryerson University. His research interests include design of analog and mixed-signal integrated circuits for high-speed data communications. Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the MASc degree in chemical engineering and PhD degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively. During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Canada. During 1989–1994, he worked for Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer. Since July 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book “Computer Methods for Analysis of Mixed-Mode Switching Circuits” (Kluwer Academic Publishers, 2004, with Ajoy Opal). Dr. Yuan received an “Excellence of Teaching" award from Changzhou Institute of Technology in 1988, a post-graduate scholarship from Natural Science and Engineering Research Council (NSERC) of Canada during 1997–1998. He is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada. Ajoy Opal (S'86-M'88) received the B. Tech degree from Indian Institute of Technology, New Delhi, India in 1981, and the MASc and PhD degrees from University of Waterloo, Waterloo, Ontario, Canada in 1984 and 1987, respectively. During 1989–92 he worked for Bell-Northern Research in the area of analog circuit simulation. He joined the Department of Electrical and Computer Engineering, University of Waterloo in 1992 and currently a Full Professor. Dr. Opal works in the area of simulation of analog and mixed digital-analog circuits, such as, switched capacitor, switched current, oversampled sigma-delta modulators. Other interests include circuit theory and filter design.     

A high precision temperature control system for CMOS integrated wide range resistive gas sensors

In this work we present an integrated interface for wide range resistive gas sensors able to heat the sensor resistance through a constant power heater block at 0°C–350°C operating temperatures. The proposed temperature control system is formed by a sensor heater (which fixes the sensor temperature at about 200°C), a R/f (or R/T) converter, which converts the resistive value into a period (or frequency), and can be able to reveal about 6 decades variation (from 10 KΩ up to 10 GΩ), and a digital subsystem that control the whole systems loop. This interface allows high sensibility and precision and performs good stability in temperature and power supply drift and low power characteristics so it can be used also in portable applications. Test measurements, performed on the fabricated chip, have shown an excellent agreement between theoretical expectations and simulation results. Giuseppe Ferri is an associate professor in Electronics at the Department of Electrical Engineering of L’ Aquila University, Ital. In 1993 he has been a visiting researcher at SGS-Thomson Milano, working in bipolar low-voltage op-amp design. In 1994-95 he has been visiting researcher at KU Leuven working in low-voltage CMOS design in the group of Prof. Sansen. His research activity is actually centred on the analog design of integrated circuits for portable applications (e.g., sensors and biomedicals) and circuit theory. He is co-author of a book entitled “Low Voltage, Low Power CMOS Current Conveyors”, Kluwer ed. (2003) and four text-books in Italian on Analogue Microelectronics (2005, 2006). Moreover, he is author and co-author of 74 papers on international and Italian journals and 123 talks at national and international conferences. Vincenzo Stornelli was born in Avezzano (AQ), Italy, on May 31, 1980. He received the Electronics Engineering degree (cum laude) in July 2004. In October 2004 he joined the Department of Electronic Engineering, University of L’Aquila, where he is actually involved with problems concerning project and design of integrated circuits for RF and sensor applications, CAD modelling, characterization, and design analysis of active microwave components, circuits, and subsystems. He regularly teaches courses of the European Computer patent and has regular collaborations with national corporations such as Thales Italia     

低功耗测试矢量生成技术的研究

在集成电路内建自测试的过程中,电路的测试功耗通常显著高于正常模式产生的功耗,因此低功耗内建自测试技术已成为当前的一个研究热点。为了减少被测电路内部节点的开关翻转活动率,研究了一种随机单输入跳变（Random Single Input Change,RSIC）测试向量生成器的设计方案,利用VHDL语言描述了内建自测试结构中的测试向量生成模块,进行了计算机模拟仿真并用FPGA（EP1C6Q240C8）加以硬件实现。实验结果证实了这种内建自测试原理电路的正确性和有效性。     

Find, filter, and retrieve from the Web ocean [book review]

The article is a review of the book: Knowledge-Based Information Retrieval and Filtering from the Web by Witold Abramowiecz (editor) and published by Kluwer Academic Publishers, 2003. The book presents trends and technologies in information filtering and retrieval, offering a complete overview of this field. Editor Witold Abramowicz has gathered a team of this subject's leading international researchers. In the exhaustive preface, he introduces the world of information filtering and retrieval as one that can be overwhelming. He outlines the significance of the tools developed in this field-tools created to make our jobs, decision making, and daily lives easier. The reviewer concludes that the book isn't an easy read. To understand it, you need a sound background in information and Internet techniques, math, and logic. For someone familiar with this subject, the book will be valuable, but it's definitely not for beginners.     

用普通基比特串行乘法电路实现(204, 188)RS码译码

用普通基比特串行乘法电路实现数字视频广播(DVB)中(204,188)RS码译码,使电路大大简化,并保持译码速率与视频信号比特和码速率一致,电路整齐规则,便于FPGA实现或专用集成电路设计,具有推广实用价值。     

面向密码算法的异步可重构结构设计

针对FPGA和ASIC在实现密码算法时的不足之处，本文介绍了一种面向密码算法的异步可重构结构。该结构的运算功能由一个可重构单元阵列提供，数据通路由可重构单元之间的相互连接实现，异步通信采用握手信号完成。在分析握手信号传输延时对可重构结构的影响后，文章提出了一种适合该结构的单元信号传输握手控制电路。同时在单元结构中，使用改进的DSDCVS逻辑来设计其运算电路，减小了单元的面积，提高了单元的工作速度。应用实例表明，在实现密码算法时，面向密码算法的异步可重构结构表现出了比FPGA更好的性能。     

用流水线技术实现STM-16帧定位电路设计

在高阶宽带电路交换专用集成电路(ASIC)芯片设计中,输入数据的帧定位和数据重排操作需要占用大量的逻辑电路.文章提出了一种流水线结构的帧定位电路设计方式,给出了STM 16码流的帧定位和数据重排的两种不同电路设计实现方案.试验结果表明,采用流水线结构设计实现的STM-16帧定位电路,可明显减小电路规模,降低芯片功耗,提高芯片的可靠性和整体性能.