USB3.0中五分频电路设计

基于65 nm CMOS工艺,分别采用CML电路和TSPC电路设计并实现一种新型五分频电路,适用于USB 3.0物理层中时钟频率的五分频转换,且输出占空比基本满足50%,仿真结果表明采用CML电路构建的分频器可稳定工作在8 GHz的输入时钟频率,此时功耗为1.9 mW,采用TSPC电路构建的分频器可稳定工作在10 GHz输入时钟频率,此时功耗为0.2 mW,2种分频电路都满足USB 3.0规范要求,完全达到预期目标。     

Full-Swing Gate Diffusion Input logic—Case-study of low-power CLA adder design

Full Swing Gate Diffusion Input (FS-GDI) methodology is presented. The proposed methodology is applied to a 40 nm Carry Look Ahead Adder (CLA). The CLA is implemented mainly using GDI full-swing F1 and F2 gates, which are the counterparts of standard CMOS NAND and NOR gates. A 16-bit GDI CLA was designed in a 40 nm low power TSMC process. The CLA, implemented according to the proposed methodology, presents full functionality and robustness under global and local process variations at wide range of supply voltages. Simulation results show 2× area reduction, 5× improvement in dynamic energy dissipation and 4× decrease in leakage, with a slight (24%) degradation in performance, when compared to the CMOS CLA. Advanced design metrics of GDI cells, such as minimum energy point (MEP) operation and minimum leakage vector (MLV), are discussed.     

中大功率单相功率因数校正器的设计与实现

采用有源功率因数校正技术(active power factor correction,APFC)设计并实现了一款高功率因数、高效率、低谐波、低噪声的"绿色"功率因数校正装置.1700 W样机实验结果表明:所设计的功率因数校正装置能在165～275 V AC宽电压范围内,得到稳定的直流电压输出;输入交流电流能很好的跟踪...     

防DPA攻击的标准单元库的设计与实现

给出了一个功耗恒定标准单元库的设计实现方法,并利用该标准单元库实现了DES密码算法中的S-盒。实验结果表明,这种标准单元库能够很好地起到防DPA攻击的作用。     

升压型同步整流功率MOSFET的分析及电路仿真

同步整流技术已成为目前提升开关电源芯片转换效率的有效手段.以采用UMC 0.6μm BiCMOS工艺制造的升压转换器为例,基于功率MOS管工作机理,对不同的负载情况和工作模式分别加以分析和模拟验证,并提出了管子尺寸的合理选择和死区时间的合理设置.为了避免电感电流倒灌,提出了DCM模式下过零检测结构电路.利用HSPICE对相关电路进行了仿真分析,得到了同步整流技术中功率器件的优化结果.     

Catastrophic Short and Open Fault Detection in Bipolar CML Circuits: A Case Study

The detection of catastrophic short and open faults in bipolar current mode logic (CML) circuits is studied. The non-intrusive tests considered include functional (logic) tests, an I_dd test, and a common-mode test. A 622 Mbps SONET SIPO (Serial-In/Parallel-Out) and a PISO (Parallel-In/Serial-Out) circuit form the basis of this case study.     

Key optimization techniques in JPEG-LS IP core design

This paper presents the key optimization techniques for an efficient accelerator implementation in an image encoder IP core design for real-time Joint Photographic Experts Group Lossless(JPEG-LS) encoding.Pipeline architecture and accelerator elements have been utilized to enhance the throughput capability.Improved parameters mapping schemes and resource sharing have been adopted for the purpose of low complexity and small chip die area.Module-level and fine-grained gating measures have been used to achieve...     

FED显示驱动电路结构及其场发射特性分析

从场发射的基本原理出发,分析了影响场发射电流的内外因素。阴极表面强电场是产 生发射电流的必要条件,但像素的不均匀性和场发射特性的非线性导致无法产生精确的发射电流,由此带来了亮度调节的可控性差;阴极驱动电路作为发射电流回路的一部分,其电路结构直接影响发射电流的控制特性,分析表明电流驱动模式能对阳极束电流进行精确控制,是实现FED亮度控制的理想驱动方式。     

New design of low power, 100 Mb-s IR-UWB pulse generator in 0.18 µm CMOS technology

A new method of impulse radio ultra-wideband (IR-UWB) pulse generation, with advantage of providing a “notch” like representation of pulse in the spectrum domain for particular control parameters values, is investigated in this paper. Low power pulse generator is composed of a glitch generator, a switched oscillator, a two-stage buffer and a pulse shaping filter. The proposed architecture, designed in UMC 0.18 µm CMOS technology, can operate in a single band from 3.3 GHz to 9.3 GHz or in a double, lower and higher UWB band (from 3 GHz to 9.15 GHz), suppressing frequencies in the WLAN band. Both spectrums fully comply with the corresponding FCC spectral mask, while the pulse generator regime and the spectrum range are determined by control signal values. Post-layout simulation results showed a pulse width of 0.5 ns, and a peak-to-peak amplitude of 211 mV for one band spectrum. The average power consumption is 0.89 mW corresponding to the energy consumption of 8.9 pJ/pulse for 100 MHz pulse repetition rate (PRF). The pulse duration is 1 ns and peak-to-peak amplitude is 202 mV in the case of the WLAN frequency band suppression. The total chip area is 0.31 mm². The pulse generator has been evaluated for the best performance supporting the on-off keying (OOK) modulation.     

Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current

Dual threshold voltages domino design methodology utilizes low threshold voltages for all transistors that can switch during the evaluate mode and utilizes high threshold voltages for all transistors that can switch during the precharge modes. We employed standby switch can strongly turn off all of the high threshold voltage transistors which enhances the effectiveness of a dual threshold voltage CMOS technology to reduce the subthreshold leakage current. Subthreshold leakage currents are especially important in burst mode type integrated circuits where the majority of the time for system is in an idle mode. The standby switch allowed a domino system enters and leaves a low leakage standby mode within a single clock cycle. In addition, we combined domino dynamic circuits style with pass transistor XNOR and CMOS NAND gates to realize logic 1 output during its precharge phase, but not affects circuits operation in its evaluation and standby phase. The first stage NAND gates output logic 1 can guarantee the second stage computation its correct logic function when system is in a cascaded operation mode. The processing required for dual threshold voltage circuit configuration is to provide an extra threshold voltage involves only an additional implant processing step, but performs lower dynamic power consumption, lower delay and high fan-out, high switching frequencies circuits characteristics. SPICE simulation for our proposed circuits were made using a 0.18 µm CMOS process from TSMC, with 10 fF capacitive loads in all output nodes, using the parameters for typical process corner at 25 °C, the simulation results demonstrated that our designed 8-bit carry look-ahead adders reduced chip area, power consumption and propagation delay time more than 40%, 45% and around 20%, respectively. Wafer based our design were fabricated and measured, the measured data were listed and compared with simulation data and prior works. SPICE simulation also manifested lower sensitivity of our design to power supply, temperature, capacitive load and process variations than the dynamic CMOS technologies.     

Analysis and design of continuous class-E power amplifier at sub-nominal condition

The continuous class-E power amplifier at sub-nominal condition is proposed in this paper. The class-E power amplifier at continuous mode means it can be high efficient on a series matching networks while at sub-nominal condition means it only requires the zero-voltage-switching condition. Comparing with the classical class-E power amplifier, the proposed design method releases two additional design freedoms, which increase the class-E power amplifier’s design flexibility. Also, the proposed continuous class-E power amplifier at sub-nominal condition can perform high efficiency over a broad bandwidth. The performance study of the continuous class-E power amplifier at sub-nominal condition is derived and the design procedure is summarised. The normalised switch voltage and current waveforms are investigated. Furthermore, the influences of different sub-nominal conditions on the power losses of the switch-on resistor and the output power capability are also discussed. A broadband continuous class-E power amplifier based on a Gallium Nitride (GaN) transistor is designed and testified to verify the proposed design methodology. The measurement results show, it can deliver 10–15 W output power with 64–73% power-added efficiency over 1.4–2.8 GHz.     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

基于部分积概率分析的高精度低功耗近似浮点乘法器设计

浮点乘法器是高动态范围(HDR)图像处理、无线通信等系统中的关键运算单元,其相比于定点乘法器动态范围更广,但复杂度更高。近似计算作为一种新兴范式,在受限的精度损失范围内,可大幅降低硬件资源和功耗开销。该文提出一种16 bit半精度近似浮点乘法器(App-Fp-Mul),针对浮点乘法器中的尾数乘法模块,根据其部分积阵列中出现1的概率,提出一种对输入顺序不敏感的近似4-2压缩器及低位或门压缩方法,在精度损失较小的条件下有效降低了浮点乘法器资源及功耗。相较于精确设计,所提近似浮点乘法器在归一化平均错误距离(NMED)为0.0014时,面积及功耗延时积方面分别降低20%及58%;相较于现有近似设计,在近似位宽相同时具有更高的精度及更小的功耗延时积。最后将该文所提近似浮点乘法器应用于高动态范围图像处理,相比现有主流方案,峰值信噪比和结构相似性分别达到83.16 dB 和 99.9989%,取得了显著的提升。     

Measuring the uniqueness and variety of analog circuit design features

Analog circuit design activity is currently a less formalized process, in which the main source for innovation is the designer's ability to produce new designs by combining basic devices, sub-circuits, and ideas from similar solutions. There are few systematic methods that can fuse and transform the useful features of the existing designs into new solutions. Moreover, most automated circuit synthesis tools are still limited to routine tasks, like transistor sizing and layout design. Developing new design techniques that can combine the existing design features requires metrics that describe the uniqueness and variety of the features. This paper evaluates for analog circuits two such general-purpose metrics proposed in [1] and [2]. Three case studies are discussed on using the metrics to characterize the design features of current mirrors, transconductors, and operational amplifiers. The two metrics and the presented study is useful in producing an overall characterization of analog circuit features. This can help in enhancing the circuit design process, training of young designers, and developing new automated synthesis tools that can explore more solution space regions that are likely to include novel design features.     

光刻、OPC与DFM

讨论了90/65nm芯片设计采用可制造性设计的必要性和优势。介绍了以RET/OPC为核心的可制造性设计。     

FMEA设计与失效分析数据库的建设

文章主要介绍FMEA（Fail Mode and Effect Analysis）设计与失效分析数据库的建设。通过失效分析、器件研究总结出设计准则,同时设计人员能方便通过网络登陆失效分析数据库管理系统导出设计准则并进行实时查询核对并开展FMEA评审,以规避设计失误,该系统建立完成后在该公司各类产品上广泛应用,产品设计质量明显提高,开发质期也得以缩短。     

A 1-V, 1.2-mA fully integrated SoC for digital hearing aids

Both power and size are very important design issues for hearing aids. This paper proposes a fully integrated low-power SoC for today׳s digital hearing aids. The SoC integrates all the audio processing elements on single chip, including the analog front-end, digital signal processing (DSP) platform and class-D amplifier. Also, the low-dropout voltage regulators and internal clock generator are both integrated to minimize the system overall size. The 24-bit DSP platform comprises an application-specific instruction-set processor and several dedicated accelerators to achieve a trade-off between flexibility and power efficiency. Three critical hearing-aid algorithms (wide dynamic range compression, noise reduction and feedback cancellation) are performed by the low-power accelerators. The proposed SoC has been fabricated in SMIC 130 nm CMOS technology. The measurement results show that the analog front-end has up to 88 dB signal-to-noise ratio. And the DSP platform consumes about 0.86 mA current at 8 MHz clock frequency when executing the three algorithms. The total current consumption of SoC is only 1.2 mA at 1 V supply. In addition, the acoustic test results indicate that the SoC is one promising candidate for hearing-aid manufacturers.     

SEC中的全数字锁相环的分析及设计

文章首先介绍了全数字锁相环(ADPLL)的基本结构和工作原理,并进行了数学建模,计算了其主要的参数指标;然后,针对SDH设备时钟(SEC)设计了一种切实可行的低抖动ADPLL的电路结构,并对其各个组成部分进行了具体的电路分析和设计,通过微机适当配置,可以使该设计的结果得到优化;最后,通过现场可编程门阵列(FPGA)验证,给出了测试结果.     

ANALYSIS AND DESIGN OF THE STABLE PARALLEL PACKET SWITCH

This paper analyzes the Parallel Packet Switch(PPS) architecture and studies how to guarantee its performance. Firstly a model of Stable PPS (SPPS) is proposed. The constraints of traffic scheduling algorithms, the number of switching layers and internal speedup, for both bufferless and buffered SPPS architecture, are theoretically analyzed. Based on these results, an example of designing a scalable SPPS with 1.28T capacity is presented, and practical considerations on implementing the scheduling algorithm are discussed. Simulations are carried out to investigate the validity and delay performance of the SPPS architecture.