A new inverter-based charge pump circuit with high conversion ratio and high power efficiency

The current paper presents a new inverter-based charge pump circuit with high conversion ratio and high power efficiency. The proposed charge pump, which consists of a PMOS pass transistor, inverter-based switching transistors, and capacitors, can improve output voltage and conversion ratio of the circuit. The proposed charge pump was fabricated with TSMC 0.35 μm 2P4M CMOS technology. The chip area without pads is only 0.87 mm×0.65 mm. The measured results show that the output voltage of the four-stage charge pump circuit with 1.8 V power supply voltage (V_DD=1.8 V) can be pumped up to 8.2 V. The proposed charge pump circuit achieves efficiency of 60% at 80 μA.     

A novel current reference based on subthreshold MOSFETs with high PSRR

A novel current reference based on subthreshold MOSFETs with high power supply rejection ratio (PSRR) is presented. The proposed circuit takes full advantages of the I-V transconductance characteristics of MOSFET operating in the subthreshold region and the enhancement pre-regulator with the high gain negative feedback loop for the current reference core circuit. The proposed circuit, designed with the SMIC 0.18 μm standard CMOS logic process technology, exhibits a stable current of about 1.701 μA with much low temperature coefficient of 2.5×10⁻⁴ μA/°C in the temperature range of −40 to 150 °C at 1.5 V supply voltage, and also achieves a best PSRR over a broad frequency. The PSRR is about −126 dB at dc frequency and remains −92 dB at the frequency higher 1 MHz. The proposed circuit operates stably at the supply voltage higher 1.2 V and has good process compatibility.     

Novel low-voltage ultra-low-power DVCC based on floating-gate folded cascode OTA

In this paper a novel low-voltage ultra-low-power differential voltage current conveyor (DVCC) based on folded cascode operational transconductance amplifier OTA with only one differential pairs floating-gate MOS transistor (FG-MOST) is presented. The main features of the proposed conveyor are: design simplicity; rail-to-rail input voltage swing capability at a low supply voltage of ±0.5 V; and ultra-low-power consumption of mere 10 μW. Thanks to these features, the proposed circuit could be successfully employed in a wide range of low-voltage ultra-low-power analog signal processing applications. Implementation of new multifunction frequency filter based on the proposed FG-DVCC is presented in this paper to take the advantages of the properties of the proposed circuit. PSpice simulation results using 0.18 μm CMOS technology are included as well to validate the functionality of the proposed circuit.     

Integrated linear giga-ohm resistance using current scaling

Integrated grounded resistors of very large value are essential circuit elements for the design of compact filters with very low cut-off frequencies. A typical application of such filters is the rejection of DC voltages in amplifier circuits especially in physiological recording systems exhibiting electrode offset and low-frequency drift. In this letter, the implementation of a giga-ohm resistance is presented using a conventional fixed-gain OTA and a cascade of weak-inversion current scalers. The circuit yields a short design time, small power and area consumption as well as high linearity. A test circuit having an area of 0.011 mm² integrated in 0.35 μm CMOS is presented which yields a 41 Hz cut-off frequency, 1 V input range and less than −52 dB THD when connected to an integrated 1 pF capacitor, making it a suitable solution for the rejection of mains interference and offset in wearable biomedical applications.     

A wide-range all digital DLL for multiphase clock generation

This paper presents a wide-range all digital delay-locked loop (DLL) for multiphase clock generation. Using the phase compensation circuit (PCC), the large phase difference is compensated in the initial step. Thus, the proposed solution can overcome the false-lock problem in conventional designs, and keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. Furthermore, the proposed all digital multiphase clock generator has wide ranges and is not related to specific process. Thus, it can reduce the design time and design complexity in many different applications. The DLL is implemented in a 0.13 μm CMOS process. The experimental results show that the proposal has a wide frequency range. The peak-to-peak jitter is less than 7.7 ps over the operating frequency range of 200 MHz-1 GHz and the power consumption is 4.8 mW at 1 GHz. The maximum lock time is 20 clock cycles.     

Low-voltage CMOS current-mode exponential circuit with 70 dB output dynamic range

The paper proposes new accurate exponential circuits, having a multitude of practical applications in analog signal processing. The original method for obtaining the exponential function is based on the utilization of new superior-order approximation functions. The accuracy of the proposed structures is excellent and the output dynamic range is strongly extended as a result of the fourth-order approximation and of the independence of implemented function on technological errors and on temperature variations (the best original proposed architecture of the exponential generator has an output dynamic range of 70 dB for an approximation error smaller than ±1 dB). The exponential circuits are designed for implementing in 0.18 µm CMOS technology, having a low-voltage operation (a minimal supply voltage of 1 V). The power consumptions of the proposed exponential circuits are smaller than 0.08 mW, for a supply voltage of 1 V. As application of the new exponential circuit, a dB-linear VGA circuit with high output dynamic range will be presented. The new computational structures have the possibility of generating any continuous mathematical function, presenting also an increased modularity and controllability and reduced design costs per implemented function.     

Low cost bulk-silicon CDMOS technology and enhanced dv/dt high voltage driver circuit for PDP data driver IC

In this paper, a 256-channel data driver IC for plasma display panels (PDPs) is proposed. A new low cost 0.5 μm bulk-silicon CDMOS (CMOS and DMOS) technology is developed, resulting in the improvement of input data frequency up to 120 MHz and reduction of die cost about 20% compared with the conventional one. A novel high voltage driver circuit is also presented to optimize dv/dt of the output signal from 1.2 to 0.2 V/ns. The proposed circuit can avoid unwanted turning on of the pLEDMOS transistors in output stage and cut down the power dissipation by 12% compared with the conventional one. The application results show rising and falling times of the output stage are 45 and 84 ns, respectively.     

An integrated readout circuit for personal dosimetry with phase-shift compensation technique to improve stability

In this paper an integrated CMOS readout circuit for a radiation detector in a personal dosimeter is presented. High counting rate and low power requirements make the stability of the conventional high-pass pulse shaper a big problem. A novel phase-shift compensation method is proposed to improve the phase margin. The principle of the compensation circuit and its influence on noise performance are analyzed theoretically. A readout chip with two channels of conventional structure and one channel of the proposed structure has been implemented in a 0.35 μm CMOS technology. It occupies an area of 2.113×0.81 mm². Measurement results show that the proposed channel can process up to 1 MHz counting rate and provide a conversion gain of about 170 mV/fC at a power dissipation of 330 μW with a 3.3 V power supply. Ac-coupled to a silicon PIN detector, it successfully detects β-rays.     

Design and testing of a self-powered 3D integrated SOI CMOS system

A self-powering 3D integrated circuit built using an SOI CMOS process is presented. The 3D integrated circuit has three tiers connected by vertical vias through the intertier oxides. The circuit elements are a photodiode array, a charge-integrating capacitor, and a local oscillator with an output buffer, each on a separate tier. The final system size is 250 μm × 250 μm × 696 μm. Our results demonstrate the circuit as a feasible proof-of-concept 3D “system”. The photodiode array stores charge on the capacitor and powers the oscillator as designed.     

Analysis and design of wide band Microstrip-line-fed antenna with defected ground structure for Ku band applications

A wide band Microstrip antenna is proposed for Ku band applications with defected ground structure. A circular shape defect is integrated in the ground plane. A novel equivalent circuit model is proposed for Microstrip patch antenna with defected ground structure. Accurate design equations are presented for the wideband Microstrip antenna and theoretical analysis is done for the proposed structure. The proposed antenna has an impedance bandwidth of 56.67% ranging from 9.8 GHz to 17.55 GHz, which covers Ku-band and partially X-band. The antenna shows good radiation characteristics within the entire band, and has a gain ranging from 5 dBi to 12.08 dBi. Minimum isolation between co-polar and cross-polarization level of 20 dB and 15 dB is achieved in H-plane and E-plane respectively. The simulation of the proposed antenna is done on HFSS v.14, and measured results of fabricated antenna are in good agreement with the theoretical and simulated results.     

An ultra-low-power CMOS voltage reference generator based on body bias technique

A CMOS voltage reference, based on body bias technique, has been proposed and simulated using SMIC 0.18 μm CMOS technology in this paper. The proposed circuit can achieve a temperature coefficient of 19.4 ppm/°C in a temperature range from −20 °C to 80 °C, and a line sensitivity of 0.024 mV/V in a supply voltage range from 0.85 V to 2.5 V, without the use of resistors and any other special devices such as thick gate oxides MOSFETs with higher threshold voltage. The supply current at the maximum supply voltage and at 27 °C is 214 nA. The power supply rejection ratio without any filtering capacitor at 10 Hz and 10 kHz are −88.2 dB and −36 dB, respectively.     

A dynamically reconfigurable NRTI switched-capacitor-based hybrid DC-DC converter suitable for embedded applications

In this paper, a dynamically reconfigurable, Non-overlap Rotational Time Interleaved (NRTI) switched capacitor (S-C) DC-DC converter is presented. Its S-C module is reconfigurable to generate three different fractions (viz., 1/3, 1/2 and 2/3) of its input supply (Vdd). This maintains good power efficiency while its output voltage gets adjusted over a large range. In addition, a load-current-sensing circuit is integrated within it to dynamically reconfigure the S-C module based on the required driving capability. This feature enables to extend load current range to higher limit and at the same time improves the power efficiency in low load current regime. The S-C module is integrated with a current control loop for load and line regulation.The proposed architecture is simulated in a 0.18 μm CMOS process using dual oxide transistors to demonstrate the efficacy of the proposed topology. The input supply voltage is 3.3 V and the regulated output range is 0.8-1.6 V. Total flying capacitance is 330 pF and the load capacitor value is 50 pF. For an output of 1.35 V, its power efficiency is maintained above 50% over a load current range of 4 -17.6 mA with a peak of 66% at 9 mA. Throughout this current range the output voltage ripple remains within 12 mV.     

A new 0.35 μm CMOS electronic interface for wide range floating capacitive and grounded/floating resistive sensor applications

In this paper we propose a novel interface circuit suitable for the read-out of both wide range floating capacitive and grounded/floating resistive sensors. This solution, employing only two Operational Amplifiers (OAs) as active blocks and some passive components, is based on a square-wave oscillating circuit topology which, instead of a voltage integration typically performed by other solutions in the literature, operates a voltage differentiation. Therefore, the proposed circuit, performing an impedance-to-period (Z–T) conversion, results to be suitable as first analog front-end for both wide variation capacitive (e.g., relative humidity) and resistive (e.g., gas) sensors. Its sensitivity and dynamic range can be easily set through external passive components. Preliminary experimental measurements, which have characterized and validated this solution, have been conducted through a suitable prototype PCB fabricated with discrete commercial components. Then, the proposed interface has been also designed at transistor level, in a standard CMOS technology (AMS 0.35 um), developing a single-chip integrated circuit with low-voltage (1.8 V, single supply) low-power (about 350 μW) characteristics in a very small silicon area (lower than 0.6 mm²) which results to be suitable for sensor array configurations and portable applications. Further experimental results, achieved utilizing commercial sample resistors and capacitors to emulate sensor behavior, have shown a linear trend and a satisfactory accuracy in the evaluation of floating capacitive (in the range 10 pF–1 μF), grounded resistive (in the range 150 kΩ–1.5 MΩ) and floating resistive (in the range 10 MΩ–1 GΩ) variations, also when compared to other solutions presented in the literature. The satisfactory interface behavior has been also confirmed by the measurement of both relative humidity through the commercial sensor Honeywell HCH-1000 (capacitive) and carbon monoxide CO through the commercial air quality sensor FIGARO TGS-2600 (resistive).     

Internally compensated LDO regulator based on the cascoded FVF

In this paper, an internally compensated low dropout (LDO) voltage regulator based on the Flipped Voltage Follower (FVF) is proposed. By means of capacitive coupling and dynamic biasing, the transient response to both load and line variations is enhanced. The proposed circuit has been designed and fabricated in a standard 0.5 µm CMOS technology. Experimental results show that the proposed circuit features a line and a load regulation of 132.04 µV/V and 153.53 µV/mA, respectively. Moreover, the output voltage spikes are kept under 150 mV for a 2 V-to-5 V supply variation and for 1 mA-to-100 mA load variation, both in 1 µs.     

A systematic design approach for low-power 10-bit 100 MS/s pipelined ADC

A systematic design approach for low-power 10-bit, 100 MS/s pipelined analog-to-digital converter (ADC) is presented. At architectural level various per-stage-resolution are analyzed and most suitable architecture is selected for designing 10-bit, 100 MS/s pipeline ADC. At Circuit level a modified wide-bandwidth and high-gain two-stage operational transconductance amplifier (OTA) proposed in this work is used in track-and-hold amplifier (THA) and multiplying digital-to-analog converter (MDAC) sections, to reduce power consumption and thermal noise contribution by the ADC. The signal swing of the analog functional blocks (THA and MDAC sections) is allowed to exceed the supply voltage (1.8 V), which further increases the dynamic range of the circuit. Charge-sharing comparator is proposed in this work, which reduces the dynamic power dissipation and kickback noise of the comparator circuit. The bootstrap technique and bottom plate sampling technique is employed in THA and MDAC sections to reduce the nonlinearity error associated with the input signal resulting in a signal-to-noise-distortion ratio of 58.72/57.57 dB at 2 MHz/Nyquist frequency, respectively. The maximum differential nonlinearity (DNL) is +0.6167/−0.3151 LSB and the maximum integral nonlinearity (INL) is +0.4271/−0.4712 LSB. The dynamic range of the ADC is 58.72 dB for full-scale input signal at 2 MHz input frequency. The ADC consumes 52.6 mW at 100 MS/s sampling rate. The circuit is implemented using UMC-180 nm digital CMOS technology.     

Voltage-to-frequency converter with high sensitivity using all-MOS voltage window comparator

A high-sensitivity voltage-to-frequency converter (VFC) using an all-MOS voltage window comparator is presented in this work. The circuit is composed of one voltage-to-current converter, one charge and discharge circuit, and one all-MOS voltage window comparator. The input voltage is converted into a current which in turn triggers the charge and discharge circuit, where a built-in capacitor is driven. The voltage window comparator monitors the variated voltage on the capacitor and generate an oscillated output of which the vibration frequency is linearly dependent to the input voltage. In this way, the worst-case linear range of the output frequency of the proposed VFC is 0-55.40 MHz verified by simulations given a 0-0.9 V input range. The physical measurement of the proposed VFC shows a 0-52.95 MHz output frequency given a 0-0.9 V input range. The error in linearity is better than 8.5% while the power dissipation is merely 0.218 mW.     

Three-solenoid windings transformer baluns on CMOS-grade silicon substrate

Several novel on-chip three-solenoid windings transformer baluns were designed and fabricated using post-CMOS compatible concave-suspending micromachining process, which are applicable in the design of radio-frequency integrated circuits (RFICs). A generalized lumped-element circuit model (LECM) is developed to accurately characterize input and output characteristics of these three-port signal conversion devices, with the partial element equivalent circuit (PEEC) method implemented for capturing skin and proximity effects in them. Satisfactory agreements are obtained among the measured, simulated, and modeled S-parameters of the fabricated baluns over the frequency range of 500 MHz-10 GHz. Measurements show that these baluns exhibit less than 1 dB amplitude imbalance and less than 1° phase imbalance up to 6 GHz. Their power transfer and impedance matching are also examined in details.     

High slew rate current mode transconductance error amplifier for low quiescent current output-capacitorless CMOS LDO regulator

This paper presents a CMOS low quiescent current output-capacitorless low-dropout regulator (LDO) based on a high slew rate current mode transconductance amplifier (CTA) as error amplifier. Using local common-mode feedback (LCMFB) in the proposed CTA, the order of transfer characteristic of the circuit is increased. Therefore, the slew rate at the gate of pass transistor is enhanced. This improves the LDO load transient characteristic even at low quiescent current. The proposed LDO topology has been designed and post simulated in HSPICE in a 0.18 µm CMOS process to supply the load current between 0 and 100 mA. The dropout voltage of the LDO is set to 200 mV for 1.2–2 V input voltage. Post-layout simulation results reveal that the proposed LDO is stable without any internal compensation strategy and with on-chip output capacitor or lumped parasitic capacitances at the output node between 10 and 100 pF. The total quiescent current of the LDO including the current consumed by the reference buffer circuit is only 3.7 µA. A final benchmark comparison considering all relevant performance metrics is presented.     

Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist

A synthesis tool consisting of coefficient synthesis of architecture, circuit specifications synthesis, and CMOS operational-amplifier (op-amp) synthesis for discrete-time sigma-delta modulators (SDMs) is presented. In circuit specifications synthesis, several major circuit non-idealities are discussed and modeled. A precise performance prediction with a new design flow of specification synthesis is proposed. A hybrid design methodology composed of equation-based and simulation-based approaches for synthesizing fully differential two-stage and folded-cascode op-amps in technology is also presented. Experimental results show that the peak signal-to-noise and distortion ratio (PSNDR) of the fourth-order feed-forward (FF) SDM with an oversampling ratio (OSR) of 64 and a bandwidth of 20 KHz estimated by the proposed synthesis tool is 94.19 dB, and the result of the circuit simulation with folded-cascode op-amp is 93.03 dB. The estimated PSNDR of the third-order multiple-feedback (MF) SDM with an OSR of 32 and a bandwidth of 256 KHz is 59.52 dB, and the HSPICE simulation result is 55.39 dB.     

A novel ultra-high compliance, high output impedance low power very accurate high performance current mirror

In this paper a novel ultra-high compliance, low power, very accurate and high output impedance current mirror/source is proposed. Deliberately composed elements and a good combination (for a mutual auto control action) of negative and positive feedbacks in the proposed circuit made it unique in gathering ultra-high compliances, high output impedance and high accuracy ever demanded merits. The principle of operation of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by HSPICE simulation in TSMC 0.18 μm CMOS, BSIM3 and Level49 technology. Simulation results with 1 V power supply and 8 μA input current show an input and output minimum voltages of 0.058 and 0.055 V, respectively, which interestingly provide the highest yet reported compliances for current mirrors implemented by regular CMOS technology. Besides an input resistance of 13.3 Ω, an extremely high output resistance of 34.3 GΩ and −3 dB cutoff frequency of 210 MHz are achieved for the proposed circuit while it consumes only 42.5 μW and its current transfer error (at bias point) is the excellent value of 0.02%.