全差分可调频率四阶Chebyshev滤波器的实现

提出了一种新的全差分运算放大器,该运算放大器在具有电压共模负反馈的同时还具有电流共模负反馈,能较好地稳定其工作点。通过利用MOS管工作在线性区便能作可变电阻之用的特性,设计实现了基于R-MOSFET-C运放的全差分频率连续调节的四阶Chebyshev低通滤波器。该滤波器采用台湾联电(UMC)2层多晶硅、2层金属(2P2M)5V电源电压、0.5m CMOS工艺生产制造。其芯片面积大小为0.36mm~2,截止频率调节范围为20kHz到420kHz,输入信号频率在100kHz,2.5Vpp时的失真小于-65dB,功耗仅为16mW。     

全差分群时延可精确调节的四阶Bessel滤波器实现

采用全差分运算放大器、无源电阻以及用作可变电阻的MOS管设计实现了全差分R-MOSFET-C四阶Bessel有源低通滤波器,在所提出的电路中通过调节工作在线性区的MOS管有源电阻的阻值以抵消集成电路制造工艺过程中电阻阻值的一致性偏差,达到Bessel滤波器的群时延值得到精确设计的目的.该滤波器中所采用的全差分运算放大器不仅具备有电压共模负反馈,而且还具有电流共模负反馈,极有利于电路静态工作点的稳定.通过无源双端RLC原型低通滤波器导出的0.75μs群时延四阶Bessel滤波器,采用台湾联电(UMC)2层多晶硅、2层金属(2P2M)、5.0V电源电压、0.5μm CMOS工艺制造,在输入信号为100kHz、2.5Vpp时,其谐波失真(THD)值低于-65dB.     

A Low Distortion Wide Tuning Range CMOS Fully-Differential Fourth-Order Bessel Filter

A fully differential R-MOSFET-C fourth-order Bessel active low-pass filter employing passive resistors and current-steering MOS transistors as a variable resistor is proposed. The implementation relies on the tunability of the current-steering MOS transistors operating in the triode region which counteract the deviation of resistors in integrated circuit manufacturing technology in order that the group delay of the Bessel active filter can be realized accurately. A 0.75 us group delay 520 kHz frequency fourth-order Bessel lowpass filter based on a passive doubly terminated RLC prototype was designed and fabricated using 3.3 V power supply and 0.35 um CMOS technology. Chip test results demonstrate better than ?65 dB THD with @100 kHz, 1.65-Vpp signal, frequency tuning range of more than ten decades from 0.6 kHz to 550 kHz, chip area of 0.32 mm² and power consumption of 13.3 mW.     

Bulk-tuned Gm–C filter using current cancellation

A new approach for small transconductance (Gm) OTA designs, suitable for relatively low frequency filtering applications in the range of few kHz, is proposed. Small Gm values are achieved by a current cancellation technique, and are adjustable by bulk driving the MOS transistors of the input differential amplifier. The OTA design procedure takes into account Pelgrom׳s modeling of mismatch errors. A common-mode feedback control circuit based on floating gate common-mode voltage detector that shares the filter main capacitances is also presented. Experimental results obtained with a low-pass filter with tunable cutoff frequency implemented in a 0.35 μm CMOS process to verify the effectiveness of the design procedure have shown close agreement with the theory.     

Design of a low-distortion 22-kHz fifth-order Bessel filter

A linearity improvement technique employing passive resistors and current-steering MOS transistors as a variable resistance element is proposed to implement a low-distortion filter in CMOS technology. This proposed implementation relies on the linearity of the passive resistors and the tunability of the current-steering MOS transistors operating in the triode region to overcome the limited linearity performance in continuous-time electronically tunable filters. By using the existing systematic feedback loops in the active filters and placing the nonlinear elements inside the feedback, the distortion resulting from the nonlinear devices is greatly reduced by the filter loop gain. A 22-kHz fifth-order Bessel filter, its dynamic range optimized by applying Karmarkar's rescaling algorithm and self-tuned with a switched-capacitor reference resistor, demonstrates better than -90-dB THD with a 2-kHz, 4-V_pp signal in 5-V 2-μm CMOS     

Fully integrated active RC filters in MOS technology

A fully integrated continuous-time low-pass filter has been fabricated with CMOS technology. The device implements an active RC network using integrated capacitors and MOS transistors operated in the nonsaturation region as voltage-controlled resistors. The filter topology is fully balanced for good linearity and for good power supply rejection. The cutoff frequency is voltage adjustable around 3 kHz, allowing compensation for process and temperature variations. For 5-V power supplies a dynamic range of over 94 dB has been achieved.     

Micropower fully integrated CMOS readout interface for neural recording application

In this paper, we presented a micropower, small-size fully integrated CMOS readout interface for neural recording system. A crucial and important module of this system is the amplifier circuit with low-power low-noise. We describe a micropower low-noise readout circuit using an active feedback fully differential structure to reject the 1/f noise and large DC-offsets, the substrate-bias technology to further decrease the noise and power of the neural recording amplifier. Therefore, the neural amplifier with micropower low-noise and high input impedance is presented. The readout interface core, fully differential amplifier is implemented in 0.35-μm CMOS process, passes neural signals from 10 Hz to 9 kHz with an input-referred noise of 4.3 μV_rms. The power consumption of single amplifier is 5.6 μW while consuming 0.03 mm² of die area. The low cutoff frequencies of the circuit can adjusted from 10 Hz to 400 Hz, and the high cutoff frequencies form 4 kHz to 9 kHz.     

A 2-V/sub pp/ 80-200-MHz fourth-order continuous-time linear phase filter with automatic frequency tuning

A CMOS 80-200-MHz fourth-order continuous-time 0.05/spl deg/ equiripple linear phase filter with an automatic frequency tuning system is presented. An operational transconductance amplifier based on transistors operating in triode region is used and a circuit that combines common-mode feedback, common-mode feedforward, and adaptive bias is introduced. The chip was fabricated in a 0.35-/spl mu/m process; filter experimental results have shown a total harmonic distortion less than -44 dB for a 2-V/sub pp/ differential input with a single 2.3-V power supply. The group delay ripple is less than 4% for frequencies up to 1.5 f/sub c/. The frequency tuning error is below 5%.     

Low Voltage Micropower Log-Domain Filters

A design technique for low-voltage, micropower continuous-time filters implementing CMOS devices operating in weak inversion is presented. The basic building block is the CMOS log-domain integrator. The effects of the MOS device nonidealities on the integrator are investigated and verified by HSPICE simulations. A 5th-order Chebyshev lowpass ladder filter was designed and simulated. The filter operates with low supply voltage of 1.5 V to achieve a cutoff frequency tunable range of 100 Hz–100 kHz, and it has a power dissipation of 254 nW/pole at the cutoff frequency of 100 kHz. The filter was laid out using the 0.35-m mixed-mode polycide CMOS technology and occupies a die area of 0.04 mm² without the i/o pads     

Low power DDA-based instrumentation amplifier for neural recording applications in 65 nm CMOS

The low power instrumentation amplifier (IA) presented in this paper has been designed to be the front-end of an integrated neural recording system, in which common-mode rejection ratio (CMRR), input referred noise and power consumption are critical requirements. The proposed IA topology exploits a differential-difference amplifier (DDA) whose differential output current drives a fully differential, high-resistance, transimpedance stage, with an embedded common-mode feedback loop to increase the CMRR. This stage is followed by a differential-to-single-ended output amplifier. Low-power operation has been achieved by exploiting sub-threshold operation of MOS transistors and adopting a supply voltage of 1 V. Simulation results in a commercial 65 nm CMOS technology show a 1 Hz to 5 kHz bandwidth, a CMRR higher than 120 dB, an input referred noise of 8.1 μVrms and a power consumption of 1.12 μW.     

A 0.5-V, 2-nW, 55-dB DR,fourth-order bandpass filter using single branch biquads: An efficient design for FoM enhancement

A compact nano-power fourth-order bandpass filter operating from a 0.5 V supply, with an adjustable center frequency ranging from 125 Hz to 16 kHz, is presented. The filter is constituted from cascadable second-order circuit cells that are realized by a network of three transistors and two capacitors comprising only one branch of bias current. The measurement results of the filter fabricated in a 0.18-μm CMOS IC process indicate that, for a 1 kHz center frequency, a dynamic range of 55 dB is obtained from 2 nW power consumption. These results lead to best figure of merit achieved when compared to other existing designs to date.     

Design of low-voltage and low-power fully integrated filter based on log-domain current-mode integrator

In this paper a novel log-domain current-mode integrator based on MOS transistors in subthreshold is proposed. The integrator's time-constant is tunable by varying a reference bias current. By use of the integrator, a fifth-order Chebyshev lowpass filter with 0.1dB ripples is designed. The simulation results demonstrate that the proposed filter has such advantages as low power supply(1.5V), very low power dissipation (μW level), nearly ideal frequency response, very small sensitivity to components in passband, and adjustable cut-off frequency over a wide range. The circuit is composed of NMOS transistors and grounded capacitors which make it suitable for fully integrated circuit implementation.     

A low-transconductance OTA with improved linearity suitable for low-frequency Gm-C filters

A fully differential operational transconductance amplifier is presented in this paper with enhanced linearity and low transconductance, suitable for low-frequency Gm-C filters. This paper also proposes a new common-mode feedback scheme that presents low sensitivity to large differential voltage swings at the OTA outputs. The proposed OTA was employed in the design of a fully-integrated Gm-C low-pass filter with a cutoff frequency of 30 kHz. The Gm-C filter was fabricated in a 0.35 μm CMOS technology and presented a THD at the output less than 1% for input signals with differential amplitudes up to 3.2 V.     

Micropower active-RC channel filter for a zero-IF Bluetooth receiver

A fourth-order low-pass channel filter for a zero-IF Bluetooth receiver is presented. It employs two cascaded multiple feedback biquads and active resistors made by quasi-floating gate MOS transistors in triode region for highly linear continuous tuning. Power consumption is strongly reduced using a gain-enhanced class-AB single-stage opamp together with a filter topology that only requires a single opamp for each biquad. The filter has been fabricated in a 0.18 μm CMOS technology and consumes 290 μW from a 1.2 V supply.     

A Switched Opamp-Based Bandpass Filter: Design and Implementation in a 0.35 μm CMOS Technology

A fully differential SC bandpass filter (central frequency, 58 kHz; Q = 15; and voltage gain, 8) based on the switched-opamp approach is designed and implemented in this work. The filter operates from a single 1 V supply voltage and is realized in a 0.35 m CMOS technology. It has been characterized with a sampling frequency of 1 MHz and its power consumption is about 230 W. As a main internal filter component, an appropiate switched opamp was also designed. Its common-mode feedback circuit was implemented by using an error amplifier and sampling of the output common-mode voltage is carried out by applying a DC offset to level shift the common-mode sample. It provides an accurate common-mode output for a wide temperature and supply voltage ranges.     

高线性度低功耗的4阶开关电容低通滤波器

介绍了一种应用于传感器的高线性度低功耗全差分4阶贝塞尔开关电容滤波器.该滤波器的运算放大器为输出AB类运算放大器,通过AB类运算放大器以及开关电容共模反馈的设计,降低了功耗.在运算放大器中设计了线性跨导环,并通过对电路的拓扑结构进行优化,提高了滤波器的线性度.测试结果表明,在采样频率为1 MHz下,该滤波器的截止频率为10.05 kHz.在输入信号频率为1 kHz,输出信号的总谐波失真(THD)为-89 dB(摆幅为2 V),功耗为5.54 mW,达到了高线性度、低功耗的设计要求.     

截止频率精确可调跨导电容滤波器实现

提出了一种新的利用开关电容技术调节偏置电流值大小的电路,应用该电路可以精确调节跨导运放Gm值的大小。采用既具有电压共模负反馈(CMFB)电路, 又同时具有工作在线性区的MOS管作源极反馈有源电阻, 实现其良好线性度的跨导运放。设计了三阶椭圆函数低通滤波器,并实现其频率的精确可调。应用台积电(TSMC)2层多晶硅,4层金属(2P4M),3.3V电源电压,0.35m CMOS工艺Spice model仿真得到的频响曲线与理想情况十分接近。     

A ±3.07% frequency variation clock generator implemented using HV CMOS process

In this paper, we propose a clock generator with a feedback TPC (temperature and process compensation) bias circuit fabricated by a high-voltage (HV) CMOS process. Particularly, the feedback TPC bias is composed of an OPA, MOS transistors and resistors, where large BJT devices are no longer needed such that it is easy to be integrated on chip with small area overhead. The feedback TPC bias circuit, including a MOS transistor, four resistors, and a differential amplifier, is used to provide temperature and process compensation. The proposed circuit design is implemented using 0.25 μm 60 V BCD process. Measurement of 10 dies in the range of 0 °C to 100 °C is carried out to verify that the worst frequency drifting error is ±3.07%.     

A fully balanced pseudo-differential OTA with common-mode feedforward and inherent common-mode feedback detector

A pseudo-differential fully balanced fully symmetric CMOS operational transconductance amplifier (OTA) architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. The OTA achieves a third harmonic distortion of -43 dB for 900 mV/sub pp/ at 30 MHz. The OTA, fabricated in 0.5-/spl mu/m CMOS process, is used to design a 100-MHz fourth-order linear phase filter. The measured filter's group delay ripple is 3% for frequencies up to 100 MHz, and the measured dynamic range is 45 dB for a total harmonic distortion of -46 dB. The filter consumes 42.9 mW per complex pole pair while operating from a /spl plusmn/1.65-V power supply.     

High-performance active polyphase filter design for digital TV tuner

This paper presents the polyphase filter design for the tuner of DTV front-end system. The polyphase filter is designed with an active circuit to improve the chip performance. Most of passive capacitor and resistor components are replaced with MOS transistors. The proposed method not only can reduce the chip area but also gain the signal level. For the prototyping implementation, the current channel bands in Taiwan are referred, which the frequency range is from 530 to 602 MHz for DTV programs. In experiments, the polyphase filter can achieve 85 dB for the image rejection in the center frequency. The main signal can be gained about 2-5 dB without using extra amplifier. The chip size is about 0.09 mm², and the average power dissipation is about 15 mW, when the chip technology employed TSMC 0.35 μm CMOS process. The proposed chip outperforms with less area and higher gain.