Gate Grounded NMOS器件的ESD性能分析

文章基于0.18μm CMOS工艺制程的1.8V NMOS器件,从工艺的角度并用TLP测试系统对栅极接地的NMOS(GGNMOS)ESD器件进行比较分析.介绍了SAB和ESD注入对GGNMOS的性能影响,影响GGNMOS ESD性能的瓶颈是均匀开启性.在GGNMOS版图等其他特征参数最优的前提下,采用SAB能改善其均匀...     

Analysis of lateral DMOS power devices under ESD stress conditions

The physical mechanisms specific for 40 V LDMOS power transistors under ESD stress (gate grounded/coupled) are investigated in detail by transmission line pulse (TLP) measurements, human body model (HBM) testing, emission microscopy (EMMI) experiments, and two-dimensional (2-D) device simulations. Inhomogeneous triggering caused by device topology as well as the sustained nonhomogeneous current flow due to the unusual electrical behavior are accurately analyzed in single- and multi-finger devices     

集成电路抗ESD设计中的TLP测试技术

介绍了一种研究器件和电路结构在ESD期间新的特性测试方法——TLP法，该方法不仅可替代HBM测试，还能帮助电路设计师详细地分析器件和结构在ESD过程中的运行机制，有目的地进行器件ESD保护电路的设计，提高器件的抗ESD水平。     

TLP应力下深亚微米GGNMOSFET特性的仿真

对TLP(传输线脉冲)应力下深亚微米GGNMOS器件的特性和失效机理进行了仿真研究. 分析表明，在TLP应力下，栅串接电阻减小了保护结构漏端的峰值电压；栅漏交迭区电容的存在使得脉冲上升沿加强了栅漏交叠区的电场，栅氧化层电场随着TLP应力的上升沿减小而不断增大，这会导致栅氧化层的提前击穿. 仿真显示，栅漏交迭区的电容和栅串接电阻对GGNMOS保护器件的开启特性和ESD耐压的影响是巨大的. 该工作为以后的TLP测试和标准化提供了依据和参考.     

栅长对SOI NMOS器件ESD特性的影响

采用TLP测试的方式,研究了不同栅长对栅接地SOI NMOS器件ESD(Electrostatic discharge,静电放电)特性的影响,结果发现栅长越大,维持电压VH越大,ESD二次击穿电流It2越大;其原因可能与薄硅层中的热分布有关。     

Design of GGNMOS ESD protection device for radiation-hardened 0.18 μm CMOS process

In this paper, the ESD discharge capability of GGNMOS (gate grounded NMOS) device in the radiation-hardened 0.18 μm bulk silicon CMOS process (Rad-Hard by Process: RHBP) is optimized by layout and ion implantation design. The effects of gate length, DCGS and ESD ion implantation of GGNMOS on discharge current density and lattice temperature are studied by TCAD and device simulation. The size of DCGS, multi finger number and single finger width of ESD verification structures are designed, and the discharge capacity and efficiency of GGNMOS devices in ESD are characterized by TLP test technology. Finally, the optimized GGNMOS is verified on the DSP circuit, and its ESD performance is over 3500 V in HBM mode.     

Design of Gate‐Ground‐NMOS‐Based ESD Protection Circuits with Low Trigger Voltage,Low Leakage Current,and Fast Turn‐On

In this paper, electrostatic discharge (ESD) protection circuits with an advanced substrate‐triggered NMOS and a gate‐substrate‐triggered NMOS are proposed to provide low trigger voltage, low leakage current, and fast turn‐on speed. The proposed ESD protection devices are designed using 0.13 μm CMOS technology. The experimental results show that the proposed substrate‐triggered NMOS using a bipolar transistor has a low trigger voltage of 5.98 V and a fast turn‐on time of 37 ns. The proposed gate‐substrate‐triggered NMOS has a lower trigger voltage of 5.35 V and low leakage current of 80 pA.     

Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology

The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip electro-static-discharge (ESD) protection. The device has a small area in requirement robustness in comparison to gate-grounded NMOS (ggNMOS). The proposed ESD protection device is designed in 0.25 μm CMOS technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 3.8 V and a high trigger current of greater than 120 mA. The robustness has measured to HBM 8 kV (HBM: human body model) and MM 400 V (MM: machine model). The proposed device has a high-level It2 of 52 mA/μm approximately.     

Characterization Analysis of UDSM LVTSCR Under TLP Stress

The characteristics of a low-voltage triggering silicon-controlled rectifier (LVTSCR) under a transmission line pulse (TLP) and the characteristics of high frequency are analyzed. The research results show that the anode series resistance has a significant effect on the key points of the snapback curve. The device characteristics can fit the requirements of a electrostatic discharge (ESD) design window by adjusting the anode series resistance. Furthermore, the set-up time of the ESD has an influence on the turn-on voltage of the LVTSCR. A steep rising edge will cause the turn-on voltage to increase. The parasitic capacitance of the device for different voltage biases and frequencies determines the capacitive impedance, and its accuracy calculation is very important to the ESD design of high frequency circuits. Our research results provide a theoretical basis for the design of an ultra-deep sub-micron (UDSM) LVTSCR structure under ESD stress and the improvement of TLP test technology.     

静电放电人体模型测试标准EIA/JEDEC中的问题研究

通过具体的实例说明目前的静电放电（Electrostatic Discharge,ESD）人体模型测试标准EIA／JEDEC尚存在一些需要完善的问题。目前的标准EIA／JEDEC中缺少对起始测试电压的规定,导致有些测试直接从千伏（kV）量级的高压开始进行,造成一些设计不良的ESD防护器件在低压发生失效的状况可能被漏检的后果。本文研究对象为一个漏端带N阱镇流电阻（Nwell-ballast）的GGNMOS（Gate-Grounded NMOS）型ESD防护结构。用Zapmaster对它做人体模型（Human Body Model,HBM）测试,发现从1Kv起测时,能够通过8Kv的高压测试;而从50V起测时,却无法通过350V。TLP测试分析的结果显示此现象确实存在。本文详细剖析了该现象产生的机理,并采用OBIRCH失效分析技术对其进行了佐证。因该问题具有潜在的普遍性,因此提出了对目前业界广泛采用的EIA／JEDEC测试标准进行补充完善的建议。     

Different Failure signatures of multiple TLP and HBM Stresses in an ESD robust protection structure

The failure signatures of a grounded-base NPN bipolar ESD protection under multiple TLP and HBM stresses are analyzed. For this particular device having a graded collector region, multiple TLP or HBM stresses result in different types of defects. OBIC techniques and TCAD simulations are used to thoroughly analyze the involved physical mechanisms.     

ESD on GaN-based LEDs: An analysis based on dynamic electroluminescence measurements and current waveforms

This work presents an extensive study on the effects of Electrostatic Discharges (ESD) on state-of-the-art GaN based LEDs, based on optical and electrical measurements carried out during the ESD events. ESD events were simulated through a Transmission Line Pulser (TLP) which generates voltage pulses with a duration of 100 ns and increasing amplitude: during each pulse, spatially-resolved electroluminescence measurements were carried out through an high speed EMCCD camera. These measurements allowed to identify the chip region where the discharge is localized and the change in the damaged area induced by consecutive ESD events. Also the current and voltage waveforms at the LED terminal were monitored during the tests; this analysis provided important information about modifications the impedance of the devices. The analysis was carried out on different types of commercially available low-power GaN-based LEDs with several differences in the manufacturing technology. Thanks to these tests we have identified two different failure behaviours during a destructive ESD event, clearly related to the different defects in the semiconductor lattice and to structure of the chip.     

用于电源线间ESD保护的新型高维持电压的SCR-LDMOS器件

The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD(electro-static discharge) clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.     

一种新的用于RFIC ESD保护的双槽LVTSCR

低压触发硅控整流器件（Low-Voltage Triggering Silicon-controlled Rectifier,LVTSCR）由于具有高的放电效率和低的寄生参数,在ESD防护方面存着诸多优势,尤其对于深亚微米集成电路和高频应用领域。本文对影响LVTSCR回退（snapback）特性曲线的几个重要因素和它的配置方式作了详细的分析和评价,这些参数包括阳极串联电阻、栅电压以及器件的结构和尺寸。并且提出了一种双槽LVTSCR结构,该结构可以获得较高且容易调节的维持电压,从而使其snapback特性很好地符合ESD设计窗口规则。论文的最后讨论了RFIC中采用LVTSCR的ESD保护策略。     

Overstress and electrostatic discharge in CMOS and BCD integrated circuits

The ESD qualification of the new technologies is obtained by testing different device structures an comparing the ESD robustness evaluated by means of different testing methods (HBM, MM, CDM and TLP). The influence of the layout parameters on the ESD robustness must also be characterized. In this paper we will present data concerning the ESD robustness of both 0.35 μm CMOS and 0.6 μm smart power (BCD5) protection structures. A study of the influence of layout parameters on the ESD robustness with different test methods (HBM, CDM and TLP) will be given. Failure analysis by means of electrical characterization, Emission Microscopy and SEM inspection will also been presented.     

ESD sensitivity investigation on a wide range of high density embedded capacitors

This work presents some results from electrical (TDDB, TLP, HBM and MM) measurements and ESD calculations/simulations on passive components such as capacitors. In a SIP context, the ESD sensitivity of innovative 3D capacitors is studied. A method to predict the failure threshold of a wide range of capacitor values under ESD events is presented and validated by measurement on silicon. This method consists of using the basic equation of the charge conservation for capacitors in parallel that is adapted to the model of the ESD event.     

TLP和VFTLP应力下高压LDMOS的触发特性研究

本文通过TCAD软件－Sentaurus Device工具, 基于文献[1]所提出的一套物理宏模型进行仿真,研究了高压LDMOS功率器件（击穿电压大于160伏）在传输线脉冲和快速传输线脉冲应力下的静电放电（ESD）触发物理机制,发现在快速传输线脉冲应力下,高压LDMOS的触发电压有明显的提高,这一现象和低压普通静电放电保护器件（如NMOS器件和SCR器件）有明显的差异。本文详细分析了触发电压的上升现象和寄生电容的关系,并且用一个简单的等效电路原理图分析了上述现象。最后,本文提出了一种能够减轻触发电压上升这一现象的改进结构,并且得到了测试结果的验证。     

Evaluation of the ESD performance of local protections based on SCR or bi-SCR with dynamic or static trigger circuit in 32 nm

The reliability of electronic devices against electrostatic discharge stresses is still a severe challenge, particularly for deep sub-micron technologies such as the CMOS 32 nm in this work. The paper presents a comparison between four ESD protections in CMOS 32 nm node. Dynamic and static triggering circuits are investigated and SCR and bi-SCR are compared. Each structure is characterized through TLP and protects up to 2 kV HBM stresses.     

Electrical overstress due to ESD induced displacement currents

In this paper a new failure mode is introduced, which is related to the large dV/dt of ESD pulses. It was observed after +4 kV HBM stress for a 90V-BCD technology device and resulted in a gate oxide defect of a low voltage PMOS transistor, which was hidden deeper in the IC's circuitry. The underlying failure mechanisms are discussed based on experimental and simulational findings and measures for early identification and protection of potentially sensible devices are proposed.     

Design of fabrication of ESD protection circuit with high holding voltage for power IC

In this paper, A newly Silicon Controlled Rectifier (SCR)-based Electric Static Discharge (ESD) protection circuit is proposed. The proposed circuit has the latch-up immunity in normal operating conditions with the high holding voltage by inserting the floating regions. To verify the electrical characteristics, a Technology Computer Aided Design (TCAD) simulation is performed by setting each of variables: D1, D2, D3, and D4. The results of the simulation show that the proposed protection circuit has the holding voltage 5 V higher than the conventional circuits and has the same level of robustness properties as the existing SCR. In addition, the proposed circuit is fabricated through a 0.18 μm Bipolar-CMOS-DMOS process. The electrical characteristics are confirmed by measuring Transmission Line Pulse, and the robustness properties are measured through Human Body Model (HBM) and Machine Model (MM). The holding voltage is about 20 V, which has the increases above 18 V or more compared to the conventional SCR. Therefore, the proposed circuit is proved to have the better ESD protection performance than HBM 8 kV and MM 800 V higher than HBM 2 kV and MM 200 V, the commercial standard.