Improving reliability of beveled power semiconductor devices passivated by SIPOS

Semi-insulating polycrystalline silicon films were prepared by direct current glow discharge on bevelled power semiconductor devices. Devices passivated by polyimide were also fabricated for comparison studies. The reverse current–voltage characteristic was studied at room temperature and high junction temperature. The differences arose from the remnant unbalance charges in the passivants as well as the varying dielectric strengths. Passivation materials applied to the beveled devices played a key role in achieving the targeted voltage. Results obtained indicated that the performance of power semiconductor devices passivated by SIPOS were superior to those passivated by polyimide, and SIPOS based process was effective and expected to enhance the reliability and yield.     

Interpretation of current flow in photodiode structures using laser beam-induced current for characterization and diagnostics

This paper presents an interpretation of the physical mechanisms involved in the generation of laser beam-induced current (LBIC) in semiconductor p-n junction diodes. LBIC is a nondestructive semiconductor characterization technique that has been used in a qualitative manner for a number of years and is especially useful for examining individual photodiodes within large two-dimensional arrays of devices. The main thrust of this work is the analysis of LBIC in terms of nonzero steady-state circulatory current flow within the device and, hence, the interpretation of LBIC line profiles to diagnose the patterns of current flow within the structure. This provides an important basis for future studies seeking to relate LBIC to indicators of p-n junction performance and integrity such as dark current components and reverse bias saturation current. In particular, this paper examines the ideal cases of a single isolated p-n junction diode structure, and also considers an array of such devices in close proximity to each other. Modifications to the idealized theory that are required to account for localized junction leakage and surface recombination are presented, and the effect of Schottky contacts is discussed. Numerical simulations based on the HgCdTe family of semiconductors are presented to support the theory.     

晶体硅太阳电池逆电流的研究

从半导体器件物理出发,分析了晶体硅太阳电池逆电流产生的原因,研究了逆电流对晶体硅太阳电池性能的影响;通过遮挡实验研究了晶体硅太阳电池逆电流对组件可靠性的影响,探讨了逆电流和热斑保护间的关系,首次提出了逆电流的控制标准。     

Redox‐Induced Asymmetric Electrical Characteristics of Ferrocene‐Alkanethiolate Molecular Devices on Rigid and Flexible Substrates

The electrical properties of ferrocene‐alkanethiolate self‐assembled monolayers (SAMs) on a high yield solid‐state device structure are investigated. The devices are fabricated using a conductive polymer interlayer between the top electrode and the SAM on both silicon‐based rigid substrates and plastic‐based flexible substrates. Asymmetric electrical transport characteristics that originate from the ferrocene moieties are observed. In particular, a distinctive temperature dependence of the current (i.e., a decrease in current density as temperature increases) at a large reverse bias, which is associated with the redox reaction of ferrocene groups in the molecular junction, is found. It is further demonstrated that the molecular devices can function on flexible substrates under various mechanical stress configurations with consistent electrical characteristics. This study enhances the understanding of asymmetric molecules and may lead to the development of functional molecular electronic devices on both rigid and flexible substrates.     

Single-shot thermal energy mapping of semiconductor devices with the nanosecond resolution using holographic interferometry

A novel two-dimensional backside optical imaging method for thermal energy mapping inside semiconductor devices is presented. The method is based on holographic interferometry from the device backside and uses the thermo-optical effect. An image of the local thermal energy is obtained with 5-ns time resolution using a single stress pulse. The technique allows a unique recording of the internal device behavior. The method is demonstrated analyzing the nonrepetitive thermal and current flow dynamics in smart power electrostatic discharge (ESD) protection devices. A spreading of the current during the stress pulse is observed and explained by the effect of the negative temperature dependence of the impact ionization coefficient.     

Effect on ion implanted germanium profile on the characteristics of Si/sub 1-x/Ge/sub x//Si heterojunction bipolar transistors

An optimum profile for Ge ion implantation in SiGe/Si heterojunction bipolar transistors is determined by using a two-dimensional simulator code for advanced semiconductor devices. The simulation code is based on a two-dimensional drift-diffusion model for heterostructure degenerate semiconductors with nonparabolicity included in the energy band structure. The model allows accurate simulations of carrier transport in short base devices. The simulation results indicate that for high current gain the Ge profile maximum must be close to the base-collector junction, and that the unavoidable tail of the implanted germanium in the collector region does not deteriorate the gain.<>     

Erosion defect formation in Ni-gate AlGaN/GaN high electron mobility transistors

High electron mobility transistors based on Aluminum Gallium Nitride/Gallium Nitride heterostructures are poised to become the technology of choice for a wide variety of high frequency and high power applications. Their reliability in the field, particularly the reliability of the gate electrode under high reverse bias, remains an ongoing concern, however. Rapid increases in gate leakage current have been observed in devices which have undergone off-state stressing. Scanning Electron Microscopy, scanning probe microscopy, and Transmission Electron Microscopy have been used to evaluate physical changes to the structure of Ni-gated devices as the gate leakage current begins its initial increase. This evaluation indicates the formation of an interfacial defect similar to erosion under the gate observed by other authors. Defect formation appears to be dependent upon electrical field as well as temperature. Transmission Electron Microscopy has been used to demonstrate that a chemical change to the interfacial oxynitride layer present between the semiconductor and gate metal appears to occur during the formation of this defect. The interfacial layer under the gate contact transitions from a mixed oxynitride comprised of gallium and aluminum to an aluminum oxide.     

Power thyristor rating practices

The power thyristor is the most important semicoductor device used in the control of electric power. An explanation of thyristor ratings and rating presentation is required for the complete understanding and successful application of these devices. This paper not only explains the meaning of thyristor temperature, voltage, current, and gate ratings but also presents insights into how these ratings are developed. Both the semiconductor controlled rectifier (SCR), which is properly called a reverse blocking triode thyristor, and the bidirectional thyristor rating methods are discussed. SCR rating are further divided into those applying to phase control applications at power frequencies and those applying to high repetition rate inverter and pulse current appications.     

Mathematical Model of Fiber Optic Temperature Sensor Based on Optic Absorption and Experiment Testing

On the basis of analysis on the temperature monitoring methods for high voltage devices, a new type of fiber optic sensor structure with reference channel is given.And the operation principle of fiber optic sensor is analysed at large based on the absorption of semiconductor chip.The mathematical model of both devices and the whole system are also given.It is proved by the experiment that this mathematical model is reliable.     

Optimized numerical models for semiconductor devices: Part I

This article presents some results from a study concerned with the trade-off between efficiency of numerical computation and accuracy of numerical models for semiconductor devices. The approach taken in this study was to use nonuniform grids in the finite difference equations approximating the semiconductor partial differential equations. A constrained minimization problem was formulated which analytically optimizes the numerical models. Several performance functions were found useful in optimizing the numerical models; the one presented here matches computed and "exact" terminal current responses. An example is presented to illustrate the results obtained with this performance function. The example model optimization shows that the optimized grids should have their greatest density in the space-charge region near the junction. An interesting side result is that when one performance function is optimized, apparently other desired features are optimized for numerical models for semiconductor devices. The Fletcher-Powell optimization algorithm was used with an adjoint gradient algorithm specifically developed for this study, without which the use of nonuniform grids would not have been practical.     

Electro-thermal analysis and optimization of edge termination of power diode supported by 2D numerical modeling and simulation

High reliability and performance of power semiconductor devices depend on an optimized design based on a good understanding of their electro-thermal behavior and of the influence of parasitic components on their operation. This leads to the need for electro-thermal 2/3-D numerical modeling and simulation in power electronics as an efficient tool for analysis and optimization of device structure design and identification of critical regions. In this paper we present an analysis and geometry optimization of a high power pin diode structure supported by advanced 2-D mixed mode electro-thermal device and circuit simulation. Lowering of the operation temperature by better power management and heat dissipation due to an optimized structure design will allow withstanding higher current pulses and suppressing the damage of the analyzed structure by thermal breakdown.     

聚合物发光器件中输运特性的模拟分析

对聚合物发光二极管 I- V特性的测量发现 ,被测器件内存在着类似于某些无机器件中的负阻现象和“迟滞回线”状场致漂移的伏安特性 .模拟分析表明 ,一种反向势垒的存在及其击穿 ,应是引起负阻现象的原因 .缺陷态的存在及其电荷填充的变化 ,是导致 I- V特性曲线随偏压扫描方向变化的主要原因 .而低场下的接触性能决定着发光二级管载流子的输运性质 :若为非欧姆接触 ,则 I- V曲线可用 F- N隧穿模型来描述 ;若为欧姆接触 ,则应用陷阱电荷限制电流 (TCL)模型来描述     

基于Matlab对Spice二极管特性受温度影响的研究

为了对Spice程序下的二极管模型的伏安特性和等效电容受温度变化的影响进行研究,在此以软件Matlab的仿真环境为基础,Spice二极管物理模型D1N4002为研究对象,在仿真软件Matlab中编写程序代码,建立了二极管模型D1N4002的伏安特性和等效电容的函数模型,绘制出不同温度下二极管伏安特性和等效电容的曲线,并结合仿真曲线对由温度变化产生的影响进行分析,得出了温度对二板管模型在反向击穿和正向导通状态下的伏安特性及等效电容有明显的影响这一结论。该研究方法以一个新颖的视角,运用Matlab构造特性函数,以温度为变量,研究了Spice二极管模型的特性,同时也为其他更加复杂的半导体器件特性的研究打下了基础。     

Optimized numerical models for semiconductor devices: Part II

This article presents some results from a study that was concerned with the trade-off between efficiency of numerical computation and accuracy of numerical models for semiconductor devices. The approach taken in this study was to use optimized nonuniform grids in the finite difference equations approximating the semiconductor partial differential equations. This paper presents a second choice of performance function that allows a minimization of the truncation error made in the difference approximation to the continuous equations. The truncation error approach is more elegant and more useful than the terminal current approach reported in Part I [7]. An example is presented to illustrate the results obtained with the truncation error performance function. A significant side result is that when the truncation error is minimized, then all other desired features are optimized for the numerical models for semiconductor devices.     

DC thermal model of semiconductor device produces current filaments as stable current distributions

How current filaments arise in semiconductor devices can be studied with the aid of a simple two-dimensional thermal model. This dc model generates temperature and current distributions across the semiconductor chip. To use the model one must be able to prescribe the temperature dependence of the dc conductance in the chip from prior knowledge of the conduction mechanism. This model produces current filaments as stable current distributions. Moreover it demonstrates that current filaments will form in avalanche diodes at high power levels even if the chips are defect-free. The key to filament formation in a semiconductor device is an increase of the dc conductance with temperature at some operating point. In avalanche conduction, when the diode bulk leakage current increases faster than the avalanche current multiplication factor decreases with temperature, the avalanche conductance begins to rise. When this happens, a current filament forms raising the temperature locally to more than 1600°C, according to the model, and results in diode burnout. This mechanism is believed to be involved also in RF-induced burnout of avalanche diodes and in the burnout of other semiconductor devices.     

Design and performance of deflected-beam electron-bombarded semiconductor amplifiers

This paper describes the design and testing of developmental electron-bombarded semiconductor (EBS) devices as pulsed dc and pulsed RF amplifiers. These devices employ a well-focused electron beam deflected in proportion to the input signal to control the current in a semiconductor target. Both Class A and Class B amplifier configurations are described, with a prediction of their relative efficiency and distortion properties. The deflection sensitivity of simple deflection plates and traveling-wave deflection systems is considered. Experimental results are given for amplifiers with planar passivated semiconductor targets and traveling-wave deflection systems operated as video-pulsed amplifiers and Class B RF amplifiers. Performance of nanosecond-risetime videopulse amplifiers with peak output power greater than 700 W and efficiency in excess of 80 percent is described. Test data are presented from RF amplifiers with efficiency performance of 60 percent. A comparison of theoretical and experimental results is given based upon a computer simulation of semiconductor target performance. Preliminary life test data showing stabilized diode performance with negligible reverse breakdown voltage deterioration are presented.     

Electrical characteristics and threshold switching in amorphous semiconductors

The relative role of thermal and electronic effects on the threshold switching mechanism in the amorphous semiconductor Ge₁₇Te₇₉Sb₂S₂, has been investigated, using virgin sandwich type devices.Evidence is presented in support of a critical field bulk switching mechanism, in which secondary heating effects play a role only because of the variation of the critical switching field with temperature. Switching delay time measurements are interpreted in terms of adiabatic and steady state heating, for times shorter and longer, respectively, than the thermal time constant of the device. An isothermal switching field is calculated by correcting the measured switching field for the estimated change in temperature of the device prior to switching. Switching voltage measurements were made with pulse widths from 1 nsec. to d.c. In this range the isothermal switching field is independent of the pulse width. The d.c. switching field is shown to be a function of the thermal constraints of the device structure. In contrast, the isothermal switching field is a fundamental material parameter. It is established, from short pulse (1·5 nsec) measurements of the current voltage characteristic that the critical switching field marks the onset of a previously unreported high field conduction region. This characteristic, in the vicinity of the switching field, is similar to that of a reverse biased diode in the vicinity of its breakdown voltage.     

Activation energy determination from low-temperature CV dispersion[semiconductor devices]

The response of semiconductor devices at low temperatures to changes in the voltage across the depletion region is limited by the dielectric relaxation time of the majority carriers in the bulk region. This results in a dispersion of the C-V curves at low temperatures. In this paper, we report a study of the dispersion seen in the accumulation and depletion regions of the C-V curve in n- and p-channel MOS transistors as well as in reverse biased one-sided abrupt junctions. From the admittance measured as a function of temperature and frequency, the dopant energy level is determined. The values of the activation energy measured using the diodes agree well with the corresponding values obtained using MOS devices     

Tunnel diode reverse characteristics at different temperatures

The tunnel diode characteristics in the reverse direction at low and high temperatures is investigated applying a simplified model of the heavily doped semiconductor junction. In this model momentum is conserved and a calculation of the tunneling probability is made on account of field and image-charge effects on the potential energy barrier.The energy gap of heavily doped germanium is plotted as a function of the impurity concentration at 78 and 300 K. It is suggested that the tunneling current increases with concentration for a given temperature, and with temperature for a given concentration.Our theoretical results are in good agreement with the experiments. The breakdown voltage decreases with temperature for a given reverse current. Finally it is suggested that the tunneling current in the Kane's theory is much larger compared to that given in the present theory and experiments.     

Some reasons for nonsaturation of reverse current in junction diodes

The saturation of reverse current for reverse voltages more than a few tenths of a volt, which is predicted for semiconductor junctions by the simple theory, actually never occurs. Effects such as surface conduction and generation of minority carriers in the space-charge region have been used to explain the failure of the current to saturate. The present discussion considers some other possibilities. For nonplanar junctions, increase in the effective junction area with increasing reverse bias may be important. For any junction, increasing bias may move the effective junction surface to places where the semiconductor has, either actually or effectively, different properties. Some examples of these possibilities, chosen to be as closely related to practical devices as possible, are given.