A 1.8-GHz injection-locked quadrature CMOS VCO with low phase noise and high phase accuracy

Injection-locked quadrature voltage-controlled oscillators are introduced in this paper as high accuracy, low phase noise, and low-power I and Q generators. A master voltage-controlled oscillator (VCO), running at twice the output frequency, locks two coupled VCOs. The former determines phase noise while the latter sets phase accuracy, thus, breaking the tradeoff between the two parameters, the main limit of free running coupled VCOs, recently proposed in the framework of highly integrated solutions. The proposed design has been tailored to DCS 1800 and prototypes have been fabricated in a 0.18-/spl mu/m CMOS technology. Experiments show a phase noise of -127 dBc/Hz and -139 dBc/Hz at 600 kHz and 3 MHz, respectively, while consuming 10 mA from 1.8 V supply. A 185-dB state-of-the-art phase noise figure of merit results. Accuracy between output signals is determined by means of image band rejection (IBR) measurements on a purposely developed single-side-band upconversion mixer. Minimum IBR among 20 samples is as large as 46 dB.     

On the amplitude and phase errors of quadrature LC-tank CMOS oscillators

An analytic approach for the estimation of the phase and amplitude imbalances caused by component mismatches and parasitic magnetic fields in two popular quadrature LC oscillators is presented. Very simple and closed-form equations are derived, proving that, although the two topologies share the same small signal circuit, they display very different sensitivities to the mentioned sources of imbalance. Moreover, it is shown that parasitic inductors coupling, overlooked up to date, plays a key role ultimately limiting the achievable phase accuracy. The theoretical results are verified through extensive simulations and measurements on a 1.7-GHz quadrature oscillator and frequency up-converter implemented in a 0.18-/spl mu/m CMOS process.     

Analysis and Design of a Double-Quadrature CMOS VCO for Subharmonic Mixing at Ka-Band

In this paper, we analyze the potentials of a four-phase 14-GHz CMOS voltage-controlled oscillator, tailored to a sub-harmonic receiver, for signal processing at Ka-band. When mild phase accuracies between in-phase and quadrature down-converted signals are required, the four-phase oscillator displays roughly the same phase noise figure-of-merit as quadrature oscillator counterparts. However, the operation at half-frequency leads to an improved performance due to a higher quality factor of the tuning varactors, and because the local oscillator circuitry and signal path run at different frequencies, relaxing coupling issues. A detailed time-variant analysis of phase noise in multiphase oscillators is introduced and validated by both simulations and experiments. Prototypes realized in a 65-nm technology occupy an active area of 0.5 mm² and show the following performances: a 26% frequency tuning range (from 12.2 to 15.9 GHz), maximum phase error from pi/4 of 2deg, and a phase noise of -110 dBc/Hz at 1 MHz from 14 GHz, while consuming 18 mA from 0.8-V supply.     

A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling

A new concept for quadrature coupling of LC oscillators is introduced and demonstrated on a 5-GHz CMOS voltage-controlled oscillator (VCO). It uses the second harmonic of the outputs to couple the oscillators. The technique provides quadrature over a wide tuning range without introducing any increase in phase noise or power consumption. The VCO is tunable between 4.57 and 5.21 GHz and has a phase noise lower than -124 dBc/Hz at 1-MHz offset over the entire tuning range. The worst-case measured image rejection is 33 dB. The circuit draws 8.75 mA from a 2.5-V supply.     

Harmonic-suppressed quadrature-input frequency divider for OFDM systems

A fully balanced harmonic-suppressed quadrature-input frequency divider is proposed.The frequency divider improves the quadrature phase accuracy at the output by using both input I/Q signals.Compared with conventional dividers,the circuit achieves an output I/Q phase sequence that is independent of the input I/Q phase sequence.Moreover,the third harmonic is effectively suppressed by employing a double degeneration technique. The desig n is fabricated in TSMC 0.13-μm CMOS and operated at 1.2 V.While locked at 8.5 GHz,the proposed divider measures a maximum third harmonic rejection of 45 dB and a phase noise of-124 dBc/Hz at a 10 MHz offset.The circuit achieves a locking range of 15%while consuming a total current of 4.5 mA.     

An Integrated 5–2.5-GHz Direct-Injection Locked Quadrature LC VCO

This letter presents an integrated direct-injection locked quadrature voltage controlled oscillator (VCO), consisted of a 5-GHz VCO integrated with injection locked LC frequency dividers for low-power quadrature generation. The circuit is implemented using a standard 0.18-mum CMOS process. The differential VCO is a full PMOS Colpitts oscillator, and the frequency divider is performed by adding an injection nMOS between the differential outputs of complementary cross-coupled np-core LC VCO. The measurement results show that at the supply voltage of 1.8-V, the master 5-GHz VCO is tunable from 4.73 to 5.74GHz, and the slave 2.5-GHz VCO is tunable from 2.36 to 2.87GHz. The measured phase noise of master VCO is -118.2dBc/Hz while the locked quadrature output phase noise is -124.4dBc/Hz at 1-MHz offset frequency, which is 6.2dB lower than the master VCO. The core power consumptions are 7.8 and 8.7mW at master and slave VCOs, respectively     

New implementation of injection locked technique and its application to low phase noise quadrature oscillators

A new implementation of the injection locked technique is proposed. The incident signal is directly injected into the common-source connection node of the sub-harmonic oscillator instead of the gate of the tail current source, and a narrowband noise filtering network is inserted into the same node to suppress the tail current source noise. A novel quadrature oscillator with the proposed injection locked technique is presented. The simulations show that the phase noise of the quadrature oscillator is about 7 dB better than that of the stand-alone sub-harmonic oscillator. The quadrature oscillator has been implemented in 0.25 um CMOS process and the measured results show that the proposed quadrature oscillator could achieve a phase noise of −130 dBc/Hz at 1 MHz offset from 1.13 GHz carrier while only drawing an 8.0 mA current from the 2.5 V power supply.     

A Low Voltage Divide-by-4 Injection Locked Frequency Divider With Quadrature Outputs

This letter presents a low voltage quadrature divide-by-4 (divide4) injection-locked frequency divider (QILFD). The QILFD consists of a 1.8-GHz quadrature voltage controlled oscillator (QVCO) and two NMOS switches, which are inserted into the quadrature outputs of the QVCO for signal injection. The low-voltage CMOS divide4 QILFD has been implemented with the TSMC 0.18-mum 1P6 M CMOS technology and the core power consumption is 3.12mW at the supply voltage of 1.2V. The free-running frequency of the QILFD is tunable from 1.73 to 1.99GHz, the measured phase noise of QILFD is -118dBc/Hz at 1-MHz offset from the free running frequency of 1.82GHz. At the input power of 0dBm, the total locking range is from 6.86 to 8.02GHz as the tuning voltage is varied from 0 to 1.2V. The phase noise of the locked output spectrum is lower than that of free running ring oscillator by 11dBc/Hz. The phase deviation of quadrature output is about 0.8deg     

使用新注入锁定技术的低相位噪声正交振荡器

提出了一种利用新注入锁定技术的低相位噪声正交振荡器,激励信号直接注入子谐波振荡器的共源连接点.原理上,正交振荡器的相位噪声性能会比子谐波振荡器的相位噪声性能好.该正交振荡器已经采用0.25μmCMOS工艺实现,测试结果表明该正交振荡器的振荡频率约为1.13GHz,在偏离振荡频率1MHz处的相位噪声约为-130dBc/Hz.该振荡器采用2.5V电源电压,消耗的电流约为8.0mA.     

一种用于蓝牙系统的延迟锁相正交信号发生器

提出了一种延迟锁相结构的正交信号发生器 ,用于蓝牙的射频信号收发电路。介绍的延迟锁相环路结构使电路性能具有良好的工艺变化不相关性 ,在很宽的频带范围内均可获得高性能的正交信号。电路采用单层多晶硅、四层金属、0 .3 5 μm CMOS数字工艺实现 ,仿真结果表明 :电路稳定工作在 2 .45 GHz频率下 ,在 1 40 MHz的输入信号频率变化范围内 ,输出的正交信号相位偏差低于 1°,幅度偏差小于 5 %。电路主要由有源器件构成 ,面积小     

A NOVEL PHASE CONTROL TECHNIQUE FOR INJECTION LOCKED OSCILLATORS

A novel technique to obtain injection locked oscillators phase tuning beyond 180° is demonstrated. The idea is to cascade injection locked oscillators together for phase change accumulation. A two stage injection locked oscillators can theoretically provide a maximum of 360?phase change within the locking range. This is particularly useful for phased array antenna applications.     

2.4GHz零中频接收机中正交相位的自校准设计

提出了实现在一个2.4GHz零中频接收机中的一种正交相位自校准方法.这种方法基于一个采用提出的正交相位检测器的延迟锁定环路来大大减小正交相位误差.该接收机采用0.18μm CMOS工艺实现.测试结果显示正交相位误差可以被校准到1°以内,满足了系统的要求.     

An LO architecture with novel wide locking range,quadrature output RILFDs and ILROs for cognitive radio applications

In this paper, a wide locking range, quadrature output ring type injection locked frequency divider (ILFD) is presented for division ratios of 3 and 4. This ILFD proposes a novel injection scheme that shapes the injection signal to a proper form and provides a convenient situation for divider locking. Furthermore, two new wide locking range, low power consumption, injection locked ring oscillators (ILROs) are proposed for quadrature generation in local oscillator architectures. A novel cognitive radio quadrature local oscillator (LO) architecture is presented by utilizing the proposed ILFDs and ILROs to verify the effectiveness of the proposed circuits. Moreover, a new technique is implemented on the LO architecture to widen the frequency range without consuming any extra power. Because of using a single LC tank, this architecture is very compact. Also, it has the benefit of low power consumption and low output phase noise.     

G/sub m/-boosted common-gate LNA and differential colpitts VCO/QVCO in 0.18-/spl mu/m CMOS

The demand for radio frequency (RF) integrated circuits with reduced power consumption is growing owing to the trend toward system-on-a-chip (SoC) implementations in deep-sub-micron CMOS technologies. The concomitant need for high performance imposes additional challenges for circuit designers. In this paper, a g/sub m/-boosted common-gate low-noise amplifier (CGLNA), differential Colpitts voltage-controlled oscillators (VCO), and a quadrature Colpitts voltage-controlled oscillator (QVCO) are presented as alternatives to the conventional common-source LNA and cross-coupled VCO/QVCO topologies. Specifically, a g/sub m/-boosted common-gate LNA loosens the link between noise factor (i.e., noise match) and input matching (i.e., power match ); consequently, both noise factor and bias current are simultaneously reduced. A transformer-coupled CGLNA is described. Suggested by the functional and topological similarities between amplifiers and oscillators, differential Colpitts VCO and QVCO circuits are presented that relax the start-up requirements and improve both close-in and far-out phase noise compared to conventional Colpitts configurations. Experimental results from a 0.18-/spl mu/m CMOS process validate the g/sub m/-boosting design principle.     

A study of phase noise in CMOS oscillators

This paper presents a study of phase noise in two inductorless CMOS oscillators. First-order analysis of a linear oscillatory system leads to a noise shaping function and a new definition of Q. A linear model of CMOS ring oscillators is used to calculate their phase noise, and three phase noise phenomena, namely, additive noise, high-frequency multiplicative noise, and low-frequency multiplicative noise, are identified and formulated. Based on the same concepts, a CMOS relaxation oscillator is also analyzed. Issues and techniques related to simulation of noise in the time domain are described, and two prototypes fabricated in a 0.5-μm CMOS technology are used to investigate the accuracy of the theoretical predictions. Compared with the measured results, the calculated phase noise values of a 2-GHz ring oscillator and a 900-MHz relaxation oscillator at 5 MHz offset have an error of approximately 4 dB     

一种相位准确度高幅值失配度低的正交LO驱动电路

提出了一种工作在1.1～1.2GHz的相位准确度高、幅值失配度低的正交LO驱动电路.它主要由高频放大器、二阶的无源多项滤波器、相位和幅度校准电路(PMCC)组成.PMCC是一种利用前馈技术实现的低功耗电路,大大提高了正交信号的正交性,降低了相邻支路信号的幅值误差.仿真结果表明,经过PMCC校准后,输出正交信号的相位误差可以降低大约一半,而幅度误差可以降低到原来的十分之一.PMCC可直接驱动混频器,无需额外的驱动电路.本设计已经用TSMC 0.25μm CMOS工艺实现并进行了验证.测试结果表明本文提出的校准电路能够获得高正交性(＜2°)和低幅值误差(＜0.1%)的正交信号,测试的最大功率增益为5.25dB,在2.5V的电源电压下,消耗的电流约为6mA,芯片面积为1.0mm×1.0mm.     

Ring oscillators for CMOS process tuning and variability control

Test structures utilizing ring oscillators to monitor MOSFET ac characteristics for digital CMOS circuit applications are described. The measurements provide information on the average behavior of sets of a few hundred MOSFETs under high speed switching conditions. The design of the ring oscillators is specifically tailored for process centering and monitoring of variability in circuit performance in the manufacturing line as well as in the product. The delay sensitivity to key MOSFET parameter variations in a variety of ring oscillator designs is studied using a compact model for partially depleted silicon on insulator(PD-SOI) technology, but the analysis is equally valid for conventional bulk Si technology. Examples of hardware data illustrating the use of this methodology are taken primarily from experimental hardware in the 90-nm CMOS technology node in PD-SOI. The design and data analysis techniques described here allow very rapid investigation of the sources of variations in circuit delays.     

CMOS second-harmonic quadrature voltage controlled oscillator using substrate for coupling

In this work, a new circuit configuration for second-harmonic quadrature voltage controlled oscillator (QVCO) with CMOS technology is proposed. The proposed QVCO is made by coupling two identical cross-connected VCOs. The coupling elements (two resistors and two capacitors) do not increase the power consumption of the core VCOs and do not disturb the resonant frequency of the tank circuit in the core VCOs and also, according to the simulations the coupling elements do not adversely affect the phase noise. The role of the substrate terminal of cross-connected MOSFETs of the core oscillators as common mode nodes is demonstrated. Using this node for coupling makes it possible to eliminate the tail transistors in the core oscillators and therefore the circuit can operate with supply voltages as low as 0.5 V. Using the same method to couple more than two core oscillators, results in a multiphase VCO.     

深空测控系统1 Hz低相噪频率合成技术

针对深空测控系统高精度测量对于信道附加相噪的要求,采用直接数字频率合成（DDS）正交调制方法设计频率综合器。通过巧妙的试验和外推方法,择优选取电压型鉴相器,在锁相环相噪模型的基础上,全面分析各部分相噪的贡献,综合设计环路带宽,有效控制附加相噪,实现低相噪频综器最理想的目标,即环路带内的相噪完全由参考决定,带外的相噪由压控振荡器（VCO）决定,并采用两源互比的方法完成1 Hz极低相位噪声的测试,测试结果为-73 dBc/Hz,与设计结果完全一致。该方法对于测控站极低相噪的设计具有一定参考价值。