Potential and modeling of 1-μm SOI CMOS operationaltransconductance amplifiers for applications up to 1 GHz

The potential of 1-μm SOI complementary metal-oxide-semiconductor (CMOS) technology for the realization of operational transconductance amplifiers (OTAs) with transition frequencies in the gigahertz range is demonstrated. High-frequency device models, design guidelines and frequency limitations are detailed, as well as layout and technology improvements which can be used to boost the transconductance at high frequency and to reduce the source/drain-to-substrate capacitances. One-stage and folded-cascode OTA's have been realized to validate the design methodology     

A 0.8-V 816-nW delta–sigma modulator for low-power biomedical applications

This letter discusses the implementation of a low-voltage, low-power delta–sigma modulator as a sensing stage for biomedical applications. A distributed feed-forward structure and bulk-driven operational transconductance amplifier are used in order to achieve efficient operation at a supply voltage of 0.8 V. Instead of conventional low-voltage amplifier architectures, our design uses folded-cascode amplifiers, although they are not used in most low-voltage circuits. A wide input swing is achieved by using the bulk-driven approach, and the drawback of the limited voltage swing of the cascoded output stage is overcome by the distributed feed-forward modulator. The designed modulator has a dynamic range of 49 dB at a 0.8-V supply voltage and consumes only 816 nW of power for the 250-Hz bandwidth. The core chip size of the modulator is 1000 μm × 500 μm by using the 0.18-μm standard CMOS process.     

Symmetrically compensated fully differential folded-cascode OTA

A symmetric compensation technique that improves the phase response for fully differential folded-cascode operational transconductance amplifiers (OTA) is proposed. Theory and simulated results show that the magnitude response and settling time for symmetrically compensated OTAs are also improved in comparison with those of compensated and typical OTAs     

A 30-MHz Fifth-Order Elliptic Low-Pass CMOS Filter With 65-dB Spurious-Free Dynamic Range

A fifth-order 30-MHz integrated low-pass filter with 65-dB spurious-free dynamic range is presented. The topology is based on an operational transconductance amplifier (OTA)-C ladder configuration implementing an elliptic transfer function. High linearity and low noise are achieved by using polysilicon resistors and efficient highly linear transconductors based on a proposed nonlinear source degeneration technique. The linearity of a typical source degenerated structure is improved by more than 10 dB while the small-signal transconductance is reduced by less than 1 dB; the additional power needed by the auxiliary circuitry is less than 10% that of the OTA's power, and the noise level increases by no more than 1 dB. Experimental results of a prototype fabricated in a standard 0.35-mum CMOS technology are presented and compared with previously reported solutions. The overall filter's power consumption is 85 mW with a 3.3-V power supply     

CMOS OTA-C high-frequency sinusoidal oscillators

Several topology families are given to implement practical CMOS sinusoidal oscillators by using operational transconductance amplifier-capacitor (OTA-C) techniques. Design techniques are proposed taking into account the CMOS OTA's dominant nonidealities. Building blocks are presented for amplitude control, both by automatic gain control (AGC) schemes and by limitation schemes. Experimental results from 3- and 2-μm CMOS (MOSIS) prototypes that exhibit oscillation frequencies of up to 69 MHz are obtained. The amplitudes can be adjusted between 1 V peak to peak and 100 mV peak to peak. Total harmonic distortions from 2.8% down to 0.2% have been measured experimentally     

A 92-MHz 13-bit IF digitizer using optimized SC integrators in 0.35-/spl mu/m CMOS technology

A feedforward compensation scheme with no Miller capacitors is proposed to overcome the bandwidth limitations of traditional Miller compensation schemes. The technique has been used in the design of an operational transconductance amplifier (OTA) with a dc gain of 80 dB, gain bandwidth of 1.4 GHz, phase margin of 62/spl deg/, and 2 ns settling time for 2-pF load capacitor in a standard 0.35-/spl mu/m CMOS technology. The OTA's current consumption is 4.6 mA. The OTA is used in the design of a fourth-order switched-capacitor bandpass /spl Sigma//spl Delta/ modulator with a clock frequency of 92 MHz. It achieves a peak signal-to-noise ratio of 80 and 54 dB for 270-kHz (GSM) and 3.84-MHz (CDMA) bandwidths, respectively and consumes 19 mA of current from a /spl plusmn/1.25-V supply.     

一种新型的分段曲率补偿带隙基准源设计

针对传统的带隙基准源曲率补偿效果较差的问题,采用两路跨导放大器设计了一种新型的分段曲率补偿的带隙基准源。其中一路跨导放大器比较三极管的发射极-基极电压VEB和一个粗略的基准电压,在低温段产生随温度升高近似成指数减小的电流;另一路跨导放大器比较VEB和另一个粗略的基准电压,在高温段产生随温度升高近似成指数增大的电流,对传统的电流型带隙基准源进行精确的分段曲率补偿。基于TSMC 0. 18μm CMOS工艺,对电路进行设计和仿真。仿真结果表明,3. 3 V电源电压时,在-40^+150℃温度范围内,温度系数为1. 84×10^-6/℃,低频时的电源抑制比为-98. 3 d B,线性调整率为0. 0047%。     

A low-power low-jitter DLL with a differential closed-loop duty cycle corrector

This paper presents an optimization-based design methodology for fully differential amplifiers (FDAs) including the effects of real common-mode feedback (CMFB) circuits as constraints in the design flow. The sizing procedure is performed separately for the main amplifier and for the CMFB circuit, reducing the number of free variables and exploring the design space in a more efficient way. Also, this methodology can be employed to design single and two-stages FDAs whereas a second pole compensation scheme is necessary. In order to validate the proposed methodology, a two-stage fully differential amplifier with a no capacitor feed-forward (NCFF) compensation technique was designed in 0.13 μm CMOS technology with a 1.2 V power supply. The presented results also include a pole-zero pair mismatch analysis and proposes a solution in order to compensate the generated pole-zero doublet that might affect the performance of the amplifier. We can show that this approach reduces the overall static power consumption while satisfying the design specifications.     

一种恒跨导CMOS运算放大器的设计

设计了一种宽带轨对轨运算放大器,此运算放大器在3.3 V单电源下供电,采用电流镜和尾电流开关控制来实现输入级总跨导的恒定。为了能够处理宽的电平范围和得到足够的放大倍数,采用用折叠式共源共栅结构作为前级放大。输出级采用AB类控制的轨对轨输出。频率补偿采用了级联密勒补偿的方法。基于TSMC 2.5μm CMOS工艺,电路采用HSpice仿真,该运放可达到轨对轨的输入/输出电压范围。     

Low-Voltage High-Frequency Continuous-Time Filters Based on Simple Transconductors and Miller Integrators

An approach to implement low-voltage continuous-time filters using simple transconductance elements and gain-stage Miller integrators is presented. The technique allows direct translation of an RC active structure or a system block diagram into a CMOS circuit that uses differential pairs as transconductors and gain stages as Miller Integrators. A novel and efficient compensation technique to cancell excess phase in Miller integrators is discussed. A new high-frequency compensated CMOS universal filter structure that has no summing nodes in the main feedback loop is discussed and experimentally verified.     

Realization of current-mode high-order filters employing multiple output OTAs

Current-mode linear transformation (CMLT) high-order filters with minimum number of multiple output operational transconductance amplifiers (MOOTAs) are presented. Based on proposed design methods, we can synthesize current-mode high-order all-pole filters with minimum number of MOOTAs and all grounded capacitors efficiently. Moreover, high-frequency canonical CMLT elliptic filters with minimum number of MOOTAs and floating capacitors are also presented. Our proposed filters have the following merits: simplified design procedures, minimum number of active elements and simple design equations. Two design examples are demonstrated in this paper. Experimental results that confirm the theoretical analysis are provided.     

一种低功耗高线性度推挽跨导放大器

采用华虹NEC 0.35um BCD工艺,设计并实现了一种可作DC-DC转换器控制芯片内部误差放大器的CMOS跨导放大器,该跨导放大器采用源极电阻跨接式负反馈技术提高跨导的线性度、采用双折叠式差分对结构实现共模输入范围轨至轨(rail-to-rail)、采用低功耗偏置推挽(push-pull)输出结构提高输出驱动负载的能力,整体电路具有结构紧凑、功耗低、线性度高等特点。仿真结果表明:在5.25V电源电压下,驱动1pf负载,直流增益可以达到68.2db,功耗708uw,100kHz下跨导的三次谐波失真HD3达到-56db。     

基于电流模施密特触发器的OTA-C张弛振荡器及其PSPICE仿真研究

提出了基于电流模施密特触发器的OTA—C张弛振荡器。该电路的振荡信号周期可由接地电容线性改变,而频率则与OTA的跨导成正比。经PSPICE仿真模拟,其结果与理论计算值一致。     

A folded-cascode mixer for mixing-spur suppressions in a 2.4-to-5.8 GHz transmitter

This paper presents a folded-cascode mixer for an ISM band transmitter that translates the signals at the 2.4 GHz band to 5.8 GHz. Comparing to the conventional Gilbert cell mixer, our proposed folded-cascode mixer architecture with DC offset blocking, and transconductance linearization techniques can effectively suppress the LO feedthrough by 9 dB. The proposed mixer is designed in 0.11 μm CMOS and consumes 2.6 mA from a 1.2 V supply. The simulation results show that the mixer achieves an output power of 4.7 dBm, and all the emission spurs are well below −40dBc.     

Large Dynamic Range High Frequency Fully Differential CMOS Transconductance Amplifier

A large dynamic range high frequency fully differential CMOS transconductance amplifier is introduced. It is based on the linear transconductance element proposed in [8] combined with the common-mode feedback circuit in [9]. The original transconductance and common-mode circuits which use two supply voltages are modified for operation under a single power supply. The performance of the complete transconductance amplifier is analysed in details. Simulation results of the whole circuit are also presented, which show that with a single 5 V supply, bandwidth in excess of 300 MHz, THD below 0.7% for a 1 V _pk–pk differential input signal, and dynamic range in excess of 70 dB can be achieved for the fully differential transconductance amplifier.     

Improvements in Biasing and Compensation of CMOS Opamps

In this paper, we present modifications to the constant-g_m bias circuit and Miller-lead compensation of operational amplifiers which eliminate or minimize some of their shortcomings. First, we demonstrate how parasitic pad capacitance can cause instability in the constant-g_m bias circuit, and show that the transconductance is constant only for specific bias conditions. Next, we suggest a new circuit topology that requires 75% less compensation capacitance to achieve stability. We also discuss problems with Miller-lead compensation that arise from temperature, process, and load variations. Finally, we present a new biasing technique to correct these problems, and, through simulation, demonstrate a 40^∘ improvement in phase margin over load current variations.Sean Nicolson received the B.A.Sc. degree in 2000 from Simon Fraser University, Vancouver, Canada, and the M.A.Sc. degree in 2003 from the University of Toronto, Toronto, Canada. In 2001, he was an design engineer for NeuroStream Technologies, Inc., where he developed implantable electronic systems.Currently, he is working on his PhD degree in the Edward S. Rogers Senior Department of Electrical and Computer Engineering, University of Toronto. His research interests include integrated circuits for biomedical applications, RF communication systems, and millimeter-wave circuits.Khoman Phang (M’00) received the B.A.Sc., M.A.Sc., and Ph.D. degrees in 1990, 1992, and 2001 respectively from the University of Toronto, On, Canada. In 1993, he was a visiting researcher at Sony headquarters in Tokyo, Japan. He joined the Microelectronics Division of IBM, Toronto, Canada in 1994, where he was involved in the development of infrared wireless networking products.In 2000, he joined the University of Toronto where he is currently an Assistant Professor in the Edward S. Rogers Senior Department of Electrical and Computer Engineering. His research interests include analog integrated circuits, optical communication systems, and integrated circuits for biomedical applications.     

Multiple-Mode OTA-C Universal Biquad Filters

Two new multiple-mode (including voltage, current, transconductance, and transresistance modes) OTA-C universal biquad filters are proposed. The first proposed circuit uses only four operational transconductance amplifiers (OTAs) and two grounded capacitors. The second proposed circuit uses five OTAs and two grounded capacitors. Both the proposed circuits can realize voltage, current, transconductance, and transresistance mode universal filtering responses (low-pass, high-pass, band-pass, notch, and all-pass) from the same topology. The first proposed circuit uses the least number of components. This represents an attractive feature from a chip area and power consumption point of view. The second proposed circuit has no need of extra inverting and non-inverting amplifiers for special input signals. Moreover, both the proposed biquads still have (i) the employment of two grounded capacitors, (ii) cascadable connection of the former voltage-mode stage and the latter current-mode stage, and (iii) low sensitivity performance. H-SPICE simulation results confirm the theoretical analysis.     

A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors

A multistage operational transconductance amplifier with a feedforward compensation scheme which does not use Miller capacitors is introduced. The compensation scheme uses the positive phase shift of left-half-plane (LHP) zeroes caused by the feedforward path to cancel the negative phase shift of poles to achieve a good phase margin. A two-stage path increases further the low frequency gain while a feedforward single-stage amplifier makes the circuit faster. The amplifier bandwidth is not compromised by the absence of the traditional pole-splitting effect of Miller compensation, resulting in a high-gain wideband amplifier. The capacitors of a capacitive amplifier using the proposed techniques can be varied more than a decade without significant settling time degradation. Experimental results for a prototype fabricated in an AMI 0.5-/spl mu/m CMOS process show DC gain of around 90 dB and a 1% settling time of 15 ns for a load capacitor of 12 pF. The power supply used is /spl plusmn/1.25 V.     

Improved Reversed Nested Miller Frequency Compensation Technique With Voltage Buffer and Resistor

This brief introduces and develops a novel frequency compensation technique for three-stage operational transconductance amplifiers. The new compensation topology exploits a voltage buffer and a nulling resistor to achieve a double pole-zero cancellation, occurring beyond the gain-bandwidth product. To verify the effectiveness of the compensation scheme, an amplifier has been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found to be in good agreement with the theoretical analysis and show an improvement in small-signal and large-signal performances     

偏振模色散前馈方案中偏振主态研究

前馈偏振模色散（PMD）补偿系统中重要的一项是要精确得到链路中的偏振主态（PSP）方向。通过在实验中加入扰偏器，分别用矢量法和粒子群优化（PSO）算法来拟合实验结果得到椭球，从而用椭球法得出了主态方向。结果表明：矢量法在获得椭球要比PSO算法更精确、速度更快以及所得到PSP方向更准确，其更适合用于前馈补偿方案中。