SET-based nano-circuit simulation and design method using HSPICE

This paper presents a simulation and design method for complementary SET-based nano-circuits from a practical circuit design point of view. HSPICE behavioral implementation of modified Lientschnig's SET model based on the orthodox theory and the Birth-Death Markov chain is demonstrated and verified with Coulomb characteristics. It shows reduced CPU time, improvement of accuracy, and more compatibility with other SPICE softwares on both Windows and Unix platforms. The proposed design methodology presents how to build static CMOS-like SET circuits, and demonstrates that conventional CMOS circuit design methodologies are all applicable to SET circuit designs based on the methodology. HSPICE simulation results show that, for 1 MΩ junction resistance, the power consumption of a SET NAND2 gate is less than 0.3 pW, and the propagation delay for a SET XOR2 gate is 29.8 ns while driving a 10 aF load.     

Single-bit digital comparator circuit design using quantum-dot cellular automata nanotechnology

The large amount of secondary effects in complementary metal–oxide–semiconductor technology limits its application in the ultra-nanoscale region. Circuit designers explore a new technology for the ultra-nanoscale region, which is the quantum-dot cellular automata (QCA). Low-energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low-complexity, QCA-based one-bit digital comparator circuit for the ultra-nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer-E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design.     

Adder design using 5-input majority gate in a novel “Multilayer Gate Design Paradigm” for Quantum Dot Cellular Automata Circuits

This paper proposes a novel design paradigm for circuits designed in quantum dot cellular automata (QCA) technology. Previously reported QCA circuits in the literature have generally been designed in a single layer which is the main logical block in which the inverter and majority gate are on the base layer, except for the parts where multilayer wire crossing was used. In this paper the concept of multilayer wire crossing has been extended to design logic gates in multilayers. Using a 5-input majority gate in a multilayer, a 1-bit and 2-bit adder have been designed in the proposed multilayer gate design paradigm. A comparison has been made with some adders reported previously in the literature and it has been shown that circuits designed in the proposed design paradigm are much more efficient in terms of area, the requirement of QCA cells in the design and the input-output delay of the circuit. Over all, the availability of one additional spatial dimension makes the design process much more flexible and there is scope for the customizability of logic gate designs to make the circuit compact.     

基于量子细胞自动机的数值比较器设计

量子细胞自动机(QCA)可以构建逻辑门和QCA线。该文基于QCA设计了1位,4位和8位数值比较器,并用QCADesigner软件进行模拟。结果表明,所设计的电路具有正确的逻辑功能。通过对电路所需细胞数、面积和时延三方面性能分析,表明所设计的电路时延并不随输入位数呈线性增加,因而所设计的电路具有良好的时延性。     

基于SET/MOS混合结构的译码器电路的设计

基于SET的I-V特性以及SET与MOS管互补的特性,以MOS管的逻辑电路为设计思想,首先提出了一个SET/MOS混合结构的反相器,进而推出或非门电路,并最终实现了一个唯一地址译码器.通过SET和MOS管两者的混合构建的电路与纯SET实现的电路相比,电路的带负载能力增强;与纯MOS晶体管实现的电路相比,电路同样仅需要单电源供电,且元器件数目得到了减少,电路的静态功耗大大降低.仿真结果验证了电路设计的正确性.     

New modified-majority voter-based efficient QCA digital logic design

ABSTRACT

Quantum-dot cellular automata (QCA) is an emerging nanotechnology and a possible alternative solution to the limitation of complementary metal oxide semiconductor (CMOS) technology. One of the most attractive fields in QCA is the implementation of configurable digital systems. This article presents a novel multifunctional gate called the modified-majority voter (MMV). The proposed gate works on the explicit interaction of the cell characteristic property for the implementation of digital circuits. This prominent feature of the proposed gate reduces the maximum hardware cost and implements highly efficient QCA structures. To verify the functionality of the proposed gate, some physical proofs, truth table and computational simulation results are performed. These results assured the validity of the existence of the proposed gate. It also dissipates less energy which has been calculated under three separate tunnelling energy levels using the QCAPro tool. To prove the effectiveness of the proposed MMV gate, several optimal irreversible arithmetic circuits such as three-input XOR, half-adder and full-adder are proposed. The modular layouts are verified with the freely available QCADesigner tool version 2.0.3.     

Analysis of missing and additional cell defects in sequential quantum-dot cellular automata

The defect characterization of sequential devices and circuits, implemented by molecular quantum-dot cellular automata (QCA), is analyzed in this paper. A RS-type flip–flop is first introduced; this flip–flop takes into account the timing issues associated with the adiabatic switching of this technology and its requirements. It is then shown that a D-type flip–flop can be constructed with an embedded QCA wire which extends over multiple clocking zones. The logic-level characterization of both flip–flop devices is provided. A single additional and missing cell defect model is assumed for molecular implementation. For sequential circuits, defect characterization is pursued. It is shown that defects affect the functionality of basic QCA devices, resulting mostly in unwanted inversion and majority voter acting as a wire at logic level. In this paper, it is shown that a device-level characterization of the defects and faults can be consistently extended to a circuit-level analysis.     

Single-Bit Comparator in Quantum-Dot Cellular Automata (QCA) Technology Using Novel QCA-XNOR Gates

To fill the continuous needs for faster processing elements with less power consumption causes large pressure on the complementary metal oxide semiconductor (CMOS) technology developers. The scaling scenario is not an option nowadays and other technologies need to be investigated. The quantum-dot cellular automata (QCA) technology is one of the important emerging nanotechnologies that have attracted much researchers’ attention in recent years. This technology has many interesting features, such as high speed, low power consumption, and small size. These features make it an appropriate alternative to the CMOS technique. This paper suggests three novel structures of XNOR gates in the QCA technology. The presented structures do not follow the conventional approaches to the logic gates design but depend on the inherent capabilities of the new technology. The proposed structures are used as the main building blocks for a single-bit comparator. The resulted circuits are simulated for the verification purpose and then compared with existing counterparts in the literature. The comparison results are encouraging to append the proposed structures to the library of QCA gates.     

Design of testable reversible latches by using a novel efficient implementation of Fredkin gate

ABSTRACT

Energy dissipation caused by information loss in irreversible computations will be an important limitation for the development of nano-scale circuits in the near future. Reductions in energy dissipation comprise one of the important goals of nanotechnology-based methods, including Quantum dot Cellular Automata (QCA), and so it is desirable to consider reversibility in the design of QCA circuits. In this research, a novel reversible Fredkin gate based on QCA is proposed, which is more efficient and less complex than the conventional Fredkin gate. Conservative reversible logic is parity preserving; hence, any permanent or transient fault can be caused a mismatch between the inputs and the outputs and can be concurrently detected if a reversible circuit is implemented with the conservative Fredkin gate. A single missing/additional cell defect is investigated in the proposed Fredkin gate and fault patterns are presented. To demonstrate the efficiency of the proposed design, some testable reversible sequential elements, such as D-latch, JK-latch, T-latch and SR-latch, are designed by using it. Our proposed concurrent testable designs greatly reduce the occupied area and maximise the circuit density in comparison with previously reported designs. The proposed designs are simulated and verified using QCA Designer ver.2.0.3 and HDLQ.     

A new quantum-dot cellular automata full-adder

A novel expandable five-input majority gate for quantum-dot cellular automata and a new full-adder cell are presented. Quantum-dot cellular automata (QCA) is an emerging technology and a possible alternative for semiconductor transistor based technologies. A novel QCA majority-logic gate is proposed. This component is suitable for designing QCA circuits. The gate is simple in structure and powerful in terms of implementing digital functions. By applying these kinds of gates, the hardware requirement for a QCA design can be reduced and circuits can be simpler in level, gate counts and clock phases. In order to verify the functionality of the proposed device, some physical proofs are provided. The proper functionality of the FA is checked by means of computer simulations using QCADesigner tool. Both simulation results and physical relations confirm our claims and its usefulness in designing every digital circuit.     

Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design

A physically based compact analytical single electron transistor (SET) model is proposed for hybrid CMOS-SET analog circuit simulation. The modeling approach is based on the "orthodox theory" of single electron tunneling, and valid for single or multi gate, symmetric or asymmetric devices and can also explain the background charge effect. The model parameters are physical device parameters and an associated parameter extraction procedure is reported. The device characteristics produced by the proposed model are verified with Monte Carlo simulation for large range of drain to source voltages (|V/sub DS/|/spl les/3e/C/sub /spl Sigma//) and temperatures [T/spl les/e/sup 2//(10k/sub B/C/sub /spl Sigma//)] and good agreements are observed. The proposed model is implemented in a commercial circuit simulator in order to develop a computer-aided design framework for CMOS-SET hybrid IC designs. A series of SPICE simulations are successfully carried out for different CMOS-SET hybrid circuits in order to reproduce their experimental/Monte Carlo simulated characteristics.     

Design and evaluation of new majority gate-based RAM cell in quantum-dot cellular automata

Quantum-dot cellular automata is one of the candidate technologies used in Nano scale computer design and a promising replacement for conventional CMOS circuits in the near future. Since memory is one of the significant components of any digital system, designing a high speed and well-optimized QCA random access memory (RAM) is a remarkable subject. In this paper, a new robust five-input majority gate is first presented, which is appropriate for implementation of simple and efficient QCA circuits in single layer. By employing this structure, a novel RAM cell architecture with set and reset ability is proposed. This architecture has a simple and robust structure that helps achieving minimal area, as well as reduction in hardware requirements and clocking zone numbers. Functional correctness of the presented structures is proved by using QCADesigner tool. Simulation results confirm efficiency and usefulness of the proposed architectures vis-à-vis state-of-the-art.     

单电子晶体管及其在细胞神经网络中的应用

研究了单电子晶体管的特性及主方程法,建立了基于主方程法的单电子晶体管SPICE模型,实现了对细胞神经网络单元的仿真。仿真结果表明,采用主方程法建立的单电子晶体管模型具有合理的精确度,对细胞神经网络单元的实现具有速度快、低功耗的优点,适合复杂细胞神经网络的进一步构建。     

量子元胞自动机器件和电路的研究进展

量子元胞自动机(QCA)是一种新颖的纳米技术,该技术不再通过电流或电压而是基于场相互作用进行信息的计算和传递。首先,综述了两种量子元胞自动机(EQCA和MQCA)器件的计算原理、基本逻辑门和时钟。指出了QCA元胞构成的不同线结构可在相同层交叉传递信号而不受影响。然后,进一步总结了制备QCA器件和功能阵列或电路的实验方法和材料,得出MQCA器件和分子EQCA器件的发展将使该器件逐步达到实际应用水平的结论。详细讨论了目前QCA器件和电路(尤其是存储单元结构)研究取得的重要进展以及面临的问题。提出了QCA器件未来理论和应用研究中的开放课题和方向。     

A new design of QCA‐based nanoscale multiplexer and its usage in communications

Quantum‐dot cellular automata (QCA) is one of the proposed nanotechnologies in the electronics industry, which offers a new construction for scheming digital circuits with less energy consumption on the nanoscale and possibly can be an appropriate replacement of complementary metal‐oxide semiconductor (CMOS) technology. Nanocommunication in QCA has attracted a wide range of researcher's attention. However, there is still a broad scope to design QCA‐based architecture for nanocommunication. The multiplexer is hugely used in the telecommunication system and transmits multiple data at the same time. Therefore, in this paper, a useful structure to implement a 2 to 1 multiplexer based on the novel XOR gate is presented and is used as a module to implement the 4 to 1 and 8 to 1 multiplexers. Simulations using QCADesigner tool are done to check the performance of the suggested designs. The 2 to 1, 4 to 1, and 8 to 1 QCA multiplexer structures utilize 22, 92, and 260 cells and consume 0.03, 0.12, and 0.40 μm² of area, respectively. They have shown that the suggested designs have stable and applicable structures regarding area, cost, and complexity.     

Exact analytical model of single electron transistor for practical IC design

This paper presents a new exact analytical model for single electron transistor (SET) applicable for circuit simulation. It has been developed based on orthodox theory of single electronics using master equation where a scheme has been suggested to determine the most probable occupied electron states. The proposed model is more flexible and is valid for single or multi-gate, symmetric or asymmetric devices and can also consider the background charge effect. It can be used for large drain-source voltage range whatever the device is biased under symmetric or asymmetric bias conditions. SET characteristics produced by the proposed model have been verified against widely accepted single electron circuits Monte Carlo simulator SIMON and show a good agreement. Moreover, the model has been implemented in a widely used commercial circuit simulator SPICE to enable simulation with conventional electronic elements and a single electron inverter has been simulated and verified with SIMON results.     

Design of reliable universal QCA logic in the presence of cell deposition defect

The emergence of Quantum-dot Cellular Automata (QCA) has resulted in being identified as a promising alternative to the currently prevailing techniques of very large scale integration. QCA can provide low-power nanocircuit with high device density. Keeping aside the profound acceptance of QCA, the challenge that it is facing can be quoted as susceptibility to high error rate. The work produced in this article aims towards the design of a reliable universal logic gate (r-ULG) in QCA (r-ULG along with the single clock zone and r-ULG-II along with multiple clock zones). The design would include hybrid orientation of cells that would realise majority and minority, functions and high fault tolerance simultaneously. The characterisation of the defective behaviour of r-ULGs under different kinds of cell deposition defects is investigated. The outcomes of the investigation provide an indication that the proposed r-ULG provides a fault tolerance of 75% under single clock zone and a fault tolerance of 100% under dual clock zones. The high functional aspects of r-ULGs in the implementation of different logic functions successfully under cell deposition defects are affirmed by the experimental results. The high-level logic around the multiplexer is synthesised, which helps to extend the design capability to the higher-level circuit synthesis.     

A Novel Hybrid Phase-Locked-Loop Frequency Synthesizer Using Single-Electron Devices and CMOS Transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PLL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PLL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.     

超深亚微米工艺下的电路级耦合SET脉冲注入

超深亚微米工艺下在电路模拟器中使用独立电流源方法的单粒子瞬态(single event transient,SET)脉冲注入与实验结果有很大误差.作者提出了一种基于二维查找表的耦合电流源注入的方法,并且基于开源的SPICE代码实现.该方法的计算结果与器件/电路混合模拟接近,而其计算时间远小于混合模拟.该法与SPICE集成,可以引入实验测量数据,适合于大规模组合电路的SET错误率分析.     

超深亚微米工艺下的电路级耦合SET脉冲注入

超深亚微米工艺下在电路模拟器中使用独立电流源方法的单粒子瞬态(single event transient, SET)脉冲注入与实验结果有很大误差. 作者提出了一种基于二维查找表的耦合电流源注入的方法,并且基于开源的SPICE 代码实现. 该方法的计算结果与器件/电路混合模拟接近,而其计算时间远小于混合模拟. 该法与SPICE 集成,可以引入实验测量数据,适合于大规模组合电路的SET 错误率分析.