薄片划片微损伤与芯片断裂强度探讨

超薄圆片的减薄、划片技术是集成电路封装小型化的关键基础工艺技术,随着减薄后化学机械抛光（CMP）、旋转腐蚀、干法刻蚀或干法抛光等释放应力技术被广泛采用,减薄造成的圆片背面损伤几乎为零,所以划片造成的微损伤对芯片断裂强度的影响变得越来越突出。本文分析了影响芯片断裂强度的主要原因,对薄片划片微损伤的来源、危害及解决方法进行了探讨。同时,着重介绍了一种新的激光划片方式,即喷水波导激光（LMJ）划片法。     

超薄圆片划片工艺探讨

集成电路小型化正在推动圆片向更薄的方向发展,超薄圆片的划片技术作为集成电路封装小型化的关键基础工艺技术,显得越来越重要,它直接影响产品质量和寿命。本文从超薄片划片时常见的崩裂问题出发,分析了崩裂原因,简单介绍了目前超薄圆片切割普遍采用的STEP切割工艺。另外,针对崩裂原因,还从组成划片刀的3个要素入手分析了减少崩裂的选刀方法。     

晶圆清洗过程中静电电压超标原因与改进

分析划片后的晶圆在清洗过程中静电电压严重超标的原因,提出4种改进方案,采用16种晶圆进行了验证。结果表明:清洗过程中关闭清洗机剥离胶膜用反冲气,操作人员佩戴防静电腕带,在取出晶圆过程中采用手持式可移动离子风枪对晶圆进行风淋,可解决长期存在的晶圆划片后清洗过程中表面静电电压严重超标的问题。     

A cutting algorithm for optimizing the wafer exposure pattern

Semiconductor manufacturing industry competes by increasing yield and lowering die costs, thereby taking advantage of significant capital investments. Many studies focus on defect reduction to improve yield rate. However, the problem of optimizing wafer exposure patterns has received little attention. In this paper, given the specific patterning constraints, we develop a two-dimensional (2-D) cutting algorithm to maximize the gross die yields of the eight-inch wafer and larger circular wafers. The empirical results that we implemented in a wafer fabrication factory in Taiwan validate the practical viability of this approach. Similar approaches can readily be applied to other wafer patterning     

Wafer-applied underfill: flip-chip assembly and reliability

Manufacturers of consumer electronic products are continuously striving to confer greater functionality to smaller, lighter, and less expensive packages, and flip-chip is an important enabling technology for these product trends. Underfill between the die and an organic substrate is necessary to compensate for the coefficient of thermal expansion mismatch. The underfill dispense and cure step is not a typical process for a surface-mount technology (SMT) factory, and demands additional capital equipment, floor space, cycle time, and headcount. An alternate approach to traditional capillary underfill is wafer-applied underfill. The underfill is applied after wafer bumping and sawing, but prior to the picking of the individual die from the saw tape. This paper describes the coating and assembly processes. Liquid-to-liquid thermal cycle shock tests (-55 to +125/spl deg/C) have been performed on test vehicles assembled with the wafer-applied underfill. First failures were at over 1000 cycles. Weibull plots of the data and failure analysis are presented.     

Fracture strength characterization and failure analysis of silicon dies

This paper characterizes fracture strength of a silicon die as a first step to predict and prevent die cracking during package assembly, reliability tests, and operation life. Die strength is measured via the three-point bend test conducted using a micro-force tester. Strength reduction due to surface defects, such as tiny notches or micro-cracks that are introduced through wafer backside grinding is evaluated. It is observed that die strength strongly depends on the grinding patterns, i.e. minimum die strength in a wafer is found if the grinding mark is in parallel with the loading axis. Furthermore, fracture strength of dies with different wafer surface conditions like polishing and no treatment (grinding) are also examined. Polished wafers possess the highest silicon strength owing to its minimum surface flaws. On the other hand, untreated wafers contain the most severe surface defects; hence exhibit the lowest die strength. Geometrical factors (square vs. rectangular) and die thickness (4 vs. 6 mils) are probed as well, however these factors do not contribute to die strength degradation. Surface morphology and roughness studies of silicon dies via scanning electron microscope and atomic force microscope also confirmed that die strength degradation is mainly controlled by surface defect (roughness) levels. Observed fracture modes also correlate well with measured die strength.     

An Alternative Integrated-Circuit Yield Model

This paper develops a model to predict the number of good integrated circuits (the yield) from a semiconductor wafer processing line. The model is different from other published models and predicts observed outcomes better. Many models tend to predict lower yields than those actually achieved because those models are inherently incapable of predicting the average number of good chips per wafer. The model developed in this paper is based on combinatorial analysis and considers the number of die sites on the wafer and the total number of yield detracting defects on the wafer. In contrast the other models referenced require at least two parameters as input data: the area of one die site or chip and the average defect density. A third parameter, the Cdf of the defect density is often implied by the selection of the model.     

Mechanisms of wafer sawing and impact on wafer properties

Silicon wafer wire‐sawing experiments were realized with different sets of sawing parameters, and the thickness, roughness, and cracks depth of the wafers were measured. The results are discussed in relation to assumptions underlying the rolling–indenting model, which describes the process. It was also found that the silicon surface at the bottom of the sawing groove is different from the wafer surface, implying different sawing conditions in the two positions. Furthermore, the measured parameters were found to vary along the wire direction, between the entrance of the wire in the ingot and its exit. Based on these observations, some improvements for the wire‐sawing model are discussed. Copyright © 2010 John Wiley & Sons, Ltd.     

Sea of Leads Compliant I/O Interconnect Process Integration for the Ultimate Enabling of Chips With Low-$hbox k$Interlayer Dielectrics

Sea of leads (SoL) process integration for the series of steps required to transform a fully intact die at the wafer level to a die that is assembled onto a board is described. The primary goal is to address the issues involved in reconciling the fabrication and assembly requirements of compliant leads, such as SoL, with those of standard semiconductor processes and chip assembly techniques. The effort is motivated in-part by the potential failure of the low-$hbox k$interlayer dielectric in microprocessors as a result of high mechanical stresses due to the coefficient of thermal expansion (CTE) mismatch between the chip and the board. SoL, and other compliant interconnections, mitigate this problem by mechanically decoupling the chip and the board. While compliant leads offer advantages over C4 technology, there is much to consider during the series of steps needed to transform the fully intact dice at the wafer level to dice that are assembled onto the board. The use of an encapsulation film over the leads during wafer sawing is shown to be necessary for slippery leads and other free-standing compliant leads. The use of a suitable flux when the leads are finished with a nickel–oxide nonwettable layer is essential for a successful wafer-level solder reflow. Successful die assembly using thermocompression bonding is demonstrated using two different SoL dice with correspondingly different substrates. The resistance of a chain of 30 cascaded leads is 2.7$Omega$.     

Yield challenges in wafer stacking technology

Wafer stacking technology offers a higher performance in a smaller size with a lower cost option for microelectronic industries. However, it suffers from a compound yield loss which becomes a key challenge and a limiting factor in this technology. A compound yield loss in wafer stacking has been analyzed and yield challenges have been presented. Assuming a random defect density per wafer and no yield fallout from stacking processes, the compound yield of a bonded wafer pair has been estimated with the most commonly used yield model. As a result, it is proposed that a die area reduction for wafer stacking is needed in order to offer a great yield advantage. Both wafer testing and wafer size are also proven to influence significantly a die yield in a bonded wafer pair.     

A neural-network approach for semiconductor wafer post-sawinginspection

Semiconductor wafer post-sawing requires full inspection to assure defect-free outgoing dies. A defect problem is usually identified through visual judgment by the aid of a scanning electron microscope. By this means, potential misjudgment may be introduced into the inspection process due to human fatigue. In addition, the full inspection process can incur significant personnel costs. This research proposed a neural-network approach for semiconductor wafer post-sawing inspection. Three types of neural networks: backpropagation, radial basis function network, and learning vector quantization, were proposed and tested. The inspection time by the proposed approach was less than one second per die, which is efficient enough for a practical application purpose. The pros and cons for the proposed methodology in comparison with two other inspection methods, visual inspection and feature extraction inspection, are discussed. Empirical results showed promise for the proposed approach to solve real-world applications. Finally, we proposed a neural-network-based automatic inspection system framework as future research opportunities     

Reliability versus yield and die location in advanced VLSI

The results of multiple correlations between reliability and yield on a die level basis are presented for an advanced microprocessors fabricated using a 0.25μ, five layer metal CMOS logic process. Traceability information was programmed into each unit; investigated were infant mortality of edge die versus center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn in failures.The model that reliability defect density is proportional to yield defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. Because the traceability information was part of the standard manufacturing flow this analysis was performed using very large, 1 million unit sample sizes.     

Back-end soft and hard defect monitoring using a single test chip

The objective of this paper is to present a mixed test structure designed to characterize yield losses due to hard defect and back-end process variation (PV) at die and wafer level. A brief overview of the structure, designed using a ST-Microelectronics’ 130 nm technology, is given. This structure is based on a SRAM memory array for detecting hard defects. Moreover each memory cell can be configured in the Ring Oscillator (RO) mode for back-end PV characterization. The structure is tested in both modes (SRAM, RO) using a single test flow. The test data analysis method is presented and applied to experimental results to confirm the ability of the structure to monitor PV and defect density.     

IC封装中引起芯片裂纹的主要因素

芯片裂纹是半导体集成电路封装过程中最严重的缺陷之一。由于芯片裂纹最初发生在芯片的背面,而且有时要在高倍显微镜下才能观察到,所以这种缺陷在很多情况下不易被发现。文章主要介绍和探讨了IC封装过程中引起芯片裂纹的主要原因。划片刀速度、装片顶针位置／顶针高度和吸嘴压力、塑封框架不到位以及切筋打弯异常等都会引起芯片裂纹,从而在从IC焊接到PCB板或使用过程中出现严重的失效和可靠性质量问题。只有了解了导致芯片裂纹的各种因素,半导体集成电路封装厂商才能采取针对性的预防措施杜绝芯片裂纹这种致命的缺陷。     

晶圆切割中背面崩裂问题的分析

半导体技术不断发展,越来越多的新材料、新工艺应用在晶圆制造中。这对封装核心工序的划片工艺提出了很大挑战。在划片工艺中背面崩裂的控制是一个难点。文章主要是从工艺材料、工艺条件、划片刀以及设备四方面分析产生背面崩裂的主要因素以及优化方法。同时介绍了两种控制背面崩裂较有效的切割工艺：减少应力的开槽切割工艺和DBG工艺。     

Strategy and metrics for wafer handling automation in legacysemiconductor fab

We present a systematic approach for converting a legacy wafer fab from manual wafer handling to fully automatic wafer handling. Our strategy began by quantifying the need for automation in terms of impact on die yield, identifying a seven percent die loss associated with scratches from wafer handling. We then addressed the fundamental changes in production equipment and processes as well as overall fab goals and attitudes that are required to achieve full wafer handling automation. After considering several approaches to staged fab automation, we selected an approach which eliminated all manual handling within specific fab modules, completing the automation within one group of modules before embarking on another module set. In this way, we limited both the initial scope and cost of the project while preparing to leverage its initial successes. This paper summarizes the methodology and metrics found useful for preparing the fab for change, executing the change, and successfully managing the overall project     

Reliability Study of High-Density EBGA Packages Using the Cu Metallized Silicon

The reliability of high-density enhanced ball grid array (EBGA) packages using the eight-layer Cu metallization silicon was discussed. The key failure mechanisms included the die cracking (in the vicinity of the edge) and thin film delamination. It was noticed that the failure was unique to the Cu metallization silicon. The large package body size (45 mm$^{2}$) and the die size (approximately 15 mm$^{2}$ ) provided additional manufacturing and reliability challenges. The die-edge defects induced during the wafer sawing process were exhibited to be the culprits of the die cracking and the thin film delamination failures. Additionally, the height of die attach fillets significantly influenced the stresses on the die edge, and the excessive fillet height was found to help extend initial cracks at the edge of the silicon. The results demonstrated the adoption of a dual-step wafer sawing scheme and resin blades would control the defects and reduce the failure rate dramatically. A mixture of low-stress encapsulation and die attach materials would help improve the overall reliability of the packages as well. The solder joint reliability of the package was very robust based on the board-level reliability testing results. The statistical analysis of the test results confirmed that most of the die cracking and thin film delamination failures were early-life failures and random. A good sample screening scheme and the process improvement procedure would help improve the reliability and insure the customer a low failure rate for the lifetime of the product. The predicted reliability of the package met the application life needs for the products with process improvement plans in place.      

Effect of laminated wafer toward dicing process and alternative double pass sawing method to reduce chipping

Thin wafers of 100-/spl mu/m thickness laminated with die-attach film (DAF) was diced using a standard sawing process and revealed a low chipping crack resistance. Wafers laminated with conductive DAF shows greater chipping compared to nonconductive DAF and bare silicon wafer. It was found through scanning electron microscopy (SEM) micrographs, energy dispersive X-ray (EDX) analysis, and atomic force microscopy (AFM) that silver fillers in the conductive DAF was the cause of excessive blade loading which resulted in bad chipping quality. To reduce chipping/cracking induced by sawing, an alternative double-pass sawing method was developed and is explained in the paper. The methodology of this study discusses a double-pass method, where the first pass dice through the wafer and varied the percentage of DAF thickness cut. Best results were achieved when dicing through the wafer and 0% of DAF, followed by a full separation in the second pass. Approximately 80% of chipping reduction compared to conventional single pass.     

Maximizing the Functional Yield of Wafer-to-Wafer 3-D Integration

Three-dimensional integrated circuit technology with through-silicon vias offers many advantages, including improved form factor, increased circuit performance, robust heterogenous integration, and reduced costs. Wafer-to-wafer integration supports the highest possible density of through-silicon vias and highest throughput; however, in contrast to die-to-wafer integration, it does not benefit from the ability to bond only tested and diced good die. In wafer-to-wafer integration, wafers are entirely bonded together, which can unintentionally integrate a bad die from one wafer to a good die from another wafer reducing the yield. In this paper, we propose solutions that maximize the yield of wafer-to-wafer 3-D integration, assuming that the individual die can be tested on the wafers before bonding. We exploit some of the available flexibility in the integration process, and propose wafer assignment algorithms that maximize the number of good 3-D ICs. Our algorithms range from scalable, fast heuristics to optimal methods that exactly maximize the yield of wafer-to-wafer 3-D integration. Using realistic defect models and yield simulations, we demonstrate the effectiveness of our methods up to large numbers of wafer stacks. Our results demonstrate that it is possible to significantly improve the yield in comparison to yield-oblivious wafer assignment methods.      

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

Recent enhancements in process development enable the fabrication of three dimensional stacked ICs (3D-SICs) such as memories based on Wafer-to-Wafer (W2W) stacking. One of the major challenges facing W2W stacking is the low compound yield. This paper investigates compound yield improvement for W2W stacked memories using layer redundancy and compares it to wafer matching. First, an analytical model is provided to prove the added value of layer redundancy. Second, the impact of such a scheme on the manufacturing cost is evaluated. Third, these two parts are integrated to analyze the trade-off between yield improvement and its associated cost; the realized yield improvement is also compared to yield gain obtained when using wafer matching. The simulation results show that for higher stack sizes layer redundancy realizes a significant yield improvement as compared to wafer matching, even at lower cost. For example, for a stack size of six stacked layers and a die yield of 85?%, a relative yield improvement of 118.79?% is obtained with two redundant layers, while this is 14.03?% only with wafer matching. The additional cost due to redundancy pays off; the cost of producing a good 3D stacked memory chip reduces with 37.68?% when using layer redundancy and only with 12.48?% when using wafer matching. Moreover, the results show that the benefits of layer redundancy become extremely significant for lower die yields. Finally, layer redundancy and wafer matching are integrated to obtain further cost reductions.