Growth and fabrication of AlGaN/GaN HEMT based on Si(1 1 1) substrates by MOCVD

AlGaN/GaN high electron mobility transistor (HEMT) hetero-structures were grown on the 2-in Si (1 1 1) substrate using metal-organic chemical vapor deposition (MOCVD). Low-temperature (LT) AlN layers were inserted to relieve the tension stress during the growth of GaN epilayers. The grown AlGaN/GaN HEMT samples exhibited a maximum crack-free area of 8 mm×5 mm, XRD GaN (0 0 0 2) full-width at half-maximum (FWHM) of 661 arcsec and surface roughness of 0.377 nm. The device with a gate length of 1.4 μm and a gate width of 60 μm demonstrated maximum drain current density of 304 mA/mm, transconductance of 124 mS/mm and reverse gate leakage current of 0.76 μA/mm at the gate voltage of −10 V.     

Stability of Frenkel pairs in Si(1 0 0) surface in the presence of germanium and oxygen atoms

A first-principles pseudo-potential study of Frenkel pair generation close to the Si(1 0 0) surface in the presence of germanium and oxygen atoms is reported. The energies and structures of the defect structures (i.e. vacancy and relaxed tetrahedral Si interstitial) are calculated using supercell with up to 88 atoms. We present results obtained using the generalized gradient approximation (GGA) for the exchange-correlation energy. We examine the effect of the presence of germanium and oxygen atoms on the stability of Frenkel pairs generated near the Si(1 0 0) surface by comparing a number of individual cases, starting from vacancy interstitial pairs situated at various positions. The general tendency of the created interstitials is to climb towards the surface, but they generally remain in subsurface layers, ready to migrate into the layer. This tendency is enhanced by the presence of the Ge and/or O atoms. We show that the formation energy is lower and Si interstitials can be created with energies as low as 1.5 eV.     

Capacitance-voltage analysis of InAs quantum dots grown on InAlAs/InP(0 0 1)

The electronic properties of InAs quantum dots (QDs) grown on InAlAs/InP(0 0 1) were studied by using capacitance-voltage (C-V) analysis and photoluminescence (PL) measurements. The level positions of electrons and holes could be studied separately by using n- and p-type InAlAs matrices, respectively. The holes are found to be more confined than electrons in these kinds of dots.     

Solid phase epitaxial growth of Dy-germanide films on Ge(0 0 1) substrates

Dy thin films are grown on Ge(0 0 1) substrates by molecular beam deposition at room temperature. Subsequently, the Dy film is annealed at different temperatures for the growth of a Dy-germanide film. Structural, morphological and electrical properties of the Dy-germanide film are investigated by in situ reflection high-energy electron diffraction, and ex situ X-ray diffraction, atomic force microscopy and resistivity measurements. Reflection high-energy electron diffraction patterns and X-ray diffraction spectra show that the room temperature growth of the Dy film is disordered and there is a transition at a temperature of 300-330 °C from a disordered to an epitaxial growth of a Dy-germanide film by solid phase epitaxy. The high quality Dy₃Ge₅ film crystalline structure is formed and identified as an orthorhombic phase with smooth surface in the annealing temperature range of 330-550 °C. But at a temperature of 600 °C, the smooth surface of the Dy₃Ge₅ film changes to a rough surface with a lot of pits due to the reactions further.     

Epitaxial growth of Dy2O3 thin films on epitaxial Dy-germanide films on Ge(0 0 1) substrates

Ultra-thin films of Dy are grown on Ge(0 0 1) substrates by molecular beam deposition near room temperature and immediately annealed for solid phase epitaxy at higher temperatures, leading to the formation of DyGe_x films. Thin films of Dy₂O₃ are grown on the DyGe_x film on Ge(0 0 1) substrates by molecular beam epitaxy. Streaky reflection high energy electron diffraction (RHEED) patterns reveal that epitaxial DyGe_x films grow on Ge(0 0 1) substrates with flat surfaces. X-ray diffraction (XRD) spectrum suggests the growth of an orthorhombic phase of DyGe_x films with (0 0 1) orientations. After the growth of Dy₂O₃ films, there is a change in RHEED patterns to spotty features, revealing the growth of 3D crystalline islands. XRD spectrum shows the presence of a cubic phase with (1 0 0) and (1 1 1) orientations. Atomic force microscopy image shows that the surface morphology of Dy₂O₃ films is smooth with a root mean square roughness of 10 Å.     

32 nm node BEOL integration with an extreme low-k porous SiOCH dielectric k = 2.3

A 32 nm node BEOL integration scheme is presented with 100 nm metal pitch at local and intermediate levels and 50 nm via size through a M1-Via1-M2 via chain demonstrator. To meet the 32 nm RC performance specifications, extreme low-k (ELK) porous SiOCH k = 2.3 is introduced at line and via level using a Trench First Hard Mask dual damascene architecture. Parametrical results show functional via chains and good line resistance. Integration validation of ELK porous SiOCH k = 2.3 is investigated using a multi-level metallization test vehicle in a 45 nm mature generation.     

Experimental study and analysis of corner compensation structures for CMOS compatible bulk micromachining using 25 wt% TMAH

In the present work, most common compensation structures (〈1 1 0〉 squares and 〈1 0 0〉 bars) have been used for convex corner compensation with 25 wt% TMAH-water solution at 90±1 °C temperature. Etch flow morphology and self-align properties of the compensating structures have been investigated. For 25 wt% TMAH water solution {3 1 1} plane is found to be responsible for corner undercutting, which is the fast etch plane. Etch-front-attack angle is measured to be 24°. Generalized empirical formulas are also discussed for these compensation structures for TMAH-water solution. 〈1 1 0〉 square structure protects mesa and convex corner and is the most space efficient compared to other compensation structures, but unable to produce perfect convex corner as 〈1 0 0〉 bar type structures. Both the 〈1 0 0〉 bar structures provide perfect convex corners, but 〈1 0 0〉 wide bar structure is more space efficient than the 〈1 0 0〉 thin bar structure. Implications of these compensation structures with realization of accelerometer structure have also been discussed. A modified quad beam accelerometer structure has been realized with these compensation structures using 25 wt% TMAH.     

Growth mechanism of iron nanoparticles on (0 0 0 1) sapphire wafers

Laser ablation of a high purity (99.7%) iron target was used to accomplish the depositions of iron nanoparticles on the (0 0 0 1) face of single crystal sapphire wafers. The nanoparticles were characterized in situ by means of X-ray photoelectron spectroscopy (XPS). The growth mechanism was determined by applying the QUASES-Tougaard methodology to the extended part of the background intensity of the Fe KMM peak in XPS spectra. The heights of nanoparticles obtained are between 3.5 and 6.5 nm. In the first 150 laser pulses, the height of the nanoparticles remained constant while the coverage was increased.     

Crystalline orientation dependence of electrical properties of Mn Germanide/Ge(1 1 1) and (0 0 1) Schottky contacts

We have investigated the crystalline orientation dependence of the electrical properties of Mn germanide/Ge(1 1 1) and (0 0 1) Schottky contacts. We prepared epitaxial and polycrystalline Mn₅Ge₃ layers on Ge(1 1 1) and (0 0 1) substrates, respectively. The Schottky barrier height (SBH) estimated from the current density-voltage characteristics for epitaxial Mn₅Ge₃/Ge(1 1 1) is as low as 0.30 eV, while the SBH of polycrystalline Mn₅Ge₃/Ge(0 0 1) is higher than 0.56 eV. On the other hand, the SBH estimated from capacitance-voltage characteristics are higher than 0.6 eV for both samples. The difference of these SBHs can be explained by the local carrier conduction through the small area with the low SBH regions in the epitaxial Mn₅Ge₃/Ge(1 1 1) contact. This result suggests the possibility that the lowering SBH takes place due to Fermi level depinning in epitaxial germanide/Ge(1 1 1) contacts.     

Compact modeling of 0.35 μm SOI CMOS technology node for 4 K DC operation using Verilog-A

Compact modeling of MOSFETs from a 0.35 μm SOI technology node operating at 4 K is presented. The Verilog-A language is used to modify device equations for BSIM models and more accurately reproduce measured DC behavior, which is not possible with the standard BSIM model set. The model presented exhibits convergent behavior and is shown to be experimentally accurate at 4 K. No design tool currently in place exhibits convergence and/or accuracy over this range. The Verilog-A approach also allows the embedding of nonlinear length, width and bias effects into BSIM calculated curves beyond those that can be achieved by the use of different BSIM parameter sets. Nonlinear dependences are necessary to capture effects particular to 4 K behavior, such as current kinks. The 4 K DC behavior is reproduced well by the compact model and the model seamlessly evolves during simulation of circuits and systems as the simulator encounters SOI MOSFETs with different lengths and widths. The incorporation of various length/width and bias dependent effects into one Verilog-A/BSIM4 library, therefore, produces one model for all sets of devices called up in a given product design kit (PDK) for this technology node.     

GaAs substrate orientation dependence of resonant quasi-level lifetime in 2D-2D InGaAs/GaAs resonant tunneling devices

Resonant quasi-level lifetime of the lowest quasi-bound state localized within the quantum well region of a InGaAs/GaAs double barrier resonant tunneling structure have been analytically calculated for three different GaAs substrate orientations such as (0 0 1), (3 1 1)A and (1 1 1)A. The calculation is based on the solution of the time-independent Schrödinger equation and takes into account the effective mass changes between the well and barrier materials. A significant dependence of the ground state energy and its associated lifetime on the effective masses of the well and barrier layers, indium concentration in the well In_xGa_1−xAs material, which is associated to the barrier height, and GaAs substrate orientation has been observed. We believe that the structure grown on GaAs (1 1 1)A substrate is more useful for developing new resonant tunneling two-dimensional (2D) devices. Finally, the coupling effect between transverse and longitudinal wave vector has also been investigated. With increasing the transverse wave vector the lowest energy and its associated lifetime decrease and this for the different GaAs substrate orientations.     

Design of Sub-1 mW CMOS LC VCO based on current reused topology with Q-enhancement and body-biased technique

A CMOS LC voltage controlled oscillator (VCO) based on current reused topology with low phase noise and low power consumption is presented for IEEE 802.11a (Seller et al. A 10 GHz distributed voltage controlled oscillator for WLAN application in a VLSI 65 nm CMOS process, in: IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 3–5 June, 2007, pp. 115–118.) application. The chip1 is designed with the tail current-shaping technique to obtain the phase noise −116.1 dBc/Hz and power consumption 3.71 mW at the operating frequency 5.2 GHz under supply voltage 1.4 V. The second chip of proposed VCO can achieve power consumption Sub 1 mW and is still able to maintain good phase noise. The current reused and body-biased architecture can reduce power consumption, and better phase noise performance is obtained through raising the Q value. The measurement result of the VCO oscillation frequency range is from 5.082 GHz to 5.958 GHz with tuning range of 15.8%. The measured phase noise is −115.88 dBc/Hz at 1 MHz offset at the operation frequency of 5.815 GHz. and the dc core current consumption is 0.71 mA at a supply voltage of 1.4 V. Its figure of merit (FOM) is −191 dBc/Hz. Two circuits were taped out by TSMC 0.18 μm 1P6M process.     

Behaviour of CPW and TFMS lines at high temperature for RF applications in sub-45 nm nodes

Coplanar waveguide (CPW) and thin film microstrip (TFMS) lines integrating porous ultra low-k as inter-metal dielectric layers (k = 2.5) and copper as metal, are for the first time experimentally measured up to 110 GHz and under different temperature conditions, up to 200 °C. The extracted attenuation and propagation coefficients of those transmission lines are compared to simulations performed with MAGWEL software, a frequency domain 3-D Maxwell solver. Based on the characterization results some guidelines related to interconnect design are presented for future applications.     

Origin of electron mobility enhancement in (1 1 1)-oriented InGaAs channel metal-insulator-semiconductor field-effect-transistors

Electrical and physical characteristics of the Al₂O₃/InGaAs interfaces with (1 1 1)A and (1 0 0) orientations were investigated in an attempt to understand the origin of electron mobility enhancement in the (1 1 1)A-channel metal-insulator-semiconductor field-effect-transistor. The (1 1 1)A interface has less As atoms of high oxidation states as probed by X-ray photoelectron spectroscopy. The electrical measurements showed that energy distribution of the interface traps for the (1 1 1)A interface is shifted toward the conduction band as compared to that for the (1 0 0) interface. Laterally-compressed cross-section transmission electron microscopy images showed that the characteristic lengths of the interface roughness are different between the (1 1 1)A and (1 0 0) interfaces. The contributions of the Coulomb and roughness scattering mechanisms are discussed based on the experimental results.     

NiSi contact metallization using electroless Ni deposition on Pd-activated self-assembled monolayer (SAM) on p-type Si(1 0 0)

In this paper we describe a method to form NiSi contacts using electroless plating of Nickel or Ni alloy on Pd activated self-assembled monolayer (SAM) on p-type Si(1 0 0). Such method allows uniform deposition of very thin, <30 nm, Ni or Ni alloy films. Clean, oxide free, Si substrate was covered with aminopropyltriethoxysilane (APTES) self-assembled monolayer. The surface was activated with Pd-citrate solution followed by electroless plating. The samples were annealed for 1 h in vacuum (∼10⁻⁶ Torr) forming the silicide layer. The annealing temperatures were 400 °C for NiP alloy and 500 °C for NiPW alloy. X-ray diffraction (XRD) measurement confirmed the presence of NiSi phase after annealing. The silicides material properties were characterized using secondary electron microscopy (SEM) analysis, X-ray diffraction (XRD) and X-ray photon spectroscopy (XPS) profiling. The results are reported and summarized.     

Performance of (1 1 0) p-channel SOI-MOSFETs fabricated by deep-amorphization and solid-phase epitaxial regrowth processes

The impact of local deep-amorphization (DA) and subsequent solid-phase epitaxial regrowth (SPER) are studied for the co-integration of devices with hybrid surface orientation. Thin-body p-channel transistors with 20 nm thick film and HfO₂ gate insulator/metal gate along several directions on a (1 1 0) substrate were fabricated and characterized. No deterioration of transconductance or threshold voltage was induced by DA/SPER process. Device co-integration using DA/SPER process is therefore a realistic option. 〈1 1 0〉 channel on (1 1 0) SOI film yields a 200% gain on the current for the (1 0 0) surface orientation. However, the benefit of it decreases with the channel length.     

FinFET based SRAM bitcell design for 32 nm node and below

The methodology of designing FinFET bitcell is presented in detail. Determination of Fin configuration (i.e., Fin thickness, space, height, and number) in the bitcell involves consideration of both layout and electrical optimization. Once optimized through the proposed method, FinFET bitcell can provide higher cell current, lower leakage current and much lower V_ccmin with smaller bitcell area, as compared to planar bitcell, which allows continuous scaling of SRAM bitcell <0.1 μm² below 32 nm node.     

Studies of Ti- and Ni-germanide Schottky contacts on n-Ge(1 0 0) substrates

In this study, we investigated fabrication and characteristics of germanides Schottky contacts on germanium. Ti- and Ni-germanides were fabricated on n-Ge(1 0 0) substrates by sputtering metal Ti or Ni on Ge followed by a furnace annealing. The influence of annealing temperature on the electrical properties of Ti- and Ni-germanide on n-Ge(1 0 0) substrates was investigated. The low temperature ∼300 °C annealing helped to obtain the optimized Schottky contact characteristics in both Ti-germanide/Ge and Ni-germanide/Ge substrates contacts. The well-behaved Ti-germanides/n-Ge Schottky contact with 0.34 eV barrier height was obtained by using a 300 °C annealing process.     

Yttrium silicide formation and its contact properties on Si(1 0 0)

Yttrium silicide formation and its contact properties on Si(1 0 0) have been studied in this paper. By evaporating a yttrium metal layer onto Si(1 0 0) wafer in conventional vacuum condition and rapid thermal annealing, we found that YSi_2-x begins to form at 350 °C, and is stable to 950 °C. Atomic force microscopy characterization shows the pinholes formation in the formed YSi_2-x film. By current-voltage measurement, the Schottky barrier height (SBH) of YSi_2-x diode on p-type Si(1 0 0) was shown to be between 0.63 and 0.69 eV for annealing temperature from 500 to 900 °C. By low temperature current-voltage measurement, the SBH of YSi_2-x diode on n-type Si(1 0 0) was directly measured and shown to be 0.46, 0.37, 0.32 eV for annealing temperature of 500, 600, and 900 °C, respectively, and possibly even lower for annealing at 700 or 800 °C.