Electroluminescence from Au/Si/SiO2/p-Si structure

Si/SiO₂ films have been grown using the two-target alternation magnetron sputtering technique. The thickness of the SiO₂ layer in all the films was 8 nm and that of the Si layer in five types of the films ranged from 4 to 20 nm in steps of 4 nm. Visible electroluminescence (EL) has been observed from the Au/Si/SiO₂/p-Si structures at a forward bias of 5 V or larger. A broad band with one peak 650–660 nm appears in all the EL spectra of the structures. The effects of the thickness of the Si layer in the Si/SiO₂ films and of input electrical power on the EL spectra are studied systematically.     

Layer-by-Layer Analysis of the Thickness Distribution of Silicon Dioxide in the Structure SiO<Subscript>2</Subscript>/Si(111) by Inelastic Electron Scattering Cross-Section Spectroscopy

The SiO₂-concentration profile in the structure SiO₂/Si(111) is determined from experimental spectra of the cross section for the inelastic scattering of reflected electrons in the primary electron energy range from 300 to 3000 eV. The spectra are analyzed with the use of a proposed algorithm and developed computer program for simulating the spectra of the cross section for the inelastic scattering of reflected electrons for layered structures with an arbitrary number of layers, arbitrary thickness, and variable concentration of components in each layer. The best agreement between the calculated and experimental spectra is attained by varying the silicon dioxide and silicon concentrations in each layer. The results obtained can be used for profiling film-substrate structures with an arbitrary composition.     

AZ4620光刻胶的喷雾式涂胶工艺

对于一些MEMS应用,需要在形貌起伏很大的晶圆表面均匀地涂布光刻胶。喷雾式涂胶工艺满足了这些要求。研究了几种稀释的AZ4620光刻胶溶液的雾化喷涂性能,在沈阳芯源微电子设备有限公司KS-M200-1SP喷雾式涂胶机上进行了雾化喷涂试验,分别对裸片及深孔不同尺寸的晶圆进行喷雾式涂胶实验;特别研究了决定喷涂薄膜膜厚和均匀性...     

X-ray reflectivity of silicon on insulator wafers

The ability of X-ray reflectivity to analyse different silicon on insulator structures is underlined. The standard geometry with first reflection occurring at the surface gives information about the thickness, roughness, and density of the layers. Deeply buried interfaces, i.e. in between thick wafers, are analysed with a non-standard geometry (the first reflection occurs at the buried interface) and with a high-energy radiation. These two methods are, respectively, illustrated by the reflectivity measurements of (SiO₂/Si/SiO₂|bulk Si) and (bulk Si/thermal SiO₂|native SiO₂/bulk Si) bonded structures, and are explained in the framework of kinematic theory of X-ray reflectivity.     

Influence of the SiO2 layer thickness on the degradation of HfO2/SiO2 stacks subjected to static and dynamic stress conditions

The substitution of the SiO₂ gate oxide in MOS devices by a material with a high-k dielectric constant is being deeply studied nowadays to solve the problem of the leakage currents that appear with the progressive scaling of SiO₂ thickness. To improve the quality of the high-k/Si interface a very thin SiO₂ film is grown between both materials. In this work, HfO₂/SiO₂ stacks with different SiO₂ thickness were subjected to different types of stress (static and dynamic) to analyze the effect of this interfacial layer of SiO₂ in the degradation of the stack. The results show that the dielectric degradation depends on the stress applied and that the thickness of the SiO₂ interfacial layer influences the advanced stages of the stack degradation.     

Investigations on a Multiple Mask Technique to Depress Processing-Induced Damage of ICP-Etched HgCdTe Trenches

A multiple mask technique, integrating patterned silicon dioxide (SiO₂) film over patterned thick photoresist (PR) film, has been investigated as a method to perform mesa etching for device delineation and electrical isolation of mercury cadmium telluride (HgCdTe) third-generation infrared focal-plane arrays. The multiple mask technique was achieved by standard thick PR photolithography, SiO₂ film deposition to cover the thick PR patterned film, and etching the SiO₂ film at the bottom region after another photolithography process. The dynamic resistance in the zero-bias and low-reverse-bias regions of HgCdTe photodiode arrays isolated by inductively coupled plasma (ICP) etching with the multiple mask of patterned SiO₂ and patterned thick PR film underneath was improved one- to twofold compared with a simple mask of patterned SiO₂. It is suggested that the multiple mask technique is capable of maintaining high etching selectivity while reducing the side-wall processing-induced damage of ICP-etched HgCdTe trenches. The results show that the multiple mask technique is readily available and shows great promise for etching HgCdTe mesa arrays.     

Growth and electrical properties of the (Si/Ge)-on-insulator structures formed by ion implantation and subsequent hydrogen-assisted transfer

Systematic features of endotaxial growth of intermediate germanium layers at the bonding interface in the silicon-on-insulator structure consisting of buried SiO₂ layer implanted with Ge⁺ ions are studied in relation to the annealing temperature. On the basis of the results for high-resolution electron microscopy and thermodynamic analysis of the Si/Ge/SiO₂ system it is assumed that the endotaxial growth of the Ge layer occurs via formation of a melt due to enhanced segregation and accumulation of Ge at the Si/SiO₂ interface. Effect of germanium at the bonding interface on the Hall mobility of holes in silicon layers with nanometer-scale thickness is studied. It is found that the structures including the top silicon layer with the thickness 3–20 nm and incorporating germanium feature the hole mobility that exceeds by a factor of 2–3 the hole mobility in corresponding Ge-free silicon-on-insulator structures.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

Conduction mechanisms of silicon oxide/titanium oxide MOS stack structures

During the last years, high-k dielectrics have been studied intensively looking for an alternative material to replace the SiO₂ films as gate dielectric in MOS transistors. Different materials and structures have been proposed. An important concern not yet solved, is the interfacial quality between high-k materials and silicon substrate. For this reason, stack structures with SiO₂ as an interfacial layer between silicon substrate and high-k film have been studied. In this contribution we analyze the main conduction mechanism observed in SiO₂/TiO₂ MOS stack structures obtained by room temperature plasma oxidation in different conditions and reactors. Films fabricated in a parallel-plate type reactor showed better quality with low current density where thermionic conduction mechanism is predominant. In lower quality films, for example those fabricated in a barrel type equipment, the current density is higher and the conduction mechanism observed is Poole–Frenkel. Finally we show that the presence of thermionic mechanism provides a weak thickness dependence and a strong current density reduction with respect to silicon oxide MOS structures with the same equivalent oxide thickness.     

Iron nitride mask and reactive ion etching of GaN films

One of the major GaN processing challenges is useful pattern transfer. Serious photoresist mask erosion and hardening are often observed in reactive ion etching of GaN. Fine pattern transfer to GaN films using photoresist masks and complete removal of remaining photoresist after etching are very difficult. By replacing the etch mask from conventional photoresist to a sputtered iron nitride (Fe-8% N) film, which is easily patterned by wet chemical etching and is very resistive to Cl based plasmas, GaN films can be finely patterned with vertical etched sidewalls. Successful pattern transfer is realized by reactive ion etching using Cl (H) containing plasmas. CHF₃/Ar, C₂ClF₅/Ar, C₂ClF₅/Ar/O₂, SiCl₄, and CHCl₃ plasmas were used to etch GaN. The GaN etch rate is dependent on the crystalline quality of GaN. Higher crystalline quality GaN films exhibit slower etch rates than GaN films with higher dislocation and stacking fault density.     

The effects of SiO2 barrier between active layer and substrate on the performance and reliability of polycrystalline silicon thin film transistors

We report on the performance and hot carrier stress (HCS) reliability of n-channel and p-channel poly-Si thin film transisters (TFT)s fabricated on SiO₂-coated 1737 glass or bare 1737 glass substrates. Low-pressure chemical vapor deposited (LPCVD) or atmospheric pressure chemical vapor deposited (APCVD) SiO₂ with different thicknesses are used as the impurity diffusion barrier layers. We have found that the performance and HCS reliability of n-TFTs on SiO₂-coated 1737 glass are superior to those of n-TFTs on bare 1737 glass. P-TFTs on SiO₂-coated 1737 glass, on the other hand, are observed to perform better than p-TFTs on bare 1737 glass substrates, however p-TFTs on SiO₂-coated 1737 glass are seen to undergo larger improvements in their OFF current, I_OFF, following the HCS compared to p-TFTs on bare 1737 glass. We also explore the impact of SiO₂ coating thickness on the performance and HCS reliability of the TFTs. The HCS reliability of the TFTs on SiO₂-coated 1737 glass substrates is observed to depend on the SiO₂ coating thickness. This was explained in terms of a phenomenological model which involves impurity and grain boundary traps. The presence of the former type of traps is controlled by the presence or absence of the SiO₂ coating, whereas the grain boundary traps are proposed to be sensitive to compressive and tensile stresses in the SiO₂ coating layer which are, in turn, dependent on the layer's thickness.     

HF chemical etching of SiO2 on 4H and 6H SiC

Thickness and etch rate of SiO₂ films thermally grown on hexagonal SiC substrates were compared to results obtained from SiO₂/Si samples. The data confirm that profilometry and ellipsometry yield the same thickness values for oxides grown on Si and SiC. Within the accuracy of our measurements, oxides grown on different polytypes and faces of SiC etch at the same rate in a HF acid solution. The etch rate using a 50:1 H₂O:HF(50%) solution at room temperature is 0.1 nm/s and is uniform throughout the thickness of the SiO₂ films. The rate is the same as that obtained for SiO₂ grown on Si.     

Current-voltage characteristics of Al/SiO2/p-Si MOS tunnel diodes with a spatially nonuniform oxide thickness

The effect of nonuniform distribution of the insulator thickness on the behavior of Al/SiO₂/p-Si MOS tunnel structures with a (1–4)-nm-thick insulator is studied. The character and magnitude of the effect depend on the applied bias. In any conditions, the nonuniformity of the SiO₂ thickness enhances the total through currents as compared to those flowing across a uniform oxide layer of the same nominal thickness. Further, the potential of the inversion layer changes in the inversion mode. The calculations performed take into account the tunnel transport between the Si conduction band and the metal, that between the Si valence band and the metal (including in the inversion mode, the resonant transport, which is less clearly pronounced because of the thickness nonuniformity), and the band-to-band tunneling in the semiconductor.     

Scanning tunneling microscopy investigation of the microtopography of SiO2 and Si surfaces at the Si/SiO2 interface in SIMOX structures

The microtopography of silicon and silicon oxide surfaces in SIMOX structures is investigated by scanning tunneling microscopy. A method of using scanning tunneling microscopy to study Si/SiO₂ interfacial roughness is developed for this purpose. It is shown that the relief of the silicon surface in SIMOX structures is smoother than that of the oxide surface. The observed Si/SiO₂ interfacial roughness is due to oxygen ion implantation in the silicon single crystal. The roughness of the SiO₂ and Si surfaces at the Si/SiO₂ interface is compared for the standard and high-temperature oxidation of the silicon single crystal. Fiz. Tekh. Poluprovodn. 33, 708–711 (June 1999)     

GaAs structures with a gate dielectric based on aluminum-oxide layers

Different types of dielectrics obtained by low-temperature electron-beam sputtering are studied; these dielectrics include Al₂O₃ layers and Al₂O₃/SiO₂/Al₂O₃ three-layer compositions. The dependence of the electrical strength of Al₂O₃ layers on their thickness is determined. It is established that formation of the three-layer dielectric Al₂O₃/SiO₂/Al₂O₃ makes it possible to increase the range of operating voltages up to 60 V for structures with a gate electrode. It is shown that it is possible to control the density of charge carriers (holes) in the two-dimensional conduction channel of GaAs structures by changing the gate voltage when the Al₂O₃/SiO₂/Al₂O₃ structure is used as a gate dielectric.     

Direct Growth of Nanocrystalline Graphene/Graphite Transparent Electrodes on Si/SiO2 for Metal‐Free Schottky Junction Photodetectors

Conventional methods to produce graphene/silicon Schottky junctions inevitably involve graphene transfer and metal deposition, which leads to the techniques being complicated, high‐cost, and environmentally unfriendly. It is possible to directly grow hybrid nanocrystalline graphene/graphite transparent electrodes from photoresist on quartz without any catalyst. Due to the source material being photoresist, nanographene/graphite patterns can easily be made on Si/SiO₂ structures to form nanographene/silicon Schottky junctions via commercial photolithography and silicon techniques. The obtained Schottky junctions exhibit excellent properties with respect to photodetection, with photovoltage responsivity of 300 V W^‐1 at a light power of 0.2 μW and photovoltage response time of less than 0.5 s. The devices also exhibit an excellent reliability with the photovoltage deviating less than 1% when cycled over 200 times.     

Influence of insulator thickness nonuniformity on the switching of the Al/SiO2/n-Si tunnel MOS structure at reverse bias

Current-voltage characteristics of the reversely biased Al/SiO₂/n-Si MOS structure are calculated taking into account the nonuniformity of oxide thickness distribution over an area at a nominal thickness of 1–3 nm. It is known that the characteristics are S-shaped in a certain range of average SiO₂ thickness, which suggests that a device is bistable. Holding and threshold voltage shifts, caused by statistical thickness variations, were predicted. In response to electrical stress, the root-mean-square deviation of the SiO₂ thickness increases, which results in a shift of the threshold voltage to higher values. The calculations are complemented by experimental data.     

Photothermal Killing of Cancer Cells by the Controlled Plasmonic Coupling of Silica‐Coated Au/Fe2O3 Nanoaggregates

Tumor ablation by thermal energy via the irradiation of plasmonic nanoparticles is a relatively new oncology treatment. Hybrid plasmonic‐superparamagnetic nanoaggregates (50–100 nm in diameter) consisting of SiO₂‐coated Fe₂O₃ and Au (≈30 nm) nanoparticles were fabricated using scalable flame aerosol technology. By finely tuning the Au interparticle distance using the SiO₂ film thickness (or content), the plasmonic coupling of Au nanoparticles can be finely controlled bringing their optical absorption to the near‐IR that is most important for human tissue transmittance. The SiO₂ shell facilitates also dispersion and prevents the reshaping or coalescence of Au particles during laser irradiation, thereby allowing their use in multiple treatments. These nanoaggregates have magnetic resonance imaging (MRI) capability as shown by measuring their r2 relaxivity while their effectiveness as photothermal agents is demonstrated by killing human breast cancer cells with a short, four minute near‐IR laser irradiation (785 nm) at low flux (4.9 W cm^‐2).     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.     

The effects of gamma irradiation on low-pressure chemical-vapor-deposited silicon dioxide metal-oxide-silicon structures

The effects of gamma irradiation on as-deposited, oxygen-annealed, and dual-dielectric gate (undoped polysilicon/oxide) low-pressure chemical-vapor-deposited (LPCVD) silicon dioxide (SiO₂) metal-oxide-silicon (MOS) structures were investigated. As-deposited LPCVD SiO₂ MOS structures exhibit the largest shift in flatband voltage with gamma irradiation. This is most likely due to the large number of bulk oxide traps resulting from the nonstochiometric nature of as-deposited LPCVD SiO₂. Dual-dielectric (undoped polysilicon/annealed LPCVD SiO₂) MOS structures exhibit the smallest shift in flatband voltage and increase in interface state density compared to as-deposited and oxygen-annealed LPCVD SiO₂ MOS structures. The interface state density of dual-dielectric MOS structures increases from 5 × 10¹⁰ eV cm⁻² to 2–3 × 10¹¹ eV cm⁻² after irradiation to a gamma total dose level of 1 Mrads(Si). This result suggests that the recombination of atomic hydrogen atoms with silicon dangling bonds, either along grain boundaries or in crystallites of the undoped polysilicon layer in dual-dielectric (undoped polysilicon/annealed LPCVD SiO₂) MOS structures, probably reduces the number of atomic hydrogen atoms reaching the Si/SiO₂ interface to generate interface states.