A 130-MHz 8-b CMOS video DAC for HDTV applications

In order to achieve monotonicity and a high-speed performance, a current-cell matrix configuration and a parallel decoding circuit with one-stage latches have been used. A deglitching circuit has been introduced in the decoding stages to guarantee a low glitch energy. P-channel devices used as current sources ensure a low noise level and a ground-referenced voltage output in a doubly terminated 75-Ω transmission line. Experimental results have shown that the maximum conversion rate is 130 MHz and the integral and differential linearity errors are less than 0.5 LSB. The maximum glitch energy is 50 pS-V. The DAC has been developed in a 1-μm digital/analog CMOS technology. The entire circuit dissipates 150 mW at a 130-MHz conversion rate while operating from a single 5-V power supply     

A cyclic A/D converter that does not require ratio-matchedcomponents

The circuit configuration of a cyclic analog-to-digital (A/D) converter using switched-capacitor techniques is described. The analog portion of the circuit consists of two operational amplifiers, four capacitors, and ten switches regardless of the number of bits per sample converted, and completes an n-bit conversion in 3n clock cycles. The conversion characteristics are inherently insensitive both to capacitor ratio and to amplifier offset voltage. The circuit, therefore, can be realized in a small die area. The effects of finite amplifier gain and switch charge injection on the conversion accuracy are discussed. A prototype chip has been fabricated in a 2-μm CMOS technology operating on a single 5-V supply. When it is operated as an 8-bit converter at a sampling rate of 8 kHz, the maximum conversion error is 0.2 LSB (least-significant bit) for differential nonlinearity and 0.5 LSB for integral nonlinearity. The die area measures 0.79 mm²     

一种用于半并行A/D转换器的比较器设计

简要介绍了半并行结构的A/D转换器原理。针对该结构的A/D转换器,提出了一种能自动校零、迟滞、全差分输入及多级前置放大的比较器。解决了输入失调电压、噪声环境下单转换、电荷注入、带宽、转换速度等问题。给出了应用该比较器的0.6μm CMOS半并行A/D转换器的性能。结果表明,设计的比较器能使丰并行ADC的DNL和INL小于±0.5 LSB,SNR大于48dB。     

一种用于数模转换器的电流-电压转换电路

介绍了一种用于数模转换器的电流 电压转换电路。在数模转换器的负载电阻片内集成的情况下 ,利用文中提出的电流 电压转换电路 ,数模转换器实现了要求的宽摆幅电平输出 (全“0”输入时 ,输出低电平 - 3V ;全“1”输入时 ,输出高电平 3 5V)。整个数模转换器电路用 1 2 μm双层金属双层多晶硅n阱CMOS工艺实现。其积分非线性误差为 0 4 5个最低有效位 (LSB) ,微分非线性误差为 0 2LSB ,满摆幅输出的建立时间小于 1μs。该数模转换器使用± 5V电源 ,功耗约为 30mW ,电路芯片面积为 0 4 2mm2 。     

A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bitsat Nyquist

A CMOS subranging analog-to-digital converter (ADC) incorporates several features to enhance performance and reduce power dissipation. The combination of an extended settling period for the fine references, absolute-value signal processing, and interpolation in the comparator banks alleviates the principal speed-limiting operation. A front-end sample-and-hold amplifier (SHA) provides sustained dynamic performance at high input frequencies and performs single-ended to differential conversion with a signal gain of two and with low distortion. The SHA holds its differential output for a full clock cycle while it simultaneously samples the next single-ended input, thereby allowing it to drive two comparator banks on consecutive clock phases. The remaining analog circuits are implemented in a fully differential manner. The use of pipelining allows every input sample to be processed by the same channel, thereby avoiding the use of ping-pong techniques, while providing a conversion latency of only two clock cycles. The dynamic performance with a single-ended input approaches that of an ideal ill-bit ADC, typically providing 9.7 effective bits for low input frequencies and 9.5 bits at Nyquist. This performance level is comparable to the best reported for 10-bit CMOS ADC's with differential inputs and significantly better than those with single-ended inputs. The typical maximum differential nonlinearity is ±0.4 LSB, and the maximum integral nonlinearity is ±0.55 LSB without trimming or calibration. With an ADC power of 55 mW plus an SHA power of 20 mW from a 5-V supply, the active area is 1.6 mm² in a 0.5-μm double-poly, double-metal CMOS technology     

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

In this paper, a 10-bit 1-GSample/s current-steering CMOS digital-to-analog (D/A) converter is presented. The measured integral nonlinearity is better than ±0.2 LSB and the measured differential nonlinearity lies between -0.08 and 0.14 LSB proving the 10-bit accuracy. The 1-GSample/s conversion rate has been obtained by an, at transistor level, fully custom-designed thermometer decoder and synchronization circuit. The layout has been carefully optimized. The parasitic interconnect loads have been estimated and have been iterated in the circuit design. A spurious-free dynamic range (SFDR) of more than 61 dB has been measured in the interval from dc to Nyquist. The power consumption equals 110 mW for a near-Nyquist sinusoidal output signal at a 1-GHz clock. The chip has been processed in a standard 0.35-μm CMOS technology and has an active area of only 0.35 mm²     

Nyquist电流型7位20MHz采样率CMOS数模转换器

介绍了一种高速7位DAC的设计及芯片测试结果,该DAC选取高5位单位电流源,低2位二进制电流源的分段结构。考虑了电流源匹配、毛刺降低以及版图中误差补偿等方面的问题来优化电路。流片采用0.35μmChartered双层多晶四层金属工艺,测试结果表明在20 MH z的采样频率下,微分非线性度和积分非线性度分别小于±0.2 LSB和±0.35 LSB。该DAC的满幅建立时间是20 ns,芯片面积为0.17 mm×0.23 mm。电源电压为3.3 V,功耗为3 mW。     

A 10 bit Current-Mode CMOS A/D Converter with a Current Predictor and a Modular Current Reference

This paper describes a 10 bit CMOS current-mode A/D converter with a current predictor and a modular current reference circuit. A current predictor and a modular current reference circuit are employed to reduce the number of comparator and reference current mirrors and consequently to decrease a power dissipation. The 10 bit current-mode A/D converter is fabricated by the 0.6 m n-well double poly/triple metal CMOS technology. The measurement results show the input current range of 16–528 A, DNL and INL of ±0.5 LSB and ±1.0 LSB, conversion rate of 10 M samples, and power dissipation of 94.4 mW with a power supply of 5 V. The effective chip area excluding the pads is 1.8 mm×2.4 mm.     

An 80-MHz 8-bit CMOS D/A converter

A high-speed 8-bit D/A converter has been fabricated in a 2-/spl mu/m CMOS technology. In order to achieve high accuracy, a current-cell matrix configuration and a switching sequence called symmetrical switching have been used. The mismatch problem of small-size transistors has been relaxed by this matrix configuration. The linearity error caused by an undesirable current distribution of the current sources has been reduced by symmetrical switching. A high-speed decoding circuit and a fast-setting current source have been developed. The experimental results show that the maximum conversion rate is 80 MHz, a typical DC integral linearity error is 0.38 LSB, a typical DC differential linearity error is 0.22 LSB, and the maximum power consumption is 145 mW. The chip size is 1.85 mm/spl times/2.05 mm.     

Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit

This paper describes an 8-bit 125 Mhzlow-powerCMOS fully-foldinganalog-to-digital converter(ADC).A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm~2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.     

A 10-b 125-MHz CMOS digital-to-analog converter (DAC) withthreshold-voltage compensated current sources

This paper describes a 10-b high-speed COMS DAC fabricated by 0.8-μm double-poly double-metal CMOS technology. In the DAC, a new current source called the threshold-voltage compensated current source is used in the two-stage current array to reduce the linearity error caused by inevitable current variations of the current sources. In the two-stage weighted current array, only 32 master and 32 slave unit current sources are required. Thus silicon area and stray capacitance can be reduced significantly. Experimental results show that a conversion rate of 125 MHz is achievable with differential and integral linearity errors of 0.21 LSB and 0.23 LSB, respectively. The power consumption is 150 mW for a single 5-V power supply. The rise/fall time is 3 ns and the full-scale settling time to ±1/2 LSB is within 8 ns. The chip area is 1.8 mm×1.0 mm     

一种应用于CMOS图像传感器的片上内插式ADC设计

设计了一种用于1024×1024CMOS图像传感器的内插式模数转换器（ADC）结构。转换采用并行处理方式,采用内插式结构,与流水线ADC相比速度更快。电路采用失调纠正技术和衬底驱动技术设计了1个低失调电压的前置全差分两级跨导运算放大器（OTA）,PMOS管作为电阻产生与锁存阈值电压相交的基准电压,具有较高的精度。基于0．35μmCMOS工艺的仿真结果表明,该ADC的DNL=0．45LSB,INL=0．65LSB,可以满足CMOS图像传感器芯片级ADC的高速高精度要求。     

A low glitch 10-bit 75-MHz CMOS video D/A converter

A low glitch 10-bit 75-MHz CMOS current-output video digital-to-analog Converter (DAC) for high-definition television (HDTV) applications is described. In order to achieve monotonicity and low glitch, a special segmented antisymmetric switching sequence and an innovative asymmetrical switching buffer have been used. The video DAC has been fabricated by using 0.8 μm single-poly double-metal CMOS technology. Experimental results indicated that the conversion rate is above 75 MHz, and nearly 50% of samples have differential and integral linearity errors less than 0.24 LSB and 0.6 LSB, respectively. The glitch has been reduced to be less than 3.9 pV·s and the settling time within ±0.1% of the final value is less than 13 ns. The video DAC is operated by a single 5 V power supply and dissipates 1.70 mW at 75 MHz conversion rate (140 mW in the DAC portion). The chip size of video DAC is 1.75 mm×1.2 mm (1.75 mm×0.7 mm for the DAC portion)     

一种低功耗嵌入式14位400MHz数模转换器

设计了一个14位刷新频率达400MHz,用于高速频率合成器的低功耗嵌入式数模转换器。该数模转换器采用5+4+5分段式编码结构,其电流源控制开关输出驱动级采用归零编码以提高DAC动态特性。该数模转换器核采用0.18μm1P6M混合信号CMOS工艺实现,整个模块面积仅为1.1mm×0.87mm。测试结果表明,该DAC模块的微分非线性误差是-0.9～+0.5LSB,积分非线性误差是-1.4～+1.3LSB,在400MHz工作频率下,输出信号频率为80MHz时的无杂散动态范围为76.47dB,并且功耗仅为107.2mW。     

一种用于时延积分CMOS图像传感器的10 bit全差分双斜坡模数转换器

为了满足时间延时积分(TDI)CMOS图像传感器转换全差分信号的需要,同时符合列并行电路列宽的限制,该文提出并实现了一种10 bit全差分双斜坡模数转换器(ADC)。在列并行单斜坡ADC的基础上,采用2个电容的上极板对差分输入进行采样,电容下极板接2个斜坡输出完成量化。基于电流舵结构的斜坡发生器同时产生上升和下降斜坡,2个斜坡的台阶电压大小相等。该电路使用SMIC 0.18 μm CMOS工艺设计实现,ADC以19.49 kS/s的采样频率对1.32 kHz的输入进行采样,仿真得到无杂散动态范围和有效位数分别为87.92 dB和9.84 bit。测试显示该ADC的微分非线性误差和积分非线性误差分别为–0.7/+0.6 LSB和–2.6/+2.1 LSB。     

一种基于65 nm CMOS工艺的10位10 MS/s SAR ADC

基于SMIC 65 nm CMOS工艺,设计了一种10位10 MS/s逐次逼近型模数转换器(SAR ADC)。采用全差分的R-C组合式DAC网络结构进行设计,提高了共模噪声抑制能力和转换精度。与全电容结构相比,R-C组合式DAC网络结构有效减小了版图面积。DAC中各开关的导通采用对称的开关时序,使比较器差分输入的共模电平保持为固定值,降低了比较器的失调电压,提高了ADC的线性度。在2.5 V模拟电源电压和1.2 V数字电源电压下,使用Spectre进行仿真验证,测得DNL为0.5 LSB,INL为0.8 LSB;在输入信号频率为4.990 2 MHz,采样频率为10 MHz的条件下,测得电路的有效位数为9.63位,FOM为0.04 pJ/conv。     

An 8-bit 80-Msample/s pipelined analog-to-digital converter withbackground calibration

An 8-bit 80-Msample/s pipelined analog-to-digital converter (ADC) uses monolithic background calibration to reduce the nonlinearity caused by interstage gain errors. Test results show that the ADC achieves a peak signal-to-noise-and-distortion ratio of 43.8 dB, a peak integral nonlinearity of 0.51 least significant bit (LSB), and a peak differential nonlinearity of 0.32 LSB with active background calibration. It dissipates 268 mW from a 3 V supply and occupies 10.3 mm ² in a single-poly 0.5 μm CMOS technology     

A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging

A 2-GS/s 6-bit ADC with time-interleaving is demonstrated in 0.18-/spl mu/m one-poly six-metal CMOS. A triple-cross connection method is devised to improve the offset averaging efficiency. Circuit techniques, enabling a state-of-the-art figure-of-merit of 3.5 pJ per conversion step, are discussed. The peak DNL and INL are measured as 0.32 LSB and 0.5 LSB, respectively. The SNDR and SFDR have achieved 36 and 48dB, respectively, with 4 MHz input signal. Near Nyquist input frequencies, the SNDR and SFDR maintain above 30 and 35.5dB, respectively, up to 941 MHz. The complete ADC, including front-end track-and-hold amplifiers and clock buffers, consumes 310 mW from a 1.8-V supply while operating at 2-GHz conversion rate. The prototype ADC occupies an active chip area of 0.5 mm/sup 2/.     

An 8-bit 20-MS/s CMOS A/D converter with 50-mW power consumption

Low power consumption and small chip area (2.09 mm×2.15 mm) are achieved by introducing a new architecture to a subranging A/D converter. In this architecture, both coarse and fine A/D conversions can be accomplished. Consequently, a large number of comparators and processing circuits have been removed from the conventional subranging A/D converter. This architecture has been realized by the introduction of a chopper-type comparator with three input terminals which makes both coarse and fine comparisons by itself. The A/D converter has two 8-b sub/A/D converters which employ this new architecture, and they are pipelined to improve the conversion rate. Good experimental results have been obtained. Both the differential and the integral nonlinearity are less than ±0.5 LSB at a 20-megasample/s sample frequency. The effective resolution at 20-megasample/s sampling frequency is 7.4 b at a 1.97-MHz input frequency and 6.7 b at a 9.79-MHz input frequency. The A/D converter has been fabricated in a 1-μm CMOS technology     

A 10-bit 200-MS/s CMOS parallel pipeline A/D converter

This paper describes a 10-bit 200-MS/s CMOS parallel pipeline analog-to-digital (A/D) converter that can sample input frequencies above 200 MHz. The converter utilizes a front-end sample-and-hold (S/H) circuit and four parallel interleaved pipeline component A/D converters followed by a digital offset compensation. By optimizing for power in the architectural level, incorporating extensively parallelism and double-sampling both in the S/H circuit and the component ADCs, a power dissipation of only 280 mW from a 3.0-V supply is achieved. Implemented in a 0.5-μm CMOS process, the circuit occupies an area of 7.4 mm². The converter achieves a differential nonlinearity and integral nonlinearity of ±0.8 LSB and ±0.9 LSB, respectively, while the peak spurious-free-dynamic-range is 55 dB and the total harmonic distortion better than 46 dB at a sampling rate of 200 MS/s