A high performance 1 Mbit EPROM

A high-performance 1-Mb EPROM has been developed by utilizing advanced 1.2-/spl mu/m minimum design rule technology. The device technology used is n-channel E/D MOS. The memory cell size is 5.5/spl times/7.5 /spl mu/m and the die size is 9.4/spl times/7.2 mm. The word organization is changeable between 64K words/spl times/16 bits and 128K words/spl times/8 bits. The active power dissipation is 500 mW and the standby power dissipation is 150 mW. The access time is typically 200 ns. The programming voltage is 12-14 V and the programming pulse width is typically 1 ms/word. In order to realize such a high-density, high-speed, low power 1-Mb EPROM, 1.2-/spl mu/m minimum patterning process technology, a high-speed sense amplifier, and a high-speed decoder are used.     

An 80 ns 1 Mbit MASK ROM with a new memory cell

A high-speed 1-Mb MASK ROM incorporating a new through-hole programmed memory cell, named THOLE CELL, and a full CMOS static sense amplifier is described. The ROM has been fabricated using a double-polysilicon p-well CMOS technology. As a result of achieving a compact ROM cell that is as small as 5.2-/spl times/6.4 /spl mu/m/SUP 2/, even with relatively conservative 2.0 /spl mu/m design rules, a small die size of 7.08/spl times/7.7 mm/SUP 2/ is realized. The ROM organization is 128K/spl times/8 bit and has a typical access time of 80 ns. A typical active current of 8 mA is achieved, in spite of the fully static system. This ROM offers high speed and low power characteristics, while achieving small die size and short turnaround time.     

A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller

A 32-KB standard CMOS antifuse one-time programmable (OTP) ROM embedded in a 16-bit microcontroller as its program memory is designed and implemented in 0.18-$muhbox m$standard CMOS technology. The proposed 32-KB OTP ROM cell array consists of 4.2$muhbox m^2$three-transistor (3T) OTP cells where each cell utilizes a thin gate-oxide antifuse, a high-voltage blocking transistor, and an access transistor, which are all compatible with standard CMOS process. In order for high density implementation, the size of the 3T cell has been reduced by 80% in comparison to previous work. The fabricated total chip size, including 32-KB OTP ROM, which can be programmed via external$hboxI^2hboxC$master device such as universal$hboxI^2hboxC$serial EEPROM programmer, 16-bit microcontroller with 16-KB program SRAM and 8-KB data SRAM, peripheral circuits to interface other system building blocks, and bonding pads, is 9.9$hbox mm^2$. This paper describes the cell, design, and implementation of high-density CMOS OTP ROM, and shows its promising possibilities in embedded applications.     

用于可编程器件的MTM反熔丝特性研究

基于ONO（Oxide-Nitride-Oxide）和MTM（Metal-to—Metal）反熔丝技术的可编程存储及逻辑器件已经广泛应用于空间技术中。MTM反熔丝以其单元面积小、集成度高、反熔丝电容小和编程后电阻小等优势,更加适合深亚微米集成电路。文章通过制备MTM反熔丝单元,对单元的击穿特性和漏电性能展开研究,给出了反熔丝单元漏电流与单元尺寸的关系,对单元的编程电流和编程后的电阻值关系进行了研究,与文献[1]给出的Ron=Vf/Ip的关系基本一致。     

一种专用可重配置的FPGA嵌入式存储器模块的设计和实现

本文设计了一种满足FPGA芯片专用定制需求的嵌入式可重配置存储器模块.一共8块,每块容量为18Kbits的同步双口BRAM,可以配置成16K×1bit、8K×2bits、4K×4bits、2K×9bits、1K×18bits、512×36bits六种不同的位宽工作模式;write_first、no_change两种不同的写入模式.多个BRAM还可以通过FPGA中互连电路的级联来实现深度或宽度的扩展.本文重点介绍实现可重配置功能的电路及BRAM嵌入至FPGA中的互连电路.采用SMIC 0.13μm 8层金属CMOS工艺,产生FDP-II芯片的完整版图并成功流片,芯片面积约为4.5mm×4.4mm.运用基于March C+算法的MBIST测试方法,软硬件协同测试,结果表明FDP-II中的BRAM无任何故障,可重配置功能正确,证实了该存储器模块的设计思想.     

A 1-Mbit CMOS dynamic RAM with a divided bitline matrix architecture

A 1-Mb dynamic RAM has been fabricated using 1.2-/spl mu/m double-level metal CMOS technology. A novel divided bitline matrix architecture allows the conventional double-polysilicon planar memory cell to be used without sacrificing signal-to-noise (S/N) ratio or die efficiency. Optimized for high bandwidth, the device uses static column circuitry and a 256K/spl times/4 organization to achieve data rates >180 Mb/s at worst-case voltage and temperature conditions. The 5.97-mm/spl times/11.4-mm die incorporates a flexible laser blown fuse link redundancy scheme which can repair a wide variety of fabrication defects. Typical row access and cycle times are 85 and 190 ns, respectively, achieving >21-Mb/s bandwidth in the non-optimized row access mode. Although some DC power is dissipated in static circuitry, active power consumption has been kept to 225 mW (45 mA), and standby power consumption has been reduced to 2.5 mW (0.5 mA).     

Characterization of single-sided gate-to-drain non-overlapped implantation nMOSFETs for multi-functional non-volatile memory applications

Novel single-sided non-overlapped implantation (SNOI) nMOSFETs are characterized for their capability of multiple programmable memory functions. These devices can be operated as mask ROMs, EEPROMs or anti-fuses by using a pure logic processing. To function as mask ROMs, they can be mask-coded with the source drain extension (SDE) implantation. They can also be used as EEPROM devices by trapping charges in the side-wall nitride spacers. Furthermore, SNOI devices can be used as antifuses by introducing the punch-through stress at the drain side. The SNOI devices were successfully demonstrated for antifuse operations with an extremely high program/initial readout current ratio exceeding 10⁹ and a program speed as high as 1 μs. These novel SNOI devices not only provide non-volatile memory solutions in standard CMOS processing but also give a flexible choice among mask ROM, antifuse and EEPROM functions.     

A 76-mm2 8-Mb chain ferroelectric memory

This paper demonstrates the first 8-Mb chain ferroelectric RAM (chain FeRAM) with 0,25-μm 2-metal CMOS technology. A small die of 76 mm² and a high average cell/chip area efficiency of 57.4 % have been realized by introducing not only chain architecture but also four new techniques: 1) a one-pitch shift cell realizes small cell size of 5.2 μm²; 2) a new hierarchical wordline architecture reduces row-decoder and plate-driver areas without an extra metal layer; 3) a small-area dummy cell scheme reduces dummy capacitor size to 1/3 of the conventional one; and 4) a new array activation scheme reduces dataline and second amplifier areas. As a result, the chain architecture with these new techniques reduces die size to 65% of that of the conventional FeRAM. Moreover a ferroelectric capacitor overdrive scheme enables sufficient polarization switching, without overbias memory cell array. This scheme lowers the minimum operation voltage by 0.23 V, and enables 2.5-V V_dd operation. Thanks to fast cell plateline drive of chain architecture, the 8-Mb chain FeRAM has achieved the fastest random access time, 40 ns, and read/write cycle time, 70 ns, at 3.0 V so far reported     

Virtual-ground sensing techniques for a 49-ns/200-MHz access time 1.8-V 256-Mb 2-bit-per-cell flash memory

Fast and accurate read operation in 1.8-V 2-bit-per-cell virtual-ground flash memories requires techniques to substantially reduce the read margin loss due to the side-leakage current and the complementary-bit disturbance. The read margin loss caused by the combination effect of these two disturbance mechanisms is serious enough to eliminate the read margin window, which is already small when the power supply voltage is about 1.8 V and when a memory cell stores 2 bits. This paper introduces for the first time the sense current recovery technique to counteract the side-leakage current effect and the differential feedback cascoded bitline control technique to minimize the complementary-bit disturbance. A 1.8-V 256-Mb 2-bit-per-cell virtual-ground flash memory employing the two techniques has been integrated using 0.13-/spl mu/m CMOS technology. These two sensing techniques are essential for the memory to achieve 49-ns initial read access and 200-MHz internal burst read access. The die size is 52 mm/sup 2/ and the cell size is 0.121 /spl mu/m/sup 2/.     

CMOS gigabit-per-second switching

An analysis and experimental results for a 600-Mb/s 1.2-μm CMOS space switch chip are provided. The high bit rate is achieved with a tree architecture, which is relatively insensitive to on-chip stray capacitance. Computer simulations indicate that bit rates in excess of 1 Gb/s are achievable with 1-μm CMOS and circuit/layout optimization. An obstacle to achieving high bit rate is crosstalk, which is primarily caused by chip packaging and not by the chip itself. Even the best discrete packaging technologies result in excessive crosstalk when 32 outputs switch simultaneously at 600 Mb/s. Tolerable crosstalk was achieved by limiting outputs to two per power supply pin. A major increase in bit rate can be obtained by switching bytes (8 b parallel) of information. This requires on-chip information storage and reclocking to maintain synchronization between the eight parallel bits. Experiments with a second-generation synchronous switch chip have demonstrated switching at 311 MB/s, which corresponds to an STS-48 rate of 2.488 Gb/s     

An antifuse EPROM circuitry scheme for field-programmable repair inDRAM

An antifuse EPROM and 3-V programming circuit has been demonstrated in an existing 0.22-μm DRAM process technology and is fully compatible with 64-Mb SDRAM specifications. The antifuse circuitry uses an internal high-voltage generator for programming and a dynamic sense and static latch scheme that appropriately enables redundant DRAM address decoders at power-up. For efficient high voltage generation, a high-voltage-tolerant capacitor structure was formed by using the high fringing capacitance available between intralevel and interlevel polysilicon and metal lines. Furthermore, the programmable EPROM element was realized without any process modifications by utilizing destructive dielectric breakdown of the thin, highly reliable oxide-nitride-oxide (ONO) dielectric in the basic DRAM cell capacitor structure. This antifuse EPROM circuit enables implementation of field-programmable DRAM features such as memory repair, output impedance matching, and data encryption     

A 126.6-mm2 AND-type 512-Mb flash memory with 1.8-Vpower supply

A 512-Mb flash memory, which is applicable to removable flash media of portable equipment such as audio players, has been developed. The chip is fabricated with a 0.18-μm CMOS process on a 126.6-mm² die, and uses a multilevel technique (2 bit/1 cell). The memory cell is AND-type, which is suitable for multilevel operation. This paper reports new techniques adopted in the 512-Mb flash memory. First, techniques for low voltage operation are described. The charge pump, control of pumps, and the reference voltage generator are improved to generate internal voltage stably for multilevel flash memory. Next, a method for reducing total memory cost in the removable flash media is described. A new operation mode named read-modify-write is introduced on the chip. This feature makes the memory system simple, because the controller does not have to track sector-erase information     

A 98 mm2 die size 3.3-V 64-Mb flash memory with FN-NORtype four-level cell

In order to realize high-capacity and low-cost flash memory, we have developed a 64-Mb flash memory with multilevel cell operation scheme. The 64-Mb flash memory has been achieved in a 98 mm² die size by using four-level per cell operation scheme, NOR type cell array, and 0.4-μm CMOS technology. Using an FN type program/erase cell allows a single 3.3 V supply voltage. In order to establish fast programming operation using Fowler-Nordheim (FN)-NOR type memory cell, we have developed a highly parallel multilevel programming technology. The drain voltage controlled multilevel programming (DCMP) scheme, the parallel multilevel verify (PMV) circuit, and the compact multilevel sense-amplifier (CMS) have been implemented to achieve 128 b parallel programming and 6.3 μs/Byte programming speed     

A 1-Mbit MRAM based on 1T1MTJ bit cell integrated with copper interconnects

A low-power 1-Mb magnetoresistive random access memory (MRAM) based on a one-transistor and one-magnetic tunnel junction (1T1MTJ) bit cell is demonstrated. This is the largest MRAM memory demonstration to date. In this circuit, the magnetic tunnel junction (MTJ) elements are integrated with CMOS using copper interconnect technology. The copper interconnects are cladded with a high-permeability layer which is used to focus magnetic flux generated by current flowing through the lines toward the MTJ devices and reduce the power needed for programming. The 25-mm/sup 2/ 1-Mb MRAM circuit operates with address access times of less than 50 ns, consuming 24 mW at 3.0 V and 20 MHz. The 1-Mb MRAM circuit is fabricated in a 0.6-/spl mu/m CMOS process utilizing five layers of metal and two layers of poly.     

A 1-Mbit BiCMOS DRAM using temperature-compensation circuittechniques

A temperature-compensation circuit technique for a dynamic random-access memory (DRAM) with an on-chip voltage limiter is evaluated using a 1-Mb BiCMOS DRAM. It was found that a BiCMOS bandgap reference generator scheme yields an internal voltage immune from temperature and V_cc variation. Also, bipolar-transistor-oriented memory circuits, such as a static BiCMOS word driver, improve delay time at high temperatures. Furthermore, the BiCMOS driver proves to have better temperature characteristics than the CMOS driver. Finally, a 1-Mb BiCMOS DRAM using the proposed technique was found to have better temperature characteristics than the 1-Mb CMOS DRAM which uses similar techniques, as was expected. Thus, BiCMOS DRAMs have improved access time at high temperatures compared with CMOS DRAMs     

A 117-mm2 3.3-V only 128-Mb multilevel NAND flash memoryfor mass storage applications

For a quantum step in further cost reduction, the multilevel cell concept has been combined with the NAND flash memory. Key requirements of mass storage, low cost, and high serial access throughput have been achieved by sacrificing fast random access performance. This paper describes a 128-Mb multilevel NAND flash memory storing 2 b per cell. Multilevel storage is achieved through tight cell threshold voltage distribution of 0.4 V and is made practical by significantly reducing program disturbance by using a local self-boosting scheme. An intelligent page buffer enables cell-by-cell and state-by-state program and inhibit operations. A read throughput of 14.0 MB/s and a program throughput of 0.5 MB/s are achieved. The device has been fabricated with 0.4-μm CMOS technology, resulting in a 117 mm² die size and a 1.1 μm² effective cell size     

The design and performance of CMOS 256K bit DRAM devices

The design and performance of CMOS 256K bit dynamic random access memory devices with 256K/spl times/1 and 64K/spl times/4 output configurations are presented. An advanced CMOS technology, with device scaling to the HMOS-III level, is used to provide effective solutions to critical device and circuit problems in DRAM design and to offer features not previously implemented in NMOS designs. The cell and die area are 70 /spl mu/m/SUP 2/ and 253 mil /spl square/ (6.3 mm /spl square/), respectively. The typical row access time is less than 100 ns. The p-channel memory array used in this design improves the memory refresh characteristics and reduces the soft error rates. The use of static and clocked CMOS circuits provides lower active power, wide operating margins, microwatt standby power, and high column data bandwidth. The 256K bit devices are designed with two output modes, namely, ripplemode and static column mode, selected by a metal mask option.     

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layoutsense amplifiers

A 16-Mb CMOS SRAM using 0.4-μm CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm² is fabricated and an address access time of 12.5 ns has been achieved     

一种基于多值RRAM的快速逻辑电路

针对移动物联网设备,提出一种基于多值RRAM的快速逻辑电路,以实现非易失性存储与快速逻辑运算。利用RRAM多值存储特性,采用Crossbar结构,实现了简单快速的译码器与高存储密度查找表,使逻辑电路具有较快的运算速度和较小的面积。基于该结构实现了4位、8位和16位的乘法器,其外围电路采用SMIC 65 nm CMOS工艺实现,而其核心多值RRAM则采用Verilog-A 模型模拟。仿真结果表明,与传统CMOS逻辑电路相比,基于多值RRAM的16位乘法器的速度提高了35.7%,面积减少了14%。     

An experimental 1-Mbit CMOS SRAM with configurable organization andoperation

A 1-Mb SRAM (static random-access memory) configurable as a 128-kb×8, 256-kb×4, or 1-Mb×1 memory featuring asynchronous operation with static-column and chip-enable-access speedup modes or synchronous operation with a fast-page (toggle) or static-column mode is described. It has been fabricated in a double-metal, double-polysilicon CMOS process with 0.7-μm geometry and special SRAM structures. The measured synchronous access of 29 ns with a fast-page mode access of 22 ns. Measured asynchronous access is 34 ns with a static-column access of 33 ns and a chip-select speedup access of 29 ns. The SRAMs six-transistor CMOS memory cell is 58.24 μm²