A folded extended window MOSFET for ULSI applications

A novel, simple, and straightforward technology, FEWMNOS, for a high-packing-density LDD CMOS device, is described. A salicide polysilicon layer, termed a window pad, is used as a window etch stop, source/drain (S/D) diffusion source, and extra sublevel interconnection layer. The reductions in layout area in transistors and in many applications including memory and ASICs (application-specific integrated circuits) are significant     

Series resistance of devices with submicrometer source/drain areas

The source-drain series resistances of devices contacted by a local interconnection technology utilizing polysilicon strapped with selective CVD tungsten were measured and compared to predictions obtained using a theoretical model. Asymmetrical devices in which the local interconnections were intentionally misaligned to the gate were fabricated to study the effects of misalignment on device characteristics. Experiments indicate that the technology is quite forgiving to the misalignment between the gate and the local interconnection     

A novel self-aligned poly-Si TFT with field-induced drain formed by the damascene Process

We have proposed and fabricated a self-aligned polysilicon thin-film transistor (poly-Si TFT) with a thick dielectric layer at the gate edges near the source and drain. A T-shaped polysilicon gate was successfully formed by the damascene process used in VLSI interconnection technology. During the on state, an inversion layer is induced by the subgate as a drain so that the on current is still high and the poly-Si region under the subgate behaves as an offset, reducing the off-state leakage current during the off-state. As the subgate dielectric becomes 3.5 times thicker than the main gate oxide, the minimum off-state leakage current of the new TFT is decreased from 1.4/spl times/10/sup -10/ to 1.3/spl times/10/sup -11/ without sacrifice of the on current. In addition, the on-off current ratio is significantly improved.     

SATPOLY: a self-aligned tungsten on polysilicon process for CMOSVLSI applications

The use of complementarily doped n⁺ and p⁺ polysilicon has been proposed for future generations of CMOS technology. The implementation of this technology requires low-resistance shunts both to reduce the overall resistance of the gate level interconnections and to short out the polysilicon p-n junctions. A process in which tungsten is chosen to provide the low-resistance shunts, with the necessary gate sidewall spacers formed before the selective deposition of tungsten, is described. A nonselective tungsten deposition process, originally developed explicitly for the implementation of direct tungsten gate MOS technology, is a key step in the formation of the spacers in the SATPOLY (self-aligned tungsten on polysilicon) process. The work function stability and the adhesion of the tungsten-polysilicon double-layer structure as a function of the polysilicon glue layer thickness have also been investigated     

Strained-Si Channel Super-Self-Aligned Back-Gate/Double-Gate Planar Transistors

We present a reproducible approach to the fabrication of super-self-aligned back-gate/double-gate n-channel and p-channel transistors with thin silicon channels and thick source/drain polysilicon regions. The device structure provides capability for scalable control of channel electrostatics, threshold variability without sacrificing source/drain series resistance, and capability of introducing strain to improve carrier transport. The separate device, circuit, and functional level back-gate access that is available through bottom interconnection also provides capability for adaptive power control and novel circuit design. Both n-channel and p-channel devices are demonstrated with the threshold tuning capability     

An Amorphous Silicon Local Interconnection (ASLI) CMOS with Self-Aligned Source/Drain and Its Electrical Characteristics

A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional ones. The electrical characteristics of this device are as good as those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3 V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.     

The effect of biased spacers on LDD MOSFET behavior

The concept of using LDD spacers that are independently biased with respect to the gate electrode is presented. It is shown that the lateral electric field is strongly influenced by the drain polysilicon spacer potential. Depending on the N^- dose, the peak substrate currents can be either enhanced or reduced by shorting the drain polysilicon spacer to the drain potential. Short-channel LDD MOSFETs have been fabricated with polysilicon LDD spacers shorted to the source and drain electrodes by titanium silicide     

A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior     

Novel self-aligned polysilicon-gate MOSFETs with polysilicon source and drain

A novel self-aligned technique is described for self-aligning a polysilicon gate in devices with polysilicon source and drain regions. The technique is demonstrated for two types of polysilicon source and drain devices. In one type of device, the polysilicon serves as the source of dopant for diffused source and drain junctions. In the second type, the polysilicon, together with an underlying interfacial oxide, forms a tunneling CIS (conductor-thin insulator-semiconductor) structure. The characteristics of devices of both types fabricated under almost identical conditions using the new self-alignment technique are compared.     

Quadruply Self-Aligned MOS (QSA MOS) -- A New Short-Channel High-Speed High-Density MOSFET for VLSI

A new device named Quadruply Self-Aligned (QSA) MOS is proposed to overcome speed and density limits of conventional scaled-down MOS VLSI circuits. This device includes four mutually selfaligned areas: narrow poly-Si gate, shallow-source/drains to eliminate short-channel effects, deep junctions for highconductance, and specific contacts to afford efficient metal interconnection. To get these four regions to register, the gate pattern is first defined followed by undercutting of the polysilicon, anisotropic reactive ion etching of the gate oxide, and ion implantation into the source/drain regions. The device has been fabricated and its proper operation has been demonstrated. Because of its short-channel length and small gate-drain overlap capacitance, this device allows the design of high-speed VLSI circuits using high-conductive interconnects. Also, the self-aligned process allows the design of high-density VLSI circuits. It is shown that the design of the ultimate 3F X 2F cell (6 /spl mu/m/sup 2//cell, namely 3 X 2 mm/sup 2//1 Mbit in 1-/spl mu/m rule) and the 4F pitch sense amplifier in dynamic MOS RAM are feasible using this QSA technology. (F is the minimum feature size.)     

A 10-s doping technology for the application of low-temperaturepolysilicon TFTs to giant microelectronics

A bucket-type high-density (0.25-1.2-mA/cm²) low-energy (500-2000 V) ion source was utilized for high-speed phosphorus doping directly into a thin polysilicon layer without cap SiO₂. Doping gas with He dilution was selected to reduce etching of polysilicon film. Excimer laser (XeCl, 8 mm×8 mm) pulse annealing was introduced to activate effectively the doped impurity. The combination of these techniques provided a practically low sheet resistance for the TFT source, drain, and gate with a short time doping. The low-temperature polysilicon TFT fabricated with a doping time of 10 s had characteristics comparable to those of that fabricated by a longer time doping or conventional ion implantation, showing the practicality of this technology and its promise for giant microelectronics     

LDD MOSFETs using disposable sidewall spacer technology

A technology for fabricating lightly doped drain (LDD) MOSFET devices based on disposable sidewall spacers is presented. Using a thin polysilicon buffer layer between the low-temperature oxide (LTO) sidewall spacers and the oxidized polysilicon gate, a single masking step can be used to form the n^- and n⁺ or p^- and p⁺ source/drain implants for the NMOS and PMOS devices, respectively. In addition, the LTO sidewall spacers may be removed by a wet HF strip, thus minimizing additional damage to the gate oxide that may be caused by reactive ion etch removal. The disposable sidewall spacer technology is easily adaptable to a CMOS process as demonstrated by the fabrication of a 4 K×4 SRAM circuit using a conventional 1.5-μ CMOS technology     

Quadruply self-aligned MOS (QSA MOS)—A new short-channel high-speed high-density MOSFET for VLSI

A new device named Quadruply Self-Aligned (QSA) MOS is proposed to overcome speed and density limits of conventional scaled-down MOS VLSI circuits. This device includes four mutually self-aligned areas: narrow poly-Si gate, shallow-source/drains to eliminate short-channel effects, deep junctions for high conductance, and specific contacts to afford efficient metal interconnection. To get these four regions to register, the gate pattern is first defined followed by undercutting of the polysilicon, anisotropic reactive ion etching of the gate oxide, and ion implantation into the source/drain regions. The device has been fabricated and its proper operation has been demonstrated. Because of its short-channel length and small gate-drain overlap capacitance, this device allows the design of high-speed VLSI circuits using high-conductive interconnects. Also, the self-aligned process allows the design of high-density VLSI circuits. It is shown that the design of the ultimate 3F × 2F cell (6 µm²/cell, namely 3 × 2 mm²/1 Mbit in 1-µm rule) and the 4F pitch sense amplifier in dynamic MOS RAM are feasible using this QSA technology. (F is the minimum feature size.)     

复合多晶硅栅LDMOS的设计

提出了一种应用于射频领域的复合多晶硅栅LDMOS结构,并提出了具体的工艺实现方法。此结构采用栅工程的概念,设计的栅由S-gate和D-gate两块并列组成,S-gate用高功函数P型多晶硅材料,D-gate用低功函数N型多晶硅材料。MEDICI模拟结果表明,该结构能够降低沟道末端和漏极附近的最高电场强度,提高器件的跨导和截止频率;同时,还能够提高器件的击穿电压,并减小器件的热载流子效应。     

Partially depleted SOI NMOSFET's with self-aligned polysilicon gateformed on the recessed channel region

A new SOI NMOSFET with a “LOCOS-like” shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, we developed a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3 μm SOI devices with V_z of 0.773 V and T_ox=7.6 nm is 360 μA/μm at V_GS=3.5 V and V _DS=2.5 V. Improved breakdown characteristics were obtained and the BV_DSS (the drain voltage for 1 nA/μm of I_D at T_GS=0 V) of the device with L_eff=0.3 μm under the floating body condition was as high as 3.7 V     

Overlaid CMOS

A CMOS structure where the source and drain terminals of the MOSFETs are in polysilicon overlaid on top of a thick oxide and the channel is in single-crystal silicon is described, utilising a 970°C SiH4 CVD process which simultaneously deposits epitaxial silicon on the exposed silicon substrate and polysilicon on oxide. The structure allows a more compact CMOS inverter layout and reduced source/drain parasitic capacitances.     

MOSFET's with PolySilicon gates self-aligned to the field isolation and to the source and drain regions

The fabrication procedure and device characteristics of MOSFET's having a unique gate electrode structure are described. The polysilicon gate electrode of the structure is self-aligned on its ends with respect to the conductive source and drain regions, and is also self-aligned on its sides with respect to the nonconductive field oxide isolation regions. This double self-alignment feature results in a polysilicon gate electrode area that matches the channel region of the FET. Another novel feature of this "recessed-gate" device is a self-registering electrical connection between the gate and the metallic interconnection pattern. Compared to MOSFET's fabricated using more conventional methods, smaller FET's with increased packing density result from this misregistration-tolerant contacting technique and the doubly self-aligned gate electrode structure. The new FET structure may be applied to various integrated circuits such as ROM's, PLA's, and dynamic RAM's. The use of a second layer of polysilicon and the addition of a fifth masking operation yields a dynamic RAM cell of small area with a diffused storage region.     

A novel PMOS SOI polysilicon transistor

An advanced silicon-on-insulator (SOI) PMOS polysilicon transistor, featuring an inverted gate electrode and self-aligned source/drain and gate/channel regions, is developed and characterized. Selective oxidation is used to form self-aligned thin polysilicon channel regions with thicker source/drain polysilicon regions. The gate electrode is formed by a high-energy boron implant into the underlying silicon substrate. Since the gate oxide is formed over single-crystal silicon rather than polysilicon, an improvement in gate oxide integrity is possible. The resulting SOI PMOS device is suitable for high-density static random access memory (SRAM) circuit applications and exhibits excellent short-channel behavior with an on/off current ratio exceeding six orders of magnitude