Physics-based MCT circuit model using the lumped-charge modelingapproach

This paper presents a physics-based model of metal-oxide-semiconductor (MOS) controlled thyristor (MCT) using the lumped-charge modeling technique. As a relatively new power semiconductor device, little effort has been made thus far in creating an accurate model for simulation use. The only MCT model available to date is that using two bipolar transistors-a behavioral subcircuit model. This model works well for static operation, but has limitations in predicting the dynamic behavior of the device due to the omission of the internal device physics. The use of the lumped-charge modeling technique facilitates the inclusion of internal physical processes and the structural geometry of the device into the model. As a result, this technique provides a more realistic and accurate one-dimensional (1-D) model than any other presently available. This paper presents the successful implementation of the lumped-charge approach on hybrid bipolar-MOS power devices such as the MCT. Most importantly, this model is capable of predicting some dynamic soft-switching behavior of the device, which was never realizable by any SPICE-based simulators. The developed model is thoroughly verified through Saber simulation and experimentation     

Locally-Stable Macromodels of Integrated Digital Devices for Multimedia Applications

This paper addresses the development of accurate and efficient behavioral models of digital integrated circuits for the assessment of high-speed systems. Device models are based on suitable parametric expressions estimated from port transient responses and are effective at system level, where the quality of functional signals and the impact of supply noise need to be simulated. A potential limitation of some state-of-the-art modeling techniques resides in hidden instabilities manifesting themselves in the use of models, without being evident in the building phase of the same models. This contribution compares three recently-proposed model structures, and selects the local-linear state-space modeling technique as an optimal candidate for the signal integrity assessment of data links. In fact, this technique combines a simple verification of the local stability of models with a limited model size and an easy implementation in commercial simulation tools. An application of the proposed methodology to a real problem involving commercial devices and a data-link of a wireless device demonstrates the validity of this approach.      

Physics-based electron device modelling and computer-aided MMICdesign

On overview on the state of the art and future trends in physics-based electron device modelling for the computer-aided design of monolithic microwave ICs is provided. After a review of the main physics-based approaches to microwave modeling, special emphasis is placed on innovative developments relevant to circuit-oriented device performance assessment, such as efficient physics-based noise and parametric sensitivity analysis. The use of state-of-the-art physics-based analytical or numerical models for circuit analysis is discussed, with particular attention to the role of intermediate behavioral models in linking multidimensional device simulators with circuit analysis tools. Finally, the model requirements for yield-driven MMIC design are discussed, with the aim of pointing out the advantages of physics-based statistical device modeling; the possible use of computationally efficient approaches based on device sensitivity analysis for yield optimization is also considered     

An improved DC model for circuit analysis programs for submicronGaAs MESFET's

An improved submicron GaAs MESFET model is presented which is suitable for nonlinear small-signal circuit designs. The Kacprzak-Materka model, which simulates the dc characteristics of large signal devices has been modified to predict the behavior of submicron devices. In this modification the concept of a shift in threshold voltage has been introduced. It has been shown that without taking into account the shift which is caused by the submicron geometry it is not possible to predict the device characteristics. Small-signal devices of different aspect ratio have been modeled with greater accuracy than that of other models. As far as possible we have determined the model parameters from the device physics and established the advantages of this approach over terminal methods. The modified model should be a useful tool for the designing of future integrated circuits with submicron gate length MESFET's     

Coupled package-device modeling for microelectromechanical systems

Microelectromechanical systems (MEMS), by their nature as sensors and actuators, require application specific packaging. The package is the near environment of the MEMS device and hence has a direct effect on its thermal behavior, mechanical effects, environmental compatibility and contamination. Therefore, understanding the influence of the packaging on MEMS device performance is critical to a successfully coupled package-device co-design. Here, an automated package-device interaction simulator has been developed. The simulator uses separate finite element method models for both the package and the device analysis and ties the simulations together through parametric behavioral package models. This technique allows the generation of package model libraries and supports the co-design of application specific packaging and MEMS devices. In the current implementation, thermomechanical package models have been implemented. Experimental verification of the technique is demonstrated by the comparison of simulation results to the measured package strain data. Although MEMS device-package interactions are not the only systems that could benefit from this method, they are a significant application area, focused on here.     

A new approach to the theory and modeling of insulated-gate field-effect transistors

Consideration of basic charge relationships in the IGFET has led to a new formulation of the theory of the device which allows model characterization in a more general manner, and with greater accuracy, than previously achieved. The contribution of the mobile channel charge to the silicon surface potential, which is believed to have a significant influence on the device characteristics, is taken into account in this approach. Accurate device modeling is achieved over a very wide range of operation, extending from weak channel (subthreshold) to high level channel conditions. An important feature of the model is that it is expressed in terms of a constant effective channel mobility. Further, the current and charge relationships involved take the form of a single set of analytic closed-form expressions in terms of the terminal voltages for all conditions of device operation, and are thus appropriate for CAD implementation. The scope and accuracy of this approach to IGFET modeling are demonstrated by comparisons between measured and theoretical dc and small-signal characteristics for sample metal and silicon gate devices.     

Game Bot Detection Approach Based on Behavior Analysis and Consideration of Various Play Styles

An approach for game bot detection in massively multiplayer online role‐playing games (MMORPGs) based on the analysis of game playing behavior is proposed. Since MMORPGs are large‐scale games, users can play in various ways. This variety in playing behavior makes it hard to detect game bots based on play behaviors. To cope with this problem, the proposed approach observes game playing behaviors of users and groups them by their behavioral similarities. Then, it develops a local bot detection model for each player group. Since the locally optimized models can more accurately detect game bots within each player group, the combination of those models brings about overall improvement. Behavioral features are selected and developed to accurately detect game bots with the low resolution data, considering common aspects of MMORPG playing. Through the experiment with the real data from a game currently in service, it is shown that the proposed local model approach yields more accurate results.     

Integration of reactive process modeling into semiconductor technology development

Understanding the physico-chemical phenomena at play in semiconductor processing is critical in making important product development decisions. Product performance and yield for even the best-designed chips can be traced back through transistor and interconnect performance to material and structure quality resulting from complex chemical processes. Despite the importance of factoring process character into design and production decisions, no complete framework exists either to connect design ideals to process realities or to quantify the impact of process uncertainty on product performance. Hence, process, device, circuit and design decisions are all made with incomplete or imprecise information leading to sub-optimal products and inefficient use of limited resources.A software-based approach to filling the significant gap at the chemical process end of the spectrum will be described. First, a hybrid approach must be created that integrates modeling with empirical methods to overcome the insufficiency of either by itself. Second, this capability must be directly accessible by technology managers, developers and practitioners to limit the decay of its decision-making value with increasing distance from its source. Third, the impact of the uncertainty associated with assumptions and model inputs must be quantified to optimize resource allocation and minimize risk. Finally, the chemical process models must be integrated with materials models and linked to solid-state process and device models while quantifying total uncertainty.     

Interconnection of Subsystem Reduced-Order Models in the Electrothermal Analysis of Large Systems

Heat conduction in an electronic device is commonly modeled as a discretized thermal system (e.g., finite element or finite difference models) that typically uses large matrices for solving complex problems. The large size of electronic-system heat transfer models can be reduced using model reduction methods and the resulting reduced-order models can yield accurate results with far less computational costs. Electronic devices are typically composed of components, like chips, printed circuit boards, and heat sinks that are coupled together. There are two ways of creating reduced-order models for devices that have many coupled components. The first way is to create a single reduced-order model of the entire device. The second way is to interconnect reduced-order models of the components that constitute the device. The second choice (which we call the "reduce then interconnect" approach) allows the heat transfer specialist to perform quick simulations of different architectures of the device by using a library of reduced-order models of the different components that make up the device. However, interconnecting reduced-order models in a straightforward manner can result in unstable behavior. The purpose of this paper is two-fold: creating reduced-order models of the components using a Krylov subspace algorithm and interconnecting the reduced-order models in a stable manner using concepts from control theory. In this paper, we explain the logic behind the "reduce then interconnect" approach, formulate a control-theoretic method for it, and finally exhibit the whole process numerically, by applying it to an example heat conduction problem     

An adjustable accuracy model for VLSI analog circuits using lookup tables

The successful design of analog VLSI circuits requires both a precise and computationally efficient device model. An accuracy adjustable table look-up modeling methodology, using a multidimensional gradient data tracing methodology and an interpolation technique with monotonicity, has been developed for analog circuit simulation. Using this technique, several table models with different accuracies have been compiled and utilized to simulate analog circuits such as a CMOS push-pull inverter and cascode opamp with a regulated current sink without loss of computational efficiency. This accuracy adjustable modeling approach has the ability to compromise between table size (speed) and model accuracy. Model accuracy can be emphasized in a specific device operation range where accuracy is critical to circuit performance by utilizing an accuracy partitioning methodology. A generic modeling methodology has been successfully generalized with dependent and independent variables applicable to several technologies, including CMOS, bipolar, and GaAs technologies. Simulation results from table models compiled by this new approach are not only more accurate but also more computationally efficient (faster) than conventional device models such as SPICE level 2 and BSIM models.     

Two-dimensional simulation of ferroelectric memory cells

An approach to increase the capabilities of integrated circuit nonvolatile memory is to take advantage of the hysteresis in the polarization of ferroelectric materials. For a rigorous analysis of the resulting devices, a suitable model for the ferroelectric effects has been developed. We present this model and show the results of its implementation into a device simulator. Although this model was designed especially for analysis of ferroelectric materials, it is also applicable to magnetic hysteresis phenomena     

基于分层架构模式识别的软件架构重构技术

本文提出一种基于分层架构模式识别的软件架构重构技术.该技术以目标软件的源代码作为输入,过滤与分层架构无关的代码,再利用代码词汇信息挖掘程序实体之间的语义关联,通过代码主题提取并计算程序实体之间的职责相似度,依据相似度将程序实体聚类形成组件.在软件组件化的基础上结合分层模式的ILD属性识别软件层次和软件架构模式.在模式识...     

Parameterized SPICE model for a phase-change RAM device

A simple form of a SPICE macro model for a generic phase-change random access memory device is presented. The approach is based upon lumped parameter multiple level models. The SPICE implementation is described using a series of increasingly complex modeling blocks for dc to transient analysis. The effect of nonlinear phase switching during the programming cycle is demonstrated in a SPICE simulation and compared to experimental data.     

A novel high-throughput method for table look-up based analog design automation

Analog circuit synthesis ofen requires repeated evaluations of circuit under design to reach the final design goals. Circuit simulations using SPICE can provide accurate assessment of circuit performance. Spice simulations are costly and incur significant overhead. A faster transistor-level evaluation is needed to provide higher throughput for synthesis applications. Further, miniaturization of FET’s has added physical effects into SPICE models, which complicated their equations with every generation. That complication has forced analog synthesis tool developers and circuit designers alike to perform circuit evaluations using SPICE.Analog circuit design tools largely failed in their declared goal, to take over circuit optimization tasks from human designers mainly due to over simplications using custom-developed equations for evaluating circuit performance. Since it is more and more difficult to accurately capture transistor behavior with each new generation of silicon technology, a more practical approach to analog design automation is to keep human engineers at the center of the design flow by providing them with as much needed decision-supporting data as quickly as possible. Mapping the trade-off landscape of a topology with respect to design specifications, for example, can save designers trial and error time. This approach to analog design automation requires less accuracy from the simulation sign-off tools, such as SPICE. However, it demands much faster response for circuit performance evaluations with sufficient accuracy.In this paper, a new solution to both calculation overheads and model complexity is proposed. The proposed fast evaluation method uses a novel look-up table (LUT) algorithm to extract circuit information from complex physics-based transistor models used by SPICE. The model makes use of contemporary memory space, by replacing equations with look-up tables in addition to advanced interpolation methods. The achieved improvement is over 100× throughput and complete decoupling from physical phenomena compared to SPICE run-time, in exchange for few gigabytes of data per device. Examples are shown for the effectiveness of replacing SPICE with our model in a transistor sizing flow, while keeping 99% of the samples inside the 5% error range on 180 nm and 40 nm CMOS processes. The proposed solution is not intended to replace sign-off quality tools, such as SPICE. Rather, it is intended to be used as a fast performance evaluator in analog design automation flows.     

Who's against Productivity?

In this nontraditional review of the productivity problem, the author holds that: ? Traditional approaches to productivity gains are based on control-that is, on prescribing and proscribing worker behavior. Despite temporary successes, these have not been adequate in the long run. ? The behavioral approach to productivity attempts to establish conditions in which human effort can be effective. However, it encounters resistance, because sustained behavior changes require basic changes in the internal culture of organizations. ? The implementation of behavioral approaches to productivity is more of an internal politicalproblem for the organization than it is a technical, psychological or industrial relations problem.     

Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors

Radiation induced faults in digital systems have started gathering major attention in recent years due to increasing reliability concern for future technologies. For future technologies, multiple transient faults (MTF) originating from a single radiation hit are expected to occur more frequently. Further, due to continuous massive scaling in device geometry, a particle with moderate linear energy transfer (LET) values is expected to affect more than one module/device during striking. Additionally, incessant escalation in operating speed with evolution of technology has increased likelihood of multi-cycle transient (MCT) faults in digital circuits. This calls for novel solutions for concurrently tackling multi-cycle transient and multi-transient fault resiliency at a higher design abstraction level such as behavioral level. This paper proposes a novel approach for generating simultaneous multi-cycle transient and multiple transient fault resilient designs during high level synthesis (HLS) of application specific datapath processors using the framework of dual modular redundancy. Results of the proposed approach on benchmarks indicated generation of low cost MCT–MFT resilient designs during HLS within acceptable runtime.     

Integrated service creation environment for open network services

The service creation scheme is changing with the advent of open network service architecture for next-generation network. New requirements should be considered for IT domain developers to create telecom and Internet combined services more easily. This paper describes an integrated service creation environment (SCE) to reflect the trend of network evolution toward an open network environment. The SCE provides multiple service programming tools to support various users’ background, a mash-up toolkit for IT domain, a simulation-based validation tool, a run-time adaptation tool, and a personalized service provisioning environment. Several example services were implemented to verify the features of an integrated SCE. Our approach is very promising because it supports various requirements and background of service developers on the full service creation process. Furthermore, it provides a means for personalized service creation driven by end-user, which is a new trend of future network.     

A behavioral model development methodology for microwave components and integration in VHDL-AMS

The new generation of system-on-chip (SoC) incorporates digital, analogue, radiofrequency (RF)/microwave and mixed-signal components. Therefore, novel design methodologies must be developed to direct the design of these mixed-technology systems, which will have to include accurate behavioral libraries of devices and processes. Thus, this paper describes a behavioral modeling approach which generates accurate empirical models for RF/microwave devices and that can be easily integrated into a VHDL-AMS simulator. This approach is applied to a microwave tunable phase shifter and it is illustrated by the development of a VHDL-AMS model library for RF/microwave applications.