Characterization of thin-oxide MNOS memory transistors

A direct tunneling theory is formulated and applied to high-speed thin-oxide complementary metal-nitride-oxide-silicon (MNOS) memory transistors. Charge transport in the erase/write mode of operation is interpreted in terms of the device threshold voltage shift. The threshold voltage shift in the erase/write mode is related to the amplitude and time duration of the applied gate voltage over the full range of switching times. MNOS memory devices (X_{o}=25 Aring, X_{N} = 335 Aring) exhibit aDelta V_{th} = plusmn3V for an erase/writet_{p} = 100ns, which corresponds to an initial oxide field strengthE_{ox}= 1.2 times 10^{7}V/cm. The direct tunneling theory is applied to the charge retention or memory mode in which charge is transported to and from the Si-SiO2interface states. The rate of charge loss to interface states is influenced by electrical stress which alters the interface state characteristics. We discuss the fabrication of complementary high-speed MNOS memory transistors and the experimental test procedures to measure charge transport and storage in these devices.     

Bottom-Gate Gallium Indium Zinc Oxide Thin-Film Transistor Array for High-Resolution AMOLED Display

The fabrication process and the characteristics of bottom-gate $ hbox{Ga}_{2}hbox{O}_{3}{-}hbox{In}_{2}hbox{O}_{3}{-}hbox{ZnO}$ (GIZO) thin-film transistors (TFTs) are reported in detail. Experimental results show that oxygen supply during the deposition of GIZO active layer and silicon oxide passivation layer controls the threshold voltage of the TFT. The field-effect mobility and the threshold voltage of the GIZO TFT fabricated under the optimum process conditions are 2.6 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$ and 3.8 V, respectively. A 4-in QVGA active-matrix organic light-emitting diode display driven by the GIZO TFTs without any compensation circuit in the pixel is successfully demonstrated.      

AlGaN/GaN Recessed MIS-Gate HFET With High-Threshold-Voltage Normally-Off Operation for Power Electronics Applications

This letter reports normally-off operation of an AlGaN/GaN recessed MIS-gate heterostructure field-effect transistor with a high threshold voltage. The GaN-based recessed MIS-gate structure in conjunction with negative polarization charges under the gate allows us to achieve the high threshold voltage, whereas the low on-state resistance is maintained by the 2-D electron gas remaining in the channel except for the recessed MIS-gate region. The fabricated device exhibits a threshold voltage as high as 5.2 V with a maximum field-effect mobility of 120 $hbox{cm}^{2}/hbox{V}cdot hbox{s}$, a maximum drain current of over 200 mA/mm, and a breakdown voltage of 400 V.      

A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V

A comparator in a low-power 65-nm complementary metal–oxide–semiconductor process (only standard transistors with threshold voltage $V_{t} approx 0.4 hbox{V}$ were used) is presented, where the circuit of a conventional latch-type comparator consisting of two cross-coupled inverters is modified for fast operation, even with 0.6 GHz at a low supply voltage of 0.65 V. The advantages of a high-impedance input, rail-to-rail output swing, robustness against the influence of mismatch, and no static power consumption are kept. To achieve a bit error rate of $10^{-9}$ at 1.2-V supply, an amplitude at the input of 16.5 mV at 4 GHz has to be applied. If the supply voltage is lowered, 12.1 mV at 0.6 GHz/0.65 V is necessary. The power consumption of the comparator is 2.88 mW at 5 GHz (1.2 V) and 128 $muhbox{W}$ at 0.6 GHz (0.65 V). Simulations show an offset standard deviation of about 6.1 mV at 0.65-V supply. With an on-chip measurement circuit, the delay time of the comparator of, e.g., 104 ps for 15-mV input amplitude at 1.2-V supply, is obtained.      

New n-Type $hbox{TiO}_{2}$ Transparent Active Channel TFTs Fabricated With a Solution Process

New metal–oxide thin-film transistors (MOxTFTs) with a solution-processed $hbox{TiO}_{2}$ transparent active channel are fabricated with a novel doping process that consists of a deposition of an ultrathin Ti layer on $hbox{TiO}_{2}$ films and a brief rapid thermal annealing. Contrary to an as-prepared device which does not show any appreciable TFT actions, devices with the proposed process exhibit a clear n-type TFT behavior with a saturation mobility of 0.12 $hbox{cm}^{2}cdothbox{V}^{-1}cdothbox{s}^{-1}$ and a threshold voltage of 11 V. A solution processibility and a low-cost manufacturability of $hbox{TiO}_{2}$ make the presented TFTs potentially attractive for cost-sensitive applications.      

Operation of Pt/AlGaN/GaN-Heterojunction Field-Effect-Transistor Hydrogen Sensors With Low Detection Limit and High Sensitivity

To enhance the device sensitivity and detection limit, a gate bias is applied to the catalytic metal of AlGaN/GaN-heterojunction field-effect-transistor (HFET) hydrogen sensors to control the carrier concentration in the channel at operation. The sensors exhibit a good sensitivity at temperatures up to 800 $^{circ}hbox{C}$ and a detection limit of 10-ppb $ hbox{H}_{2}$ in $hbox{N}_{2}$. The dependence of the device sensitivity on gate and drain biases has been investigated. The sensitivity peaks at the gate bias of threshold voltage and the drain bias of knee voltage in sensing gas. At high temperatures and $hbox{H}_{2}$ concentrations, specifically from 300 $^{circ}hbox{C}$ and 1000-ppm $hbox{H}_{2}/hbox{N}_{2}$, respectively, the sensitivity of HFETs at $V_{rm gs} = -hbox{3.5} hbox{V}$ and $V_{rm ds} = hbox{1} hbox{V}$ is more than three orders higher than their sensitivity at $V_{rm gs} = hbox{0} hbox{V}$ and the sensitivity of Schottky diodes.      

Transparent Electronics for See-Through AMOLED Displays

Transparent thin-film-transistors (TFTs) with a channel semiconductor based on the zinc–tin–oxide (ZTO) system are presented. Specifically, the technological and material aspects of the plasma-assisted pulsed laser deposition of these materials are discussed. The supply of additional radical oxygen species will be evidenced to significantly reduce defects in the material and as a consequence allows for well-behaved n-channel TFTs with mobilities higher than 10 ${hbox{cm}}^{2} {hbox{V}} ^{-1} {hbox{s}} ^{-1}$ and a threshold voltage in the range of 0 V. In addition the devices are extremely stable versus bias/current stress, which is especially important for active matrix OLED applications. Based on a detailed understanding of the interaction of the TFT channels with oxygen a strategy for the thin-film encapsulation of the TFTs will be presented, which leaves their device characteristics unaffected.      

The thermal properties of gallium arsenide laser structures

The development of high-power junction lasers has resulted in the development at many laboratories of laser structures which will enable devices to operate at high mean power or continuously at the highest possible temperature. However, little attention has been paid to the measurement of the thermal properties of the resulting structures. Although CW operation does not, in general, give the maximum mean power from a device, continuous operation at elevated temperatures is a convenient development aim and it is shown that this can be predicted on the basis of two conditions: 1)gammaI_{0}vtheta/T_{0} < 0.15if joule heating is small, or 2)I_{0}^{2}Rtheta/T_{0} < 0.067if joule heating dominates the device dissipation, where I0threshold current at the ambient temperature T0Vjunction voltage 0 thermal impedance of the deviceReffective ohmic resistance of the device 1 - γ device quantum efficiency. Various methods of measuring the thermal impedance θ have been devised and are considered in detail. These methods involve observations of spectra or threshold under various operating conditions and give results which are in good mutual agreement. It is suggested that the thermal properties of a device can conveniently be described in terms of two figures of merit given byI_{0}Vtheta_{gamma}andI_{0}^{2}Rtheta.     

Gate-Recess Technology for InAs/AlSb HEMTs

The gate-recess technology for Si $delta$-doped InAs/AlSb high-electron-mobility transistors (HEMTs) has been investigated by combining atomic force microscopy (AFM) inspection of the gate-recess versus time with electrical device characterization. Deposition of the gate metal on the $hbox{In}_{0.5}hbox{Al}_{0.5}hbox{As}$ protection layer or on the underlying AlSb Schottky layer resulted in devices suffering from high gate-leakage current. Superior dc and high frequency device performance were obtained for HEMTs with an insulating layer between the gate and the Schottky layer resulting in a reduction of the gate leakage current $I_{G}$ by more than two orders of magnitude at a drain-to-source voltage $V_{DS}$ of 0.1 V. The existence of this intermediate insulating layer was evident from the electrical measurements. AFM measurements suggested that the insulating layer was due to a native oxidation of the AlSb Schottky layer. The insulated-gate HEMT with a gate length of 225 nm exhibited a maximum drain current $I_{D}$ higher than 500 mA/mm with good pinchoff characteristics, a dc transconductance $g_{m}$ of 1300 mS/mm, and extrinsic values for cutoff frequency $f_{T}$ and maximum frequency of oscillation $f_{max}$ of 160 and 120 GHz, respectively.      

Increase of Breakdown Voltage on AlGaN/GaN HEMTs by Employing Proton Implantation

The breakdown voltage of new AlGaN/GaN high electron mobility transistors (HEMTs) was increased considerably without sacrificing any other electrical characteristics by proton implantation. The breakdown voltage of proton-implanted AlGaN/GaN HEMTs with 150 KeV $hbox{1}times hbox{10}^{14} hbox{-}hbox{cm}^{-2}$ fluence after thermal annealing at 400 $^{circ}hbox{C}$ for 5 min under $hbox{N}_{2}$ ambient was 719 V, while that of conventional device was 416 V. The increase of the breakdown voltage is attributed to the expansion of the depletion region under the 2-D electron gas (2-DEG) channel. The depletion region expanded downward into the GaN buffer layer because implanted protons acted as positive ions and attracted electrons in the 2-DEG channel.      

Effects of ionizing radiation on n-channel MOSFET's fabricated in zone-melting-recrystallized Si films on SiO2

We have investigated the effects of irradiation with 1.5 MeV electrons on the electrical characteristics of n-channel MOSFET's fabricated in zone-melting-recrystallized Si films on SiO2-coated Si substrates. With a -15 V bias applied to the Si substrate during irradiation and device operation, the subthreshold leakage current remains below 0.2 pA/µm (channel width) for ionizing doses up to 10⁶rad(Si). The negative substrate bias also reduces the shift of threshold voltage to less than 0.3 V for devices with 50 nm-thick gate oxide.     

Artificial creation of threshold characteristics in the domain switching of ferroelectric—Ferroelastic Gadolinium molybdate

A new method of providing artificially well-defined threshold characteristics in the domain switching of ferroelectric-ferroelastic Gd2(MoO4)3single crystals is presented and experimentally confirmed. The essence of the idea lies in the utilization of a coupling effect between the strain and the polarization which is a characteristic of ferroelectric-ferroelastic crystals. The potential barrier required for electrical switching with a definite threshold is produced by the strain due to locally deposited surface films, which results in strain-induced multidomain regions beneath the films and stabilizes the domain wall at the end of strain-free switching regions. The measured characteristics of the threshold switching elements were as follows; threshold voltageV_{t}=190V and switching timet_{s} = 0.6ms at applied full voltageV_{f} = 250V. These threshold switching elements have potential applications to a ferroelectric light valve array and a ferroelectric memory device.     

Small-Subthreshold-Swing and Low-Voltage Flexible Organic Thin-Film Transistors Which Use HfLaO as the Gate Dielectric

Pentacene organic thin-film transistors (OTFTs) with a high-$kappa$ HfLaO dielectric were integrated onto flexible polyimide substrates. The pentacene OTFTs exhibited good performance, such as a low subthreshold swing of 0.13 V/decade and a threshold voltage of $-$1.25 V. The field-effect mobility was 0.13 $hbox{cm}^{2}/hbox{V}cdothbox{s}$ at an operating voltage as low as only 2.5 V. These characteristics are attractive for high-switching-speed and low-power applications.      

A high threshold voltage uniformity MIS-like heterostructure FET using n+-Ge as a gate electrode

A new n+-Ge/ undoped-AlxGa1-xAs/ undoped-GaAs MISlike heterostructure FET (n+-Ge-HFET), using n+-Ge layer as a gate electrode material, is shown to have a high threshold voltage uniformity (sigmaV_{TH} = 11mV) over a large sample area of a 2-in wafer quadrant. This is thought to come from the FET structure, for which the threshold voltage is principally determined by the difference in the electron affinities of Ge and GaAs. The high VTHuniformity, as well as the positive FET characteristics (g_{m} = 170mS/mm,V_{TH} = 0.25V), makes n+-Ge-HFET very attractive for LSI application.     

Simple model for threshold voltage in a short-channel IGFET

The threshold voltage of a short-channel IGFET can be expressed, in relation to that for a long-channel device, asV_{T} = V_{TLC} - alpha - betaV_{DS}. This behavior is deduced from a charge injection model and is verified both by two-dimensional numerical simulations and by actual threshold data.     

A 300 nW, 15 ppm/$^{circ}$C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

A low-power CMOS voltage reference was developed using a 0.35 $mu$m standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745$~$mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/ $^{circ}$C at best and 15 ppm/$^{circ}$C on average, in a range from ${-}$ 20 to 80$^{circ}$ C. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4–3 V, and the power supply rejection ratio (PSRR) was ${-}$45 dB at 100 Hz. The power dissipation was 0.3 $mu$W at 80$^{circ}$C. The chip area was 0.05 mm$^2$ . Our device would be suitable for use in subthreshold-operated, power-aware LSIs.      

A 0.22 V Quadrature VCO in 90 nm CMOS Process

This letter presents an ultra-low voltage quadrature voltage-controlled oscillator (QVCO). The LC-tank QVCO consists of two low-voltage voltage-controlled oscillators (VCOs) with the body dc biased at the drain bias through a resistor. The superharmonic and back-gate coupling techniques are used to couple two differential VCOs to run in quadrature. The proposed CMOS QVCO has been implemented with the UMC 90 nm CMOS technology and the die area is 0.827 $, times ,$0.913 mm $^{2}$. At the supply voltage of 0.22 V, the total power consumption is 0.33 mW. The free-running frequency of the QVCO is tunable from 3.42 to 3.60 GHz as the tuning voltage is varied from 0.0 to 0.3 V. The measured phase noise at 1 MHz offset is ${-}112.97$ dBc/Hz at the oscillation frequency of 3.55 GHz and the figure of merit (FOM) of the proposed QVCO is about ${-}188.79$ dBc/Hz.      

A Novel Multiple-Gate Polycrystalline Silicon Nanowire Transistor Featuring an Inverse-T Gate

A novel multiple-gate field-effect transistor with poly-Si nanowire (NW) channels is proposed and fabricated using a simple process flow. In the proposed structure, poly-Si NW channels are formed with sidewall spacer etching technique, and are surrounded by an inverse-T gate and a top gate. When the two gates are connected together to drive the NW channels, dramatic performance enhancement as compared with the cases of single-gate operation is observed. Moreover, subthreshold swing as low as 103 mV/dec at $hbox{Vd} = hbox{2} hbox{V}$ is recorded. Function of using the top gate bias to modulate the threshold voltage of device operation driven by the inverse-T gate biases is also investigated in this letter.      

A Low Voltage and Low Power Bottom-Series Coupled Quadrature VCO

This letter presents a new low power quadrature voltage-controlled oscillator (QVCO), which consists of two complementary cross-coupled voltage-controlled oscillators (VCOs) with split-source tail inductors. The bottom-series coupling transistors are in parallel with the tail inductors and require no dc voltage headroom. The proposed CMOS QVCO has been implemented with the TSMC 0.18 $mu{rm m}$ CMOS technology and the die area is $0.512times 1.065 {rm mm}^{2}$. At the supply voltage of 1.1 V, the total power consumption is 2.545 mW. The free-running frequency of the QVCO is tunable from 4.38 to 4.71 GHz as the tuning voltage is varied from 0.0 V to 0.6 V. The measured phase noise at 1 MHz frequency offset is $-$120.8 dBc/Hz at the oscillation frequency of 4.4 GHz and the figure of merit (FOM) of the proposed QVCO is $-$ 189.61 dBc/Hz.      

A Low Voltage Quadrature VCO Implemented With Series Frequency Doublers

Using the transformer coupling technique, this letter presents a new quadrature voltage-controlled oscillator (QVCO) with bottom series-coupled transistors. The proposed CMOS QVCO has been implemented with the TSMC $0.13~mu{rm m}$ 1P8M CMOS process, and the die area is $1.03 times 0.914~{rm mm}^{2}$. At the supply voltage of 1.0 V, the total power consumption is 3.56 mW. The free-running frequency of the QVCO is tunable from 5.43 GHz to 5.92 GHz as the tuning voltage is varied from 0.0 V to 1.0 V. The measured phase noise at 1 MHz frequency offset is $-117.98~{rm dBc/Hz}$ at the oscillation frequency of 5.5 GHz and the figure of merit (FOM) of the proposed QVCO is $-187.27~{rm dBc/Hz}$.