OBIST methodology incorporating modified sensitivity of pulses for active analogue filter components

In this paper, oscillation-based built-in self-test method is used to diagnose catastrophic and parametric faults in integrated circuits. Sallen–Key low pass filter and high pass filter circuits with different gains are used to investigate defects. Variation in seven parameters of operational amplifier (OP-AMP) like gain, input impedance, output impedance, slew rate, input bias current, input offset current, input offset voltage and catastrophic as well as parametric defects in components outside OP-AMP are introduced in the circuit and simulation results are analysed. Oscillator output signal is converted to pulses which are used to generate a signature of the circuit. The signature and pulse count changes with the type of fault present in the circuit under test (CUT). The change in oscillation frequency is observed for fault detection. Designer has flexibility to predefine tolerance band of cut-off frequency and range of pulses for which circuit should be accepted. The fault coverage depends upon the required tolerance band of the CUT. We propose a modification of sensitivity of parameter (pulses) to avoid test escape and enhance yield. Result shows that the method provides 100% fault coverage for catastrophic faults.     

A Fast Redundancy Analysis Algorithm in ATE for Repairing Faulty Memories

Testing memory and repairing faults have become increasingly important for improving yield. Redundancy analysis (RA) algorithms have been developed to repair memory faults. However, many RA algorithms have low analysis speeds and occupy memory space within automatic test equipment. A fast RA algorithm using simple calculations is proposed in this letter to minimize both the test and repair time. This analysis uses the grouped addresses in the faulty bitmap. Since the fault groups are independent of each other, the time needed to find solutions can be greatly reduced using these fault groups. Also, the proposed algorithm does not need to store searching trees, thereby minimizing the required memory space. Our experiments show that the proposed RA algorithm is very efficient in terms of speed and memory requirements.     

An optimal checkpointing-strategy for real-time control systemsunder transient faults

Real-time computer systems are often used in harsh environments, such as aerospace, and in industry. Such systems are subject to many transient faults while in operation. Checkpointing enables a reduction in the recovery time from a transient fault by saving intermediate states of a task in a reliable storage facility, and then, on detection of a fault, restoring from a previously stored state. The interval between checkpoints affects the execution time of the task. Whereas inserting more checkpoints and reducing the interval between them reduces the reprocessing time after faults, checkpoints have associated execution costs, and inserting extra checkpoints increases the overall task execution time. Thus, a trade-off between the reprocessing time and the checkpointing overhead leads to an optimal checkpoint placement strategy that optimizes certain performance measures. Real-time control systems are characterized by a timely, and correct, execution of iterative tasks within deadlines. The reliability is the probability that a system functions according to its specification over a period of time. This paper reports on the reliability of a checkpointed real-time control system, where any errors are detected at the checkpointing time. The reliability is used as a performance measure to find the optimal checkpointing strategy. For a single-task control system, the reliability equation over a mission time is derived using the Markov model. Detecting errors at the checkpointing time makes reliability jitter with the number of checkpoints. This forces the need to apply other search algorithms to find the optimal number of checkpoints. By considering the properties of the reliability jittering, a simple algorithm is provided to find the optimal checkpoints effectively. Finally, the reliability model is extended to include multiple tasks by a task allocation algorithm     

系统芯片中AMBA总线串扰故障的自测试方法

系统芯片(SoC)技术的发展使得芯片内总线长度大大增加；芯片速度按照摩尔定律成倍提高(高达GHz)，总线间的串扰(Crosstalk)现象也日益严重，因此关于串扰的故障模型和自测试技术越来越受到关注。本文利用最大侵扰故障MAF(Maximal Aggressor Fault)模型，提出了一种SoC芯片中总线串扰故障的自测试方法。利用该方法，SoC芯片中地址、数据和控制总线的串扰故障均得到了测试，实验结果也表明其硬件开销较其它方案大大降低。     

A high fault coverage test approach for communication channels in network on chip

This paper proposes a new high fault coverage test approach for short faults in Network on Chip communication channels. The proposed approach consists of a built in self-test as well as a Packet/flit Comparing Module (PCM) embedded in the network adapter and a router, respectively. The approach is mainly characterized by the fact that, the detection, location, and routing table updating processes are simultaneously carried out after which the test time is minimized. The approach with high scalability leads to 100% test coverage and 89.5% capability of diagnosing faulty channels in one round (two phases). The simulation results show that the approach hardware and time cost is optimized compared with the previous methodologies.     

一种Mbist新型算法March 3CL的设计

制造工艺的不断进步,嵌入式存储器在片上系统芯片中的集成度越来越大,同时存储器本身也变得愈加复杂,使得存储器出现了一系列新的故障类型,比如三单元耦合故障.存储器內建自测试技术是当今存储器测试的主流方法,研究高效率的Mbist算法,是提高芯片成品率的必要前提.以SRAM的7种三单元耦合故障为研究对象,通过分析故障行为得到三单元耦合的72种故障原语,并且分析了地址字内耦合故障的行为,进而提出新的测试算法March 3CL.以2048X32的SRAM为待测存储器,利用EDA工具进行了算法的仿真,仿真结果表明,该算法具有故障覆盖率高、时间复杂度低等优点.     

The number of working periods of a repairable Markov system duringa finite time interval

In reliability analysis, continuous parameter homogeneous irreducible finite Markov processes are used to model repairable systems with time-independent transition rates between individual states. The state space is then partitioned into the set of up states and the set of down states. The number of completed repair events during a finite time interval is an important (undiscounted) cost measure for such a system; it can be expressed in terms of the number of working periods during the same time interval. This paper derives a closed-form expression for the PMF of this latter quantity. The tool used is a recent result on the joint distribution of sojourn times in finite Markov processes. The MatLab implementation of the Markov model of a 2-unit parallel power transmission system is used to demonstrate the utility of the formula. The quantity examined is the number of completed repairs during a finite time interval. The method is viable in this case whereas the more usual randomization technique is not     

Automated repair of complex systems by fault compensation

A formal method used to repair discrete-event systems consisting of communicating processes is described. Two mechanisms of repairing faulty systems are proposed: the first inserts a new “compensator module” into the communication channel between the faulty process and one or more of its neighbors; the second modifies a neighbor of the faulty process in a compensating manner. The two mechanisms fall under a class of methods in which faults are not fixed by replacement of a faulty unit with a fault-free one, but where changes to the non-faulty parts of the system repair the system. A finite-state model is used to describe processes, and the problem is solved for two models of communication: the symmetric (or the handshake) model and, an asymmetric model. The algorithm is described, and examples are presented, including an indication of how the approach may be applied as part of a sophisticated fault management system for communication networks     

电子系统未发现故障研究综述

电子系统的复杂度日渐增加,工艺水平日益提升,未发现故障(NFF)事件频发,对电子设备产生很大的影响,常导致不必要的重复停机、过度修理和零备件大量损耗等问题,影响设备的战备完好性。主要从NFF事件的基本概念和相关术语、NFF事件原因如故障因素和非故障因素、间歇故障引起NFF事件的机理等方面对NFF 事件进行系统论述,并指出了NFF事件的危害及其应对/预防措施,列举了相关实例,以期给相关工程和研究人员以借鉴,促进对NFF事件的研究。     

Robust Adaptive Fault Estimation for a Class of Nonlinear Systems Subject to Multiplicative Faults

In this paper, a fault estimation problem for a class of nonlinear systems subject to multiplicative faults and unknown disturbances is investigated. Multiplicative faults usually mixed with system states and inputs can cause additional complexity in the design of fault estimator due to parameter changes within process. Especially for the nonlinear system corrupted with unknown disturbances, it is not an easy work to distinguish the real fault factor from the mixed term. Under the nonlinear Lipschitz condition, the proposed robust adaptive fault estimation approach not only estimates the multiplicative faults and system states simultaneously, but also extracts the real effect of the faults. Meanwhile, the effect of disturbances is restricted to an L ₂ gain performance criteria which can be formulated into the basic feasibility problem of a linear matrix inequality (LMI). In order to reduce the conservatism of the proposed method, a relaxing Lipschitz matrix is introduced. Finally, an illustrative example is applied to verify the efficiency of the proposed robust adaptive estimation scheme.     

Fault-Tolerant Control for Markovian Jump Delay Systems with an Adaptive Observer Approach

This paper investigates the problem of fault estimation and fault-tolerant control for a class of Markovian jump systems with mode-dependent interval time-varying delay and Lipschitz nonlinearities. In this paper, a new adaptive fault observer is designed to solve the problem of fault estimation. The proposed observer can estimate the states and faults simultaneously, whether faults are of time-varying or constant characterization. Based on the fault estimation, a fault-tolerant controller is designed to stabilize the closed-loop system. Sufficient conditions for the existence of the observer gain and fault-tolerant controller gain are got by a set of linear matrix inequalities. Finally, a numerical example is presented to illustrate the effectiveness of the proposed fault-tolerant control method.     

Online Fault Tolerance for FPGA Logic Blocks

Most adaptive computing systems use reconfigurable hardware in the form of field programmable gate arrays (FPGAs). For these systems to be fielded in harsh environments where high reliability and availability are a must, the applications running on the FPGAs must tolerate hardware faults that may occur during the lifetime of the system. In this paper, we present new fault-tolerant techniques for FPGA logic blocks, developed as part of the roving self-test areas (STARs) approach to online testing, diagnosis, and reconfiguration . Our techniques can handle large numbers of faults (we show tolerance of over 100 logic faults via actual implementation on an FPGA consisting of a 20 times 20 array of logic blocks). A key novel feature is the reuse of defective logic blocks to increase the number of effective spares and extend the mission life. To increase fault tolerance, we not only use nonfaulty parts of defective or partially faulty logic blocks, but we also use faulty parts of defective logic blocks in nonfaulty modes. By using and reusing faulty resources, our multilevel approach extends the number of tolerable faults beyond the number of currently available spare logic resources. Unlike many column, row, or tile-based methods, our multilevel approach can tolerate not only faults that are evenly distributed over the logic area, but also clusters of faults in the same local area. Furthermore, system operation is not interrupted for fault diagnosis or for computing fault-bypassing configurations. Our fault tolerance techniques have been implemented using ORCA 2C series FPGAs which feature incremental dynamic runtime reconfiguration     

Circular BIST with state skipping

Circular built-in self-test (BIST) is a "test per clock" scheme that offers many advantages compared with conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion. However, it has seen limited use because it does not reliably provide high fault coverage. This paper presents a systematic approach for achieving high fault coverage with circular BIST. The basic idea is to add a small amount of logic that causes the circular chain to skip to particular states. This "state skipping" logic can be used to break out of limit cycles, break correlations in the test patterns, and jump to states that detect random-pattern-resistant faults. The state skipping logic is added in the chain interconnect and not in the functional logic, so no delay is added on system paths. Results indicate that in many cases, this approach can boost the fault coverage of circular BIST to match that of conventional parallel BIST approaches while still maintaining a significant advantage in terms of hardware overhead and control complexity. Results are also shown for combining "state skipping" logic with observation point insertion to further reduce hardware overhead.     

混沌扩频多根电缆故障在线同步诊断研究

针对实际飞机电源系统电缆布线复杂,数量多的问题,本文基于现有的单根电缆故障检测成本高、效率低、检测难度大的研究现状,利用混沌序列对初值敏感（初值不同信号干扰小）、序列数量巨大的特点,提出将混沌序列用于飞机多根电缆故障在线同步诊断的方法.解决了扩展频谱时域反射法（Spread Spectrum Time Domain Reflectometry,SSTDR）中采用相同m序列进行同步诊断时相互干扰、易误判问题,m序列数量限制导致的检测数量问题.研究发现其尖锐的自相关特性能够较好应用于单根电缆故障诊断,故障特征明显;其良好的互相关特性能够同时进行多根电缆的故障诊断,抗干扰性好;结合混沌序列数量多的优势,其能够推广应用于复杂电缆故障的在线诊断.实验结果表明混沌扩频电缆故障诊断方法可有效实现多根电缆故障的同步诊断,定位误差在20cm以内,检测率达90%以上.     

一种片上网络路由测试方法研究

对片上网络路由器的结构进行了分析,建立了相应的故障模型.针对此故障模型结合内建自测试,提出了一种基于量子遗传算法的测试矢量传递路径寻优方法.该算法具有收敛速度快,精度高等优点.最后通过对测试故障覆盖率和测试时间进行分析表明这种测试方法具有较高的故障覆盖率、较少的测试时间.     

Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics

We propose a built-in self-test (BIST) procedure for nanofabrics implemented using chemically assembled electronic nanotechnology. Several fault detection configurations are presented to target stuck-at faults, shorts, opens, and connection faults in nanoblocks and switchblocks. The detectability of multiple faults in blocks within the nanofabric is also considered. We present an adaptive recovery procedure through which we can identify defect-free nanoblocks and switchblocks in the nanofabric-under-test. The proposed BIST, recovery, and defect tolerance procedures are based on the reconfiguration of the nanofabric to achieve complete fault coverage for different types of faults. We show that a large fraction of defect-free blocks can be recovered using a small number of BIST configurations. We also present simple bounds on the recovery that can be achieved for a given defect density. Simulation results are presented for various nanofabric sizes, different defect densities, and for random and clustered defects. The proposed BIST procedure is well suited for regular and dense architectures that have high defect densities.     

Code-width testing-based compact ADC BIST circuit

This paper proposes a new analog-to-digital converter (ADC) built-in self-test (BIST) scheme based on code-width and sample-difference testing that does not require a slope-calibrated ramp signal. The proposed BIST scheme can be implemented by a simple digital circuit whose gate count is only approximately 550. The proposed BIST scheme is verified by simulation with 138 test circuits of 6-b pipeline ADC with arbitrary faults. Simulation results show that it effectively detects not only the catastrophic faults but also some parametric faults. The simulated fault coverage is approximately 99%.     

Mixing of Two Renewal Processes and Its Applications to Reliability Theory

The probabilistic behavior of repairable two-state systems is studied. It is assumed that the reliability of the system can be measured by the amount of time the system has been operative. The operating and repair states are a pair of renewal processes, a particular mixture of which describes the statistical behavior of the system. The object of this contribution is to extend the results of Muth who has earlier obtained the average value of the downtime and its variance, when one of the constituent renewal processes has its interval lengths distributed exponentially. This paper, by the repeated use of the method of regeneration points, obtains the mean and mean-square values of the uptime distribution. In addition the correlation of the uptime for different times has been derived and a proof of Takacs' theorem is provided. Since the criteria for the reliability of the system include the associated cost, it is worthwhile investigating the operating cost over any period of time for arbitrary distribution of the two states. In particular a demonstration of the calculation of the first two moments of the total cost is given.     

Simple and effective open switch fault diagnosis of single-phase PWM rectifier

In order to obtain lower harmonics distortion and higher power factors, single-phase pulse-width modulation (PWM) rectifiers are adopted in AC railway drive systems. Therefore, its reliability is of most importance with regard to the safe operation of the train. In this paper, a fault diagnosis method for open switch fault in single-phase PWM rectifier is proposed based on the switching system theory. It requires no additional sensor, nor extra operation states need to be set. Four observers which correspond to four kinds of open switch faults are utilized to detect and locate the faults. Real-time simulations are carried out to validate the effectiveness of this method.     

Testability of parity checkers

Checkers are used in digital circuits to detect both intermittent and stuck-at faults. The most common error detectors are parity checkers. Such circuits are themselves subject to failures. The use of parity trees is outlined, and techniques for testing them are surveyed. The effect of the checker's structure on its testability is discussed. Several fault models are considered: single stuck-at, multiple stuck-at, and bridging faults. The effectiveness of single stuck-at fault test sets in detecting multiple stuck-at and bridging faults is described. Upper bounds for the double fault coverage of the minimal single fault test are given for different tree structures. The testabilities of some selected checkers are examined to illustrate the concepts developed. A built-in self-test is proposed