Feasible approach to the fabrication of asymmetric Schottky barrier MOSFETs by using the spacer technique

The spacer technique is proposed for the fabrication of the Asymmetric Schottky Barrier MOSFETs (ASB-MOSFET). The characteristics of the 45 nm and the 20 nm n-channel ASB-MOSFETs, which adopt a Schottky barrier height of 0.9 eV at source and that of 0.2 eV at drain, have been simulated and discussed by the comparisons with the conventional Schottky Barrier MOSFETs (SB-MOSFET). With a higher Ion/Ioff ratio, the ASB-MOSFET structure has shown a better performance than the conventional SB-MOSFETs.     

High-quality NiGe/Ge diodes for Schottky barrier MOSFETs

Schottky barrier (SB) Ge channel MOSFETs suffer from high drain-body leakage at the required elevated substrate doping concentrations to suppress source–drain leakage. Here, we show that electrodeposited Ni–Ge and NiGe/Ge Schottky diodes on highly doped Ge show low off current, which might make them suitable for SB-MOSFETs. The Schottky diodes showed rectification of up to five orders in magnitude. At low forward biases, the overlap of the forward current density curves for the as-deposited Ni/n-Ge and NiGe/n-Ge Schottky diodes indicates Fermi-level pinning in the Ge bandgap. The SB height for electrons remains virtually constant at 0.52 eV (indicating a hole barrier height of 0.14 eV) under various annealing temperatures. The series resistance decreases with increasing annealing temperature in agreement with four-point probe measurements indicating the lower specific resistance of NiGe as compared with Ni, which is crucial for high drive current in SB-MOSFETs. We show by numerical simulation that by incorporating such high-quality Schottky diodes in the source/drain of a Ge channel PMOS, highly doped substrate could be used to minimize the subthreshold source to drain leakage current.     

Drivability improvement in Schottky barrier source/drain MOSFETs with strained-Si channel by Schottky barrier height reduction

Due to an extra barrier between source and channel, the drivability of Schottky barrier source/drain MOSFETs (SBMOSFETs) is smaller than that of conventional transistors. To reach the drivability comparable to the conventional MOSFET, the Schottky barrier height (SBH) should be lower than a critical value. It is expected that SBH can be effectively reduced by a bi-axially strain on Si. In this letter, p-channel MOSFETs with PtSi Schottky barrier source/drain, HfAlO gate dielectric, HfN/TaN metal gate and strained-Si channel are demonstrated for the first time using a simplified low temperature process. Devices with the channel length of 4 μm have the drain current of 9.5 μA/μm and the transconductance of 14 μS/μm at V_gs − V_th = V_ds = −1 V. Compared to the cubic Si counterpart, the drain current and the transconductance are improved up to 2.7 and 3.1 times respectively. The improvement is believed to arising from the reduced barrier height of the PtSi/strained-Si contact and the enhanced hole mobility in the strained-Si channel.     

A computational study of thin-body, double-gate, Schottky barrier MOSFETs

Nanoscale Schottky barrier MOSFETs (SBFETs) are explored by solving the two-dimensional Poisson equation self-consistently with a quantum transport equation. The results show that for SBFETs; with positive, effective metal-semiconductor barrier heights, the on-current is limited by tunneling through a barrier at the source. If, however, a negative metal-semiconductor barrier height could be achieved, on-current of SBFETs would approach that of a ballistic MOSFET. The reason is that the gate voltage would then modulate a thermionic barrier rather than a tunneling barrier, a process similar to ballistic MOSFETs and one that delivers more current.     

Simulation of Schottky barrier MOSFETs with a coupled quantuminjection/Monte Carlo technique

A full-band Monte Carlo device simulator has been used to analyze the performance of sub-0.1 μm Schottky barrier MOSFETs. In these devices, the source and drain contacts are realized with metal silicide, and the injection of carriers is controlled by gate voltage modulation of tunneling through the source barrier. A simple model treating the silicide regions as metals, coupled with an Airy function approach for tunneling through the barrier, provides injecting boundary conditions for the Monte Carlo procedure. Simulations were carried out considering a p-channel device with 270 Å gate length for which measurements are available. Our results show that in these structures there is not a strong interaction with the oxide interface as in conventional MOS devices and carriers are injected at fairly wide angles from the source into the bulk of the device. The Monte Carlo simulations not only give good agreement with current-voltage (I-V) curves, but also easily reproduce the subthreshold behavior since all the computational power is devoted to simulation of channel particles. The simulations also clarify why these structures exhibit a large amount of leakage in subthreshold regime, due to both thermionic and tunneling emission. Computational experiments suggest ways to modify the doping profile to reduce to some extent the leakage     

Modeling of 10-nm-scale ballistic MOSFET's

We have performed numerical modeling of nanoscale dual-gate ballistic n-MOSFET's with ultrathin undoped channel, taking into account the effects of quantum tunneling along the channel and through the gate oxide. The results show that transistors with channel length as small as 8 nm can exhibit either a transconductance up to 4000 mS/mm or gate modulation of current by more than 8 orders of magnitude, depending on the gate oxide thickness. These characteristics make the sub-10-nm devices potentially suitable for logic and memory applications, though their parameters are rather sensitive to size variations     

Design considerations for planar Schottky barrier diodes

The cut-off frequency of the simplest planar Schottky diode on a uniformly doped n-layer of GaAs is derived. The theoretical results are given as functions of doping concentration and layer thickness with the specific contact resistance as parameter. An improved planar diode structure is presented with several short Schottky contact fingers connected in parallel. Experimental values ranging from 100 to 300 GHz agree with the calculated values when parasitic capacitances are taken into account.     

双栅掺杂隔离肖特基MOSFET的解析模型

通过考虑肖特基势垒降低效应求解三段连续的二维泊松方程,建立了双栅掺杂隔离肖特基MOSFET亚阈值区全沟道连续的电势模型。在该电势模型的基础上,推导了阈值电压模型和漏致势垒降低效应的表达式;研究了掺杂隔离区域不同掺杂浓度下的沟道电势分布,分析了沟道长度和厚度对短沟道效应的影响。结果表明,掺杂隔离区域能改善肖特基MOSFET的电学特性;对于短沟道双栅掺杂隔离肖特基MOSFET,适当减小沟道宽度能有效抑制短沟道效应。     

Demonstration of the first 10-kV 4H-SiC Schottky barrier diodes

This letter reports the demonstration of the first 4H-SiC Schottky barrier diode (SBD) blocking over 10 kV based on 115-/spl mu/m n-type epilayers doped to 5.6 /spl times/ 10/sup 14/ cm/sup -3/ through the use of a multistep junction termination extension. The blocking voltage substantially surpasses the former 4H-SiC SBD record of 4.9 kV. A current density of 48 A/cm/sup 2/ is achieved with a forward voltage drop of 6 V. The Schottky barrier height, ideality factor, and electron mobility for this very thick epilayer are reported. The SBD's specific-on resistance is also reported.     

Fabrication of Schottky barrier MOSFETs using self-assembly CoSi2 nanopatterning and spacer gate technologies

A self-assembly patterning method for generation of epitaxial CoSi₂ nanostructures was used to fabricate 50 nm channel-length MOSFETs. The transistors have either a symmetric structure with Schottky source and drain or an asymmetric structure with n⁺-source and Schottky drain. The patterning technique is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal oxidation. The strain field is generated along the edges of a mask consisting of 20 nm SiO₂ and 300 nm Si₃N₄. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. A poly-Si spacer was used as the gate contact. The asymmetric transistor was fabricated by ion implantation into the unprotected CoSi₂ layer and a subsequent out-diffusion process to form the n⁺-source. I–V characteristics of both the symmetric and asymmetric transistor structures have been investigated.     

Dopant-Segregated Schottky Silicon-Nanowire MOSFETs With Gate-All-Around Channels

In this letter, we demonstrated dopant-segregated Schottky (DSS) p-MOSFET with gate-all-around silicon-nanowire (SiNW) channel of 10 nm in diameter. The DSS transistor shows improved performance as compared to a reference Schottky barrier (SB) transistor without dopant segregation. The DSS transistor shows $I_{rm ON}$ of 319 $mu hbox{A}/muhbox{m}$ at a low gate overdrive of $-$ 0.6 V, high $I_{rm ON}/I_{rm OFF}$ ratio $(sim!hbox{10}^{5})$, and short-channel performance with subthreshold slope $sim$90 mV/dec down to 100-nm gate length with relatively thick (6 nm) deposited gate oxide. The DSS transistor also shows significant reduction ( $sim!hbox{40}times$ lower) in the series resistance as compared to the SB transistor. The origin of the improved performance of the DSS is the thin dopant layer segregated at the nickel monosilicide/SiNW point contact which results in the enhanced hole injection at the source side and the suppressed electron injection at the drain side.      

Two-dimensional numerical simulation of Schottky barrier MOSFETwith channel length to 10 nm

We present simulation results of a silicon-based metal-oxide-semiconductor field-effect transistor (MOSFET), which has a structure similar to that of a conventional MOSFET, but the source and drain regions are now entirely replaced by metals. By using abrupt metal/silicon Schottky junctions, short-channel effects are avoided. Based on a few commonly used physical assumptions, we have calculated the transistor characteristics, and we find that this new three-terminal transistor can offer gain and impedance isolation, desirable for logic circuit applications     

High-Quality Schottky Contacts for Limiting Leakage Currents in Ge-Based Schottky Barrier MOSFETs

Schottky barrier (SB) Ge channel MOSFETs suffer from high drain-body leakage at the required elevated substrate doping concentrations to suppress source–drain leakage. Here, we show that electrodeposited Ni–Ge and NiGe/Ge Schottky diodes on highly doped Ge show low off current, which might make them suitable for SB p-MOSFETs. The Schottky diodes showed rectification of up to five orders of magnitude. At low forward biases, the overlap of the forward current density curves for the as-deposited Ni/n-Ge and NiGe/n-Ge Schottky diodes indicates Fermi-level pinning in the Ge bandgap. The SB height for electrons remains virtually constant at 0.52 eV (indicating a hole barrier height of 0.14 eV) under various annealing temperatures. The series resistance decreases with increasing annealing temperature in agreement with four-point probe measurements indicating the lower specific resistance of NiGe as compared to Ni, which is crucial for high drive current in SB p-MOSFETs. We show by numerical simulation that by incorporating such high-quality Schottky diodes in the source/drain of a Ge channel PMOS, a highly doped substrate could be used to minimize the source-to-drain subthreshold leakage current.      

The Schottky barrier cold cathode

Cathodic vacuum emission from forward biased, rectifying contacts between n-type GaP, ZnSe and ZnS and thin Ag films covered with a monolayer of Cs agrees with a simple theory which assumes isotropic scattering of hot electrons on transmission through the interface between the semiconductor and the Ag. The maximum measured emission efficiency is 6 × 10⁻³ per cent but at least 2 per cent is expected with further development.     

Schottky barrier restricted GaAlAs laser

A new type of a simple gain-guided GaAlAs laser using a Schottky barrier restriction (SBR) technique is presented. Low current thresholds of ~2.2 kA/cm2, CW operation up to 70°C with a T0 = 160°, and a high coupling efficiency to multimode fibres are comparable to the high-quality lasers prepared with more traditional current restriction methods. This excellent performance has been achieved with extremely simple processing afforded by the SBR scheme. Although these SBR lasers have not yet been subjected to aging tests, GaAIAs LEDs fabricated in an identical fashion show excellent reliability.     

平面肖特基二极管的制作

为研究制作THz频段下工作的肖特基二极管器件,系统研究了平面肖特基二极管的制作工艺。通过分子束外延(MBE)生长了掺杂浓度分别为5×1018 cm-3的缓冲层和2×1017 cm-3的外延层,并研究温度对厚度的影响,使得膜层厚度控制良好,晶格完整。通过参数控制,减小了等离子体增强化学气相沉积(PECVD)的SiO2钝化层应力,使压指结构的翘曲情况得以改善。研究了不同退火温度下欧姆接触的情况,使接触电阻率减小到0.8×10-7 ?/cm2。用电子束光刻和干法刻蚀制作了亚微米级的阳极区域,结合GaAs湿法刻蚀的速率控制,完成了表面沟道的制作,制作出完整的平面肖特基二极管。通过I-U曲线理论计算,二极管的截止频率达到太赫兹量级,为后续工作奠定了基础。     

Thermally oxidized mesa Schottky barrier diodes

Schottky barriers with a thermally oxidized mesa structure have been fabricated. The fabrication process is described. The mesa structure averts electric field crowding at the barrier periphery. The reverse diode characteristic shows a sharp breakdown at the voltage expected for an ideal, abrupt diode of semi-infinite extent and identical doping concentration.     

Gallium arsenide dual Schottky barrier diodes

Gallium arsenide diodes were made which had Schottky-barriers for both contacts. Devices which were too thick for space change reach-through to occur at breakdown showed microwave oscillations, while thin diodes did not oscillate. Additionally, the structures could be distinguished on the basis of the noise accompanying breakdown. The performance was analysed in terms of transistor theory in which there is avalanche multiplication in the collector space charge region. It was concluded that there is a smooth transition between the reachthrough breakdown characteristic of the BARITT and true avalanche breakdown. The nature of the breakdown depends on the base width and the emitter efficiency.