High Mobility Strained Ge pMOSFETs With High-κ/Metal Gate

Compressively strained Ge long channel ring-type pMOSFETs with high-kappa Si/SiO₂/HfO₂/TiN gate stacks are fabricated on Si_0.2Ge_0.8 virtual substrates. Effective oxide thickness is approximately 1.4 nm with low gate leakage current. A peak hole mobility of 640 cm²/ Vldrs and up to a four times enhancement over the Si/SiO₂ universal curve are observed. Parasitic conduction within the Si-cap layers degrades the mobility at large vertical fields, although up to a 2.5 times enhancement over universal remains at a field of 0.9 MV/cm.     

Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer HfO2/SiO2 High- κ Gate Stack Observed by Using Low-Frequency Charge Pumping Method

Transient charging and discharging of border traps in the dual-layer HfO₂/SiO₂ high-kappa gate stack have been extensively studied by the low-frequency charge pumping method with various input pulse waveforms. It has been demonstrated that the exchange of charge carriers mainly occurs through the direct tunneling between the Si conduction band states and border traps in the HfO₂ high-kappa dielectric within the transient charging and discharging stages in one pulse cycle. Moreover, the transient charging and discharging behaviors could be observed in the time scale of 10^-8- 10^-4 s and well described by the charge trapping/detrapping model with dispersive capture/emission time constants used in static positive bias stress. Finally, the frequency and voltage dependencies of the border trap area density could also be transformed into the spatial and energetic distribution of border traps as a smoothed 3-D mesh profiling     

The scaled performance of Si/Si1-xGexresonant tunneling diodes

Small area resonant tunneling diodes (RTDs) with strained Si_0.4Ge_0.6 potential barriers and a strained Si quantum well grown on a relaxed Si_0.8Ge_0.2 virtual substrate were fabricated and characterized. A room temperature peak current density (J_P) of 282 kA/cm² with a peak to valley current ratio (PVCR) of 2.43 were recorded for a 5×5 μm ² sample, the highest values reported to date for Si/Si_1-xGe_x RTDs. Scaling of the device size demonstrated a decrease in J_P proportional to an increase in the lateral area of the tunnel junctions, whereas the PVCR remained approximately constant. This observation suggests that the dc behavior of such Si/Si_1-xGe_x RTD design is presently limited by thermal effects     

High performance Si/Si1-xGex resonanttunneling diodes

Resonant tunneling diodes (RTDs) with strained i-Si_0.4Ge_0.6 potential barriers and a strained i-Si quantum well, all on a relaxed Si_0.8Ge_0.2 virtual substrate were successfully grown by ultra high vacuum compatible chemical vapor deposition and fabricated using standard Si processing methods. A large peak to valley current ratio of 2.9 and a peak current density of 4.3 kA/cm² at room temperature were recorded from pulsed and continuous dc current-voltage measurements, the highest reported values to date for Si/Si_1-xGe_x RTDs. These dc figures of merit and material system render such structures suitable and highly compatible with present high speed and low power Si/Si_1-xGe_x heterojunction field effect transistor based integrated circuits     

Theoretical small-signal performance of Si/SiGe/Si HBT

Application of the Monte Carlo technique to analyze electron and hole transport in bulk Si_0.8Ge_0.2 and strained Si _0.8Ge_0.2/Si is discussed. The computed minority- and majority-carrier transport properties were used in a comprehensive small-signal model to evaluate the high-frequency performance of a state-of-the-art n-p-n heterostructure bipolar transistors (HBT) fabricated with SiGe as the base material. The valence band discontinuity of a SiGe-base HBT reverses the degradation in emitter injection efficiency caused by bandgap narrowing in the base, and permits a higher ratio of base doping to emitter doping than would be practical for a bipolar transistor. Any degradative effect of increased base doping on electron and hole mobilities is offset by improved transport in the strained SiGe base, resulting in a marked decrease in the base resistance and base transit time. Compared to the Si BJT, the use of Si_0.8Ge_0.2 for the base region of an HBT leads to significant improvements in low-frequency common emitter current gain, low-frequency unilateral power gain, and maximum oscillation frequency     

Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stack

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO ₂/HfO₂ gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO₂ layer and HfO₂/SiO₂ interface region. The trap density in the SiO₂ layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO₂ layer     

High-mobility strained-Si PMOSFET's

Operation and fabrication of a new high channel mobility strained-Si PMOSFET are presented. The growth of high-quality strained Si layer on completely relaxed, step-graded, SiGe buffer layer is demonstrated by gas source MBE. The strained-Si layer is characterized by double crystal X-ray diffraction, photoluminescence, and transmission electron microscopy. The operation of a PMOSFET is shown by device simulation and experiment. The high-mobility strained-Si PMOSFET is fabricated on strained-Si, which is grown epitaxially on a completely relaxed step-graded Si_0.82Ge_0.18 buffer layer on Si(100) substrate. At high vertical fields (high |V_g|), the channel mobility of the strained-Si device is found to be 40% and 200% higher at 300 K and 77 K, respectively, compared to those of the bulk Si device. In the case of the strained-Si device, degradation of channel mobility due to Si/SiO₂ interface scattering is found to be more pronounced compared to that of the bulk Si device. Carrier confinement at the type-II strained-Si/SiGe-buffer interface is clearly demonstrated from device transconductance and C-V measurements at 300 K and 77 K     

Work function of boron-doped polycrystallineSixGe1-x films

The work function of p-type polycrystalline Si_xGe_1-x films deposited by LPCVD using SiH₄ and GeH₄ was determined by CV measurements on MOS structures. Boron was introduced in the Si_xGe_1-x films either exsitu by ion implantation or insitu by adding B₂H₆ in the reactants during film deposition. The work function of the Si_xGe_1-x films is found to decrease as the Ge content increases; it is 5.16 eV for Si, 4.76 eV for Si_0.49Ge_0.51, and 4.67 eV for Ge. The work function of the Si and Ge films coincides well with that of single crystalline Si and Ge, respectively. It is also found that a thin Si adhesion layer of about 3 nm (nominal thickness), deposited prior to the Si_xGe_1-x, has a negligible effect on the work function determination     

Electron mobility enhancement in strained-Si n-MOSFETs fabricatedon SiGe-on-insulator (SGOI) substrates

We demonstrate electron mobility enhancement in strained-Si n-MOSFETs fabricated on relaxed Si_1-xGe_x-on-insulator (SGOI) substrates with a high Ge content of 25%. The substrates were fabricated by wafer bonding and etch-back utilizing a 20% Ge layer as an etch stop. Epitaxial regrowth was used to produce the upper portion of the Si_0.75Ge_0.26 and the surface strained Si layer. Large-area strained-Si n-MOSFETs were fabricated on this SGOI substrate. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFETs. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si_1-xGe_x layer     

SiGe pMODFETs on silicon-on-sapphire substrates with 116 GHzfmax

The dc and microwave results of Si_0.2Ge_0.8/Si_0.7Ge_0.3 pMODFETs grown on silicon-on-sapphire (SOS) substrates by ultrahigh vacuum chemical vapor deposition are reported. Devices with L_g=0.1 μm displayed high transconductance (377 mS/mm), low output conductance (25 mS/mm), and high gate-to-drain breakdown voltage (4 V). The dc current-voltage (I-V) characteristics were also nearly identical to those of control devices grown on bulk Si substrates. Microwave characterization of 0.1×50 μm² devices yielded unity current gain (f_T) and unilateral power gain (f _max) cutoff frequencies as high as 50 GHz and 116 GHz, respectively. Noise parameter characterization of 0.1×90 μm² devices revealed minimum noise figure (F_min) of 0.6 dB at 3 GHz and 2.5 dB at 20 GHz     

Novel SOI p-channel MOSFETs with higher strain in si channel usingdouble SiGe heterostructures

We have studied p-channel advanced SOI MOSFETs using double SiGe heterostructures fabricated by the combination of SIMOX and high-quality strained-Si/SiGe regrowth technologies, in order to introduce higher strain in Si channel. It was revealed that this double SiGe structure of second Si_0.82Ge_0.18Si_0.93Ge_0.07 allows the second SiGe layer to relax by about 70%, because of the elastic energy balance between the second and the first-SiGe layers. As a result, the strain of Si layer on this double SiGe structure becomes higher than that of the single SiGe structure. Strained SOI p-MOSFETs using the double layer SiGe structure exhibited higher hole mobility than that of strained-SOI MOSFETs with single Si_0.9Ge_0.1 structure. The hole mobility enhancement of 30% and 45% was achieved in the strained-SOI MOSFETs with double SiGe structures, compared to that of the universal curve and the control-SOI MOSFETs, respectively     

Fabrication and analysis of deep submicron strained-Si n-MOSFET's

Deep submicron strained-Si n-MOSFETs were fabricated on strained Si/relaxed Si_0.8Ge_0.2 heterostructures. Epitaxial layer structures were designed to yield well-matched channel doping profiles after processing, allowing comparison of strained and unstrained Si surface channel devices. In spite of the high substrate doping and high vertical fields, the MOSFET mobility of the strained-Si devices is enhanced by 75% compared to that of the unstrained-Si control devices and the state-of-the-art universal MOSFET mobility. Although the strained and unstrained-Si MOSFETs exhibit very similar short-channel effects, the intrinsic transconductance of the strained Si devices is enhanced by roughly 60% for the entire channel length range investigated (1 to 0.1 μm) when self-heating is reduced by an ac measurement technique. Comparison of the measured transconductance to hydrodynamic device simulations indicates that in addition to the increased low-field mobility, improved high-field transport in strained Si is necessary to explain the observed performance improvement. Reduced carrier-phonon scattering for electrons with average energies less than a few hundred meV accounts for the enhanced high-field electron transport in strained Si. Since strained Si provides device performance enhancements through changes in material properties rather than changes in device geometry and doping, strained Si is a promising candidate for improving the performance of Si CMOS technology without compromising the control of short channel effects     

High-κ Metal Gate MOSFETs: Impact of Extrinsic Process Condition on the Gate-Stack Quality—A Mobility Study

The effects of source/drain activation thermal budget and premetallization degas conditions on interfacial regrowth, carrier mobility, and defect densities are examined for SiO₂/HfO₂/TaN stacks. We observe a correlation between the mobility degradation and the interfacial re-growth possible with the thermal budget employed. The mobility degradation arises from an increase of defects, both within the interface layer (IL) and the high-kappa bulk, as detected by both pulsed current-voltage and charge-pumping measurements. Two junction activation processes have been applied: a conventional process (peak temperature of 1000 degC spike for t=1 s) and a Solid Phase Epitaxial Re-growth (SPER) (peak temperature of 650 degC for t=60 s). For 1000 degC spike-annealed films, where the highest SiO₂/IL defect density is observed, the consequent mobility degradation is explained by a transition region between HfO₂ and the IL which increases for high-temperature processing     

Numerical simulation and comparison of Si BJTs andSi1-xGex HBTs

Using the Monte Carlo method for the solution of the Boltzmann transport equation, the authors analyze the low-field carrier mobilities of strained layer and bulk Si and Si_1-xGe_x alloys. Strained alloy layers exhibit higher low-field mobility compared with bulk Si at doping levels >10¹⁸ cm^-3 and for a Ge mole fraction x⩽0.2, while the unstrained alloy bulk low-field mobility is always lower than that of Si for any doping level or mole fraction. These mobilities are then used in a two-dimensional drift-diffusion equation solver to simulate the performance of Si BJTs (bipolar junction transistors) and Si_1-xGe_x HBTs (heterojunction bipolar transistors). The substitution of a Si_0.8 Ge_0.2 layer for the base region leads to a significant improvement in current gain, turn-on voltage, and high-frequency performance. Maximum unity current gain frequency f_T increases two times over that of an Si BJT if the bulk alloy mobility is used for the alloy base layer; it increases three times if strained-layer mobility is used. Maximum frequency of oscillation also improves, but not as dramatically as f_T     

Measurement of Enhanced Gate-Controlled Band-to-Band Tunneling in Highly Strained Silicon-Germanium Diodes

Strained silicon-germanium (Si_0.6Ge_0.4) gated diodes have been fabricated and analyzed. The devices exhibit significantly enhanced gate-controlled tunneling current over that of coprocessed silicon control devices. The current characteristics are insensitive to measurement temperature in the 80 K to 300 K range. Independently extracted valence band offset at the strained Si_0.6Ge_0.4/Si interface is 0.4 eV, yielding a Si_0.6Ge_0.4 bandgap of 0.7 eV, which is much reduced compared to that of Si. The results are consistent with device operation based on quantum-mechanical band-to-band (BTB) tunneling rather than on thermal generation. Moreover, simulation of the strained Si_0.6Ge_0.4 device using a quantum-mechanical BTB tunneling model is in good agreement with the measurements.     

Low-frequency noise in Si0.7Ge0.3 surface channel pMOSFETs with ALD HfO2/Al2O3 gate dielectrics

Low-frequency noise was characterized in Si_0.7Ge_0.3 surface channel pMOSFETs with ALD Al₂O₃/HfO₂/Al₂O₃ stacks as gate dielectrics. The influences of surface treatment prior to ALD processing and thickness of the Al₂O₃ layer at the channel interface were investigated. The noise was of the 1/f type and could be modeled as a sum of a Hooge mobility fluctuation noise component and a number fluctuation noise component. Mobility fluctuation noise dominated the 1/f noise in strong inversion, but the number fluctuation noise component, mainly originating from traps in HfO₂, also contributed closer to threshold and in weak inversion. The number fluctuation noise component was negligibly small in a device with a 2 nm thick Al₂O₃ layer at the SiGe channel interface, which reduced the average 1/f noise by a factor of two and decreased the device-to-device variations.     

Fabrication of thin film transistors using a Si/Si1-xGex/Si triple layer film on a SiO2 substrate

A novel approach that can reduce the thermal budget in the fabrication of thin film transistors (TFTs) using a Si/Si_0.7Ge_0.3/Si triple film as an active layer was proposed. The crystallization behavior of the triple film was described and device characteristics of Si/Si_0.7Ge_0.3 /Si TFTs were compared with those of Si TFTs and of SiGe TFTs. The triple film was completely crystallized only after a 25-h anneal at 550°C. N-channel polycrystalline Si/Si_0.7Ge_0.3/Si TFTs had a field-effect mobility of 57.9 cm²/Vs and an I_on/I_off ratio of 5.7×10⁶. This technique provides not only a shorter time processing capability than Si TFT's technology but also superior device characteristics compared to SiGe TFTs     

High temperature formed SiGe p-MOSFETs with good devicecharacteristics

We have used a simple process to fabricate Si_0.3Ge_0.7/Si p-MOSFETs. The Si_0.3Ge _0.7 is formed using deposited Ge followed by 950°C rapid thermal annealing and solid phase epitaxy that is process compatible with existing VLSI. A hole mobility of 250 cm²/Vs is obtained from the Si_0.3Ge_0.7 p-MOSFET that is ~two times higher than Si control devices and results in a consequent substantially higher current drive. The 228 Å Si_0.3Ge_0.7 thermal oxide grown at 1000°C has a high breakdown field of 15 MV/cm, low interface trap density (D_it) of 1.5×10¹¹ eV^-1 cm^-2, and low oxide charge of 7.2×10¹⁰ cm^-2. The source-drain junction leakage after implantation and 950°C RTA is also comparable with the Si counterpart     

High quality gate dielectrics grown by rapid thermal processingusing split-N2O technique onstrained-Si0.91Ge0.09 films

Thermal stability and strain relaxation temperature of strained Si _0.91Ge_0.09 layers has been investigated using double crystal x-ray diffraction (DCXRD). High quality gate oxynitride layers rapid thermally grown on strained Si_0.91Ge_0.09 using N₂O and the split N₂O cycle technique below the strained relaxed temperature is reported. A positive fixed oxide charge density was observed for N₂O and split-N₂ O grown films. The O₂ grown films exhibit a negative fixed oxide charge. The excellent improvements in the leakage current, breakdown field and charge-to-breakdown value of the N₂O or split-N₂O grown films were achieved compared to pure O₂ grown films     

Carrier Transportation Mechanism of the $hbox{TaN}/ hbox{HfO}_{2}/hbox{IL}/hbox{Si}$ Structure With Silicon Surface Fluorine Implantation

In this paper, the current transportation mechanism of HfO₂ gate dielectrics with a TaN metal gate and silicon surface fluorine implantation is investigated. Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the current transport mechanisms and energy band diagrams for TaN/HfO₂/IL/Si structures with fluorine incorporation, respectively. In particular, we have obtained the following physical quantities: 1) fluorinated and as-deposited interfacial layer (IL)/Si barrier heights (or conduction band offsets) at 3.2 and 2.7 eV; 2) TaN/fluorinated and as-deposited HfO₂ barrier heights at 2.6 and 1.9 eV; and 3) effective trapping levels at 1.25 eV (under both gate and substrate injections) below the HfOF conduction band and at 1.04 eV (under gate injection) and 1.11 eV (under substrate injection) below the HfO₂ conduction band, which contributes to Frenkel-Poole conduction.