A comparative study of self-heating effect of nMOSFETs fabricated on SGOI and SGSOAN substrates

In this work, for the first time, the electrical and thermal characteristics of strained Si/SiGe nanoscale n type metal–oxide–silicon field-effect transistors (MOSFETs) with silicon-on-aluminum nitride (SOAN) substrate are investigated by ISE TCAD. This novel structure is named as SGSOAN nMOSFET. A comparative study of self-heating effect (SHE) of nMOSFETs fabricated on SGOI and SGSOAN are presented in this paper. Numerical study results show that this novel SGSOAN structure can greatly eliminate excessive self-heating in devices, which gives a more promising application for SGOI to work at high temperature.     

Fabrication and Simulation of Silicon-on-Insulator Structure with Si3N4 as a Buried Insulator

In order to minimize the self-heating effect of the classic SOI devices,SOI structures with Si3N4 film as a buried insulator (SOSN) are successfully formed using epitaxial layer transfer technology for the first time.The new SOI structures are investigated with high-resolution cross-sectional transmission electron microscopy and spreading resistance profile.Experiment results show that the buried Si3N4 layer is amorphous and the new SOI material has good structural and electrical properties.The output current characteristics and temperature distribution are simulated and compared to those of standard SOI MOSFETs.Furthermore,the channel temperature and negative differential resistance are reduced during high-temperature operation,suggesting that SOSN can effectively mitigate the self-heating penalty.The new SOI device has been verified in two-dimensional device simulation and indicated that the new structures can reduce device self-heating and increase drain current of the SOI MOSFET.     

以Si3N4为埋层的SOI结构制备与器件模拟

为了减少经典SOI器件的自加热效应,首次成功地用外延方法制备以Si3N4薄膜为埋层的新结构SOSN,用HRTEM和SRP表征了SOI的新结构.实验结果显示,Si3N4层为非晶状态,新结构的SOSN具有良好的结构和电学性能.对传统SOI和新结构SOI的MOSFETs输出电流的输出特性和温度分布用TCAD仿真软件进行了模拟.模拟结果表明,新结构SOSN的MOSFET器件沟道温度和NDR效益都得到很大的降低,表明SOSN能够有效地克服自加热效应和提高MOSFET漏电流.     

SOI MOSFET自加热效应测试方法

为研究自加热效应对绝缘体上硅(SOI)MOSFET漏电流的影响,开发了一种可同时探测20 ns时瞬态漏源电流-漏源电压(Ids-Vds)特性和80μs时直流静态Ids-Vds特性的超快脉冲I-V测试方法。将被测器件栅漏短接、源体短接后串联接入超快脉冲测试系统,根据示波器在源端采集的电压脉冲的幅值计算漏电流受自加热影响的动态变化过程。选取体硅NMOSFET和SOI NMOSFET进行验证测试,并对被测器件的温度分布进行仿真,证实该方法用于自加热效应的测试是准确有效的,能为建立准确的器件模型提供数据支撑。采用该方法对2μm SOI工艺不同宽长比的NMOSFET进行测试,结果表明栅宽相同的器件,栅长越短,自加热现象越明显。     

Numerical Study of C–V Characteristics of Double-Gate Ultrathin SOI MOSFETs

Capacitance-voltage (C-V) characteristics of double-gate ultrathin silicon-on-insulator (SOI) MOSFETs are numerically investigated in detail. The measured back-gate bias dependence is reproduced by the Poisson-Schrodinger solver including the highly precise physical models for many-body interactions of carrier-carrier and carrier-ion, and for incomplete ionization of doping impurities in whole semiconductor regions of n⁺poly-Si/oxide/SOI/oxide/p-Si capacitor including the volume inversion. In addition, we study the higher subband effect at higher temperature in detail, in order to deduce the impacts of self-heating and nonstatic transport     

Investigation of the Electrical and Thermal Performance of SOI MOSFETs with Modified Channel Engineering

In this paper, we present a novel type of channel doping engineering, using a graded doping distribution, that improves the electrical and thermal performance of silicon-on-insulator (SOI) metal–oxide–semiconductor field effect transistors (MOSFETs), according to simulations that we have performed. The results obtained include a reduction in the self-heating effect, a reduction in leakage currents due to the suppression of short-channel effects (SCEs), and a reduction in hot-carrier degradation. We term the proposed structure a modified-channel-doping SOI (MCD-SOI) MOSFET. The main reason for the reduction in the self-heating effect is the use of a lower doping density near the drain region in comparison with conventional SOI MOSFETs with a uniform doping distribution. The most significant reason for the leakage current reduction in the MCD-SOI structure is the high potential barrier near the source region in the weak inversion state. The SCE factors, including the drain-induced barrier lowering, subthreshold swing, and threshold voltage roll-off, are improved. A highly reliable structure is achieved owing to the lower doping density near the drain region, which reduces the peak electric field and the electron temperature.     

Scaling constraints imposed by self-heating in submicron SOIMOSFET's

The presence of a buried oxide layer in silicon causes enhanced self-heating in Silicon-On-Insulator (SOI) n-channel MOSFETs. The self-heating becomes more pronounced as device dimensions are reduced into the submicron regime because of increased electric field density and reduced silicon volume available for heat removal. Two-dimensional numerical simulations are used to show that self-heating manifests itself in the form of degraded drive current due to mobility reduction and premature breakdown. The heat flow equation was consistently solved with the classical semiconductor equations to study the effect of power dissipation on carrier transport. The simulated temperature increases in the channel region are shown to be in close agreement with recently measured data. Numerical simulation results also demonstrated accelerated turn-on of the parasitic bipolar transistor due to self-heating. Simulation results were used to identify scaling constraints caused by the parasitic bipolar transistor turn-on effect in SOI CMOS ULSI. For a quarter-micron n-channel SOI MOSFET, results suggest a maximum power supply of 1.8 V. In the deep submicron regime, SOI devices exhibited a negative differential resistance due to increased self-heating with drain bias voltage. Detailed comparison with bulk devices suggested significant reduction in the drain-source avalanche breakdown voltage due to increased carrier injection at the source-body junction     

采用局域注氧技术制备的新型DSOI场效应晶体管的热特性

通过局域注氧工艺,在同一管芯上制作了DSOI、体硅和SOI三种结构的器件.通过测量和模拟比较了这三种结构器件的热特性.模拟和测量的结果证明DSOI器件与SOI器件相比,具有衬底热阻较低的优点,因而DSOI器件在保持SOI器件电学特性优势的同时消除了SOI器件严重的自热效应.DSOI器件的衬底热阻和体硅器件非常接近,并且在进入到深亚微米领域以后能够继续保持这一优势.     

Direct extraction of MOSFET dynamic thermal characteristics from standard transistor structures using small signal measurements

A method is presented for directly obtaining the temperature rise in MOSFETs due to channel current self-heating. The technique is based on small signal measurements, and also provides thermal time-constant data. No special layout structures are needed, making it suitable for bulk and SOI technologies. Experimental results are compared with data obtained using thermal noise measurements with a special SOI MOSFET, and the two figures show good agreement.<>     

Efficient thermal modeling of SOI MOSFETs for fast dynamic operation

An efficient dynamic thermal model has been developed for silicon-on-insulator (SOI) MOSFETs. The model is derived from the variational principle using a thermal functional, and is able to describe extremely fast dynamic thermal behavior in SOI devices subjected to sudden changes in power generation. The developed model is further converted into a thermal circuit with time-varying thermal resistances and capacitances. With the circuit implemented in a circuit simulator, these time-varying thermal resistances and capacitances are able to reasonably capture extremely fast temperature evolution in SOI devices without including a large number of nodes. The developed dynamic thermal model and circuit are verified with the rigorous device simulation including self-heating.     

Analysis of Self-Heating Effects in Ultrathin-Body SOI MOSFETs by Device Simulation

This paper discusses self-heating (SHE) effects in silicon-on-insulator (SOI) CMOS technology and applies device simulation to analyze the impact of thermal effects on the operation of nanoscale SOI n-MOSFETs. A 2-D drift-diffusion electrothermal simulation, using an electron transport model calibrated against Monte Carlo simulations at various temperatures, is employed in the analysis. We report the effects of device-structure parameters, such as SOI layer thickness, buried-oxide (BOX) thickness, source/drain (S/D) extension length, and thickness of the elevated S/D region, on the SHE of nanoscale MOSFETs. The SHE effects become significant due to the adoption of thin silicon layers and to the low thermal conductivity of the BOX, leading to the rise of large temperature under nominal operation conditions for high-performance digital circuits. The ac performance of SOI MOSFETs is influenced as well, and in particular, a severe degradation of the cutoff frequency of very short MOSFETs is predicted by numerical electrothermal device simulations. Although the effects of SHE on device performance are found to be somewhat modest and might be mitigated through device design, they may result in a degradation of the long-term reliability.     

一种采用局域注氧技术制备的新型DSOI器件

为了克服传统SOI器件的浮体效应和自热效应,采用创新的工艺方法将低剂量局域SIMOX工艺及传统的CMOS工艺结合,实现了DSOI结构的器件.测试结果表明,该器件消除了传统SOI器件的浮体效应,同时自热效应得到很大的改善,提高了可靠性和稳定性.而原先SOI器件具备的优点得到了保留     

SOI thermal impedance extraction methodology and its significancefor circuit simulation

The buried-oxide in SOI MOSFET inhibits heat dissipation in the Si film and leads to increase in transistor temperature. This paper reports a simple and accurate characterization method for the self-heating effect (SHE) in SOI MOSFETs. The AC output conductance at a chosen bias point is measured at several frequencies to determine the thermal resistance (R_th) and thermal capacitance (C_th) associated with the SOI device. This methodology is important to remove the misleadingly large self-heating effect from the DC I-V data in device modeling. Not correcting for SHE may lead to significant error in circuit simulation. After SHE is accounted for, the frequency-dependent SHE may be disabled in circuit simulation without sacrificing the accuracy, thus providing faster circuit simulation for high-frequency circuits     

一种采用局域注氧技术制备的新型DSOI器件

为了克服传统SOI器件的浮体效应和自热效应,采用创新的工艺方法将低剂量局域SIMOX工艺及传统的CMOS工艺结合,实现了DSOI结构的器件.测试结果表明,该器件消除了传统SOI器件的浮体效应,同时自热效应得到很大的改善,提高了可靠性和稳定性.而原先SOI器件具备的优点得到了保留.     

Special mechanisms in thin-film SOI MOSFETs

The main special mechanisms that govern the operation of thin-film SOI MOSFETs are reviewed. The influence of the most important technological and electrical parameters, e.g. the film and buried oxide thicknesses, film and silicon substrate doping, channel length, substrate bias, and interface defects, is discussed. The electrical properties of fully depleted thin-film SOI MOS transistors are improved, especially the driving current and the subthreshold swing. We address the advantages of thin-film SOI devices in relation to scaling rules down to deep submicron transistors, as well as the main parasitic phenomena, e.g. the kink, latch, breakdown, self-heating and hot-carrier degradation effects. Finally, the low temperature properties and potential quantum effects are outlined.     

Deep submicron PDSOI thermal resistance extraction

Deep submicron partially depleted silicon on insulator (PDSOI) MOSFETs with H-gate were fabricated based on the 0.35μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences. Because the self-heating effect (SHE) has a great influence on SOI, extractions of thermal resistance were done for accurate circuit simulation by using the body-source diode as a thermometer. The results show that the thermal resistance in an SOI NMOSFET is lower than that in an SOI PMOSFET; and the thermal resistance in an SOI NMOSFET with a long channel is lower than that with a short channel. This offers a great help to SHE modeling and parameter extraction.     

Wafer level measurements and numerical analysis of self-heating phenomena in nano-scale SOI MOSFETs

We present an experimental technique and a Finite Element thermal simulation for the determination of the temperature elevation in Silicon on Insulator (SOI) MOSFETs due to self-heating. We evaluate the temperature elevation in two steps, as we calibrate the gate resistance over temperature with the transistor at off state at a first stage, and then we deduce the temperature elevation through gate resistance measurements. We simulate the self-heating phenomena in a Finite Elements Method (FEM) environment, both with 2D and 3D models. In order to set up the simulations, we weight the effects of several parameters, such as thermal material properties, the modeling of heat generation and a careful setting of boundary conditions. We present typical temperature fields and local heat fluxes, thus giving concrete indications for solving thermal reliability issues. Simulation results show temperature elevations up to approximately 120 K in the hot spot, 70 K in the gate and 7 K in the Back End of Line (BEoL). The 3D model gives results that are satisfying over the whole set of MOSFETs we consider in this work. Temperature elevation strongly depends on physical dimensions, where transistors endowed with shorter gates suffer from more severe self-heating. We propose a simplified model based on geometrical parameters that predict maximum and gate temperatures, obtaining satisfying results. Since correlation with measurements confirms the correctness of our model, we believe that our simulations could be a useful tool to determine accurate reliability rules and in a context of thermal aware design.     

Impact of device physics on DG and SOI MOSFET linearity

The influence of different physical mechanisms on MOSFET linearity is analyzed using 2D TCAD device simulations. In particular, the RF linearity performance of 50 nm gate length SOI and DG-MOSFETs are investigated and compared with traditional bulk MOSFETs. We employ the hydrodynamic (HD) transport model to account for non-equilibrium carrier dynamics and the density gradient approximation for quantum mechanical effects. Impact ionization of channel carriers and self-heating effect (SHE) are also accounted for in the thin-body devices. Our results disclose the relationship between various aspects of device physics and linearity. We show that linearity performance is particularly sensitive to non-local effects and are lowered due to SHE. Quantum mechanical effects appear to have a small positive impact on linearity. Drift-diffusion approximation is found to be unreliable for linearity analysis of DG MOSFETs due to large overestimation from this model. We also observe that linearity has an anomalous monotonous dependence on the ambient temperature.     

SOI反偏肖特基势垒动态阈值MOS特性

将Ti硅化物-p型体区形成的反偏肖特基势垒结构引入绝缘体上硅动态阈值晶体管.传统栅体直接连接DTMOS,为了避免体源二极管的正向开启,工作电压应当低于0.7V.而采用反偏肖特基势垒结构,DTMOS的工作电压可以拓展到0.7V以上.实验结果显示,室温下采用反偏肖特基势垒SOI DTMOS结构,阈值电压可以动态减小200mV.反偏肖特基势垒SOI DTMOS结构相比于传统模式,显示出优秀的亚阈值特性和电流驱动能力.另外,对浮体SOI器件、传统模式SOI器件和反偏肖特基势垒SOI DTMOS的关态击穿特性进行了比较.     

Physical modeling of temperature dependences of SOI CMOS devicesand circuits including self-heating

To simulate and examine temperature and self-heating effects in Silicon-On-Insulator (SOI) devices and circuits, a physical temperature-dependence model is implemented into the SOISPICE fully depleted (FD) and nonfully depleted (NFD) SOI MOSFET models. Due to the physical nature of the device models, the temperature-dependence modeling, which enables a device self-heating option as well, is straightforward and requires no new parameters. The modeling is verified by DC and transient measurements of scaled test devices, and in the process physical insight on floating-body effects in temperature is attained. The utility of the modeling is exemplified with a study of the temperature and self-heating effects in an SOI CMOS NAND ring oscillator. SOISPICE transient simulations of the circuit, with floating and tied bodies, reveal how speed and power depend on ambient temperature, and they predict no significant dynamic self-heating, irrespective of the ambient temperature