CCⅡ低通滤波器的PSpice仿真分析

用子电路模块代替电路中的关键元件,采用理论分析与PSpice的参数扫描分析和优化分析相结合的方法对电路进行最优化设计,结合一个CCⅡ低通滤波电路的设计实例,阐述了仿真分析方法的具体步骤,给出了滤波电路最优化设计的仿真分析结果,该结果符合设计理论分析值的要求。对优化后的电路进行了温度扫描分析、蒙托卡诺分析和最坏情况分析。仿真结果表明,该方法在电路设计中是可行的。     

带通滤波电路故障的BP网络诊断方法与仿真设计

本文在传统诊断技术理论基础上,将BP神经网络方法应用到模拟电路故障诊断的故障诊断中,分析了带通滤波电路故障的BP网络及人工神经网络的故障诊断方法;利用PSPice仿真软件和MATLAB仿真软件对电路进行了故障诊断,对几种常见模拟电路的故障机理作了初步研究,给出了实验结果。     

PSPICE6.3中电路的容差分析

本文详细介绍了PSPICE6．3通用电路分析软件，进行电路容差分析的方法，并举例说明WorstCase（最坏情况）和MonteCarlo（蒙特卡罗）分析的基本步骤。     

基于仿真的电路故障模式识别研究

电路故障仿真技术是实现电子产品功能设计与可靠性测试性一体化设计的核心技术,也是当前国内外系统可靠性分析的热点.本文介绍了电路故障仿真原理和方法,在电路板级故障仿真数据处理基础上,建立了用K-平均值法和判别分析法相结合的故障模式分类方法,对电路板级的故障模式进行识别分类,分类的结果作为系统级故障仿真的输入,以获取对系统级电路的故障影响分析,从而为实现系统级电路自动FMEA提供支持.     

基于Multisim的三相电路仿真

三相电路是日常生产和生活中应用广泛的电路,通过实验方法研究和分析三相电路的运行情况显得很有必要,但由于三相电路的实验有一定的危险性,而且某些故障性实验可能会对元件甚至整个电力系统造成破坏,因此三相电路的实验难以实施。通过三相负载对电路的影响的理论分析,阐述了供电系统中采用三相四线制的原因,并利用Multism仿真软件进行仿真。通过虚拟实验的方法验证了理论分析的结果,表明了运用Multism仿真是进行电路分析的一个有效手段。     

基于故障注入的基准电路故障响应分析

为了提高集成电路的成品率,试图采用更简便有效的方法测试芯片,并获得反映电路特性的故障响应率,在进行电路功能仿真(前仿真)或电路时序仿真(后仿真)的过程中,对电路注入单故障或多故障,然后在电路存在故障的情况下,模拟电路的行为,获得电路的故障响应率.实现了一个通用的数字电路"故障响应分析"程序,他模拟电路注入故障,收集模拟结果,通过分析获取电路的故障响应率.     

基于EDA的电子产品一体化设计分析技术

以故障仿真分析为核心的可靠性与性能一体化设计分析技术,是一项电子产品研制阶段及时发现设计缺陷并有效提升产品固有可靠性的重要技术.简要回顾了相关技术的发展,分析了高可靠电子产品对该技术的需求,阐述了应用电子设计自动化（EDA）工具实现电路性能和可靠性的一体化设计的技术流程,给出了以故障仿真分析为核心实现电路一体化设计的思路.最后着重介绍了建立电路可靠性与性能一体化设计与仿真分析环境时面临的故障建模、故障注入、故障判别、数据接口、仿真效率等关键技术的解决方法,为该技术实现工程实用性提供了重要支持.     

基于EWB的电路容差分析

用电子电路仿真软件EWB是分析电路容差的一种有效、可靠、快捷的方法。举例说明用EWB进行最坏情况分析和蒙托卡诺分析的具体方法和步骤。     

遥控接收机天线匹配电路设计及仿真

针对车载遥控接收机天线馈电端口不匹配的情况,利用电磁仿真软件FEKO对天线馈电端口的驻波比、输入阻抗进行仿真分析。由匹配电路设计软件ADS得到分立LC匹配电路,并在FEKO软件中通过非辐射网络来模拟天线的匹配电路,实现天线匹配网络与天线的一体化仿真。仿真表明,遥控接收机天线馈电端口的驻波比由3.96降至1.5以下。     

基于Multisim8的电压串联负反馈放大器仿真

采用Multisim8软件创建负反馈放大电路,利用其虚拟仪表和仿真分析了功能测试和仿真分析负反馈对放大电路的影响,通过对串联负反馈放大电路的理论研究和利用Multisim8仿真软件对电路实际工作情况进行模拟,根据二者结果的对比,研究并提出了串联负反馈放大电路的Multisim电路仿真研究的方法。Multisim8仿真分析中图像清晰、现象直观、结果精确,是一种有效的辅助实验手段。     

电路故障仿真中的故障建模、注入及判定方法研究

针对“性能可靠性一体化设计”这一热点研究方向,文章提出了将EDA仿真和故障注入相结合的电路故障仿真方法。从介绍该方法的基本原理出发,详细论述了其中包含的故障建模、故障注入、故障判定的方法;通过对典型案例的仿真分析,验证了电子系统故障仿真方法的正确性,并证明该方法具有很强的工程实用价值。     

A practical methodology for the statistical design of complex logicproducts for performance

Contradictory trends in the industrial design environment have increased uncertainty while decreasing the tolerance to uncertainty. Worst case design techniques, still widely used in industry, do not provide the accuracy required to design under these conditions. On the other hand, statistical design techniques do provide a significant improvement in accuracy, by virtue of their “circuit adaptive” behavior, but at a substantial cost in computational effort. One practical solution to improving the accuracy of worst case design without sacrificing efficiency is considered here. It integrates an efficient statistical circuit simulator with worst case design tools into a hierarchical performance design process. It employs two stages of worst case analysis, calibrated with statistical circuit simulation, serving as filters to screen out circuits that easily meet their performance requirements. This focuses the use of statistical circuit simulation on those circuits for which the improved accuracy provides significant benefit. This methodology has been applied with outstanding results in design and manufacturing     

Statistical device models from worst case files and electrical testdata

Two statistical metal oxide semiconductors (MOS) models are described, one based on worst case files and the other on electrical test data. The former is appropriate for predicting the variability of a process early in its life cycle, while the latter would better track a maturing process. The key statistical tool that is used to develop the models is principal component analysis (PCA), which is used in novel ways in order to derive statistical models from readily available information. The models are used to perform statistical circuit simulation in order to quantitatively predict the impact of manufacturing variations on circuit performance metrics. Due to the use of linear response surface modeling and latin hypercube sampling, the simulation cost of using the models is about the same as with worst case simulation. The modeling technique is general and is applicable to other semiconductor devices besides MOS devices which are considered in this paper     

一种新的缩短随机测试序列长度的方法

本文提出了一种新的缩短随机测试序列长度的方法,它是在找到电路中难测故障分布的基础上,通过对电路的初始输入施加概率不等的“１”信号,使这些难测故障的测试率升至最大值,这样,就可以达到提高故障覆盖率和缩短测试序列长度的目的。     

On the performance of early packet discard

In a previous paper, one of the authors gave a worst case analysis for the early packet discard (EPD) technique for maintaining packet integrity during overload in ATM switches. This analysis showed that to ensure 100% goodput during overload under worst case conditions requires a buffer with enough storage for one maximum length packet from every active virtual circuit. This paper refines that analysis, using assumptions that are closer to what we expect to see in practice, and examines how EPD performs when the buffer is not large enough to achieve 100% goodput. We show that 100% goodput can be achieved with substantially smaller buffers than predicted by the worst case analysis, although the required buffer space can be significant when the link speed is substantially higher than the rate of the individual virtual circuits. We also show that high goodputs can be achieved with more modest buffer sizes, but that EPD exhibits anomalies with respect to buffer capacity, in that there are situations in which increasing the amount of buffering can cause the goodput to decrease. These results are validated by comparison with simulation     

A fault detection sensor for circuit aging using double-edge-triggered flip-flop

In nanoscale technology, transistor aging is one of the most critical problems that impact on the reliability of circuits. Aging sensor is a good online way to detect the circuit aging, which performs during the operating time with no influence of the normal operation of circuits. In this paper, a Double-edge-triggered Detection Sensor for circuit Aging (DSDA) is proposed, which employs data signal of logic circuits as its clock to control the sampling process. The simulation is done by Hspice using 45 nm technology. The results show that this technique is not sensitive to the process variations. The worst case of the detection precision is more than 80% under the different process variations. It can detect aging fault effectively with the 8% power cost and 30% performance cost.     

基于故障仿真和粗糙集的复杂电路板测试性分析

针对关联模型在复杂电路板测试性分析中对不确定问题描述与分析的缺陷,提出了基于故障仿真和粗糙集的测试性分析方法.通过故障仿真生成条件属性集,利用粗糙集将其约简,最终形成分辨矩阵,从而评价电路的测试性水平.最后通过实例分析验证了方法的有效性.     

一种基于多频灵敏度分析的模拟电路K故障诊断方法

在模拟电路灵敏度分析的基础上，提出了多频灵敏度K故障诊断方法，详细说明了多频灵敏度K故障诊断方法的原理和步骤。针对模拟电路中最常见的双故障进行了电路仿真，仿真结果说明了该方法的有效性。     

TBSA: Threshold-Based Simulation Accuracy Method for Fast Analog DC Fault Simulation

Starting from a good solution approximation has proved to be very efficient to reduce CPU time required by DC simulation of analog circuits. In order to obtain an additional speedup in DC fault simulation, this paper proposes a new criterion to end the Newton-Raphson (NR) iterative algorithm before convergence. In the case where an initial solution approximation is used, the analysis of the NR algorithm behavior until convergence is presented and a threshold-based simulation accuracy (TBSA) method is then proposed. TBSA stops the iterations when the solution at current NR iteration is enough accurate to immediately classify the fault. According to the detection thresholds, a CPU time/accuracy tradeoff is achieved without altering the fault classification results. The proposed method has been validated on 12 MOS and BJT benchmark circuits considering DC fault simulation under process parameter variations. TBSA is compared to two existing methods which are: standard simulation until convergence method which is accurate but requires a large CPU time, and single NR iteration method which is very fast but without any control over the accuracy. All the compared methods reuse the fault-free circuit results as initial solution for each faulty circuit simulation. It is shown that TBSA requires an intermediate number of NR iterations while achieving correct fault classification, especially for parametric faults which take advantage of using a more accurate initial solution.