Low supply voltage operation of over-40-Gb/s digital ICs based on parallel-current-switching latch circuitry

We implemented a low-voltage latch circuit topology in a full-rate 4:1 multiplexer (MUX) using InP-HBT technology. The proposed latch circuitry incorporates parallel current switching together with inductive peaking a combination that makes it suitable for over-40-Gb/s operation at supply voltages ranging from 1.5 to 1.8 V. The full-rate 4:1 MUX provided 40-Gb/s error-free operation with a power dissipation of only 1 W at a supply voltage of 1.8 V. The D-flip/flop (D-F/F) based on this latch circuitry provided 50-Gb/s D-F/F operation at a supply voltage as low as 1.5 V. Demultiplexing operation was also confirmed for the D-F/F with this circuit technology at a data rate of up to 110Gb/s with a 1.8-V supply voltage. The latch circuitry should help enable development of a low-voltage 40-Gb/s full-rate module which can be seamlessly connected with high-speed CMOS I/O circuits.     

A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20MS/s and 54-dB S/N at 30 MS/s

A new video-speed current-mode CMOS sample-and-hold IC has been developed. It operates with a supply voltage as low as 1.5 V, a signal-to-noise ratio (S/N) of 57 dB and 54 dB with a 1-MHz input signal at clock frequencies of 20 and 30 MHz, and a power dissipation of 2.3 mW. It consists of current-mirror circuits with the node voltages at the input and the output terminals which are kept constant in all phases of the input signal by the use of low-voltage operational amplifiers; this reduces the signal current dependency. The low-voltage operational amplifier consists of a MOS transistor and a constant current source in a common-gate amplifier configuration. Only two analog switches in differential form were used to construct the differential sample-and-hold circuit. This minimizes the error caused by the switch feed through, and thus high accuracy can be realized. Since there is no analog switch in the input path, it is possible to convert the input signal voltage to a current by simply connecting an external resistor. The circuit was fabricated using standard 0.6-μm MOS devices with normal threshold voltages (V_th) of +0.7 V (nMOS) and -0.7 V (pMOS)     

Low-voltage FGMOS based analog building blocks

Novel floating gate MOSFET (FGMOS) based low-voltage analog circuits such as current-to-voltage converter, current-mode divider and pseudo-exponential function generator are proposed in this paper. The inherent advantages of these circuits are their simplicity, accuracy and low power dissipation. The current-to-voltage converter is operated with a single power supply of 0.9 V. The current-mode divider and pseudo-exponential function generator are operated at supply voltages of ±0.9 V. It was observed that the power dissipation of the current-to-voltage converter is reduced to 12 μW using a single power supply. The power dissipations of the current-mode divider and pseudo-exponential function generator are found to be 356 and 471 μW, respectively. The proposed circuits are simulated using SPICE in 0.5 μm CMOS process technology to demonstrate the feasibility and the effectiveness of the proposed circuits.     

Low-voltage high-gain differential OTA for SC circuits

A new differential operational transconductance amplifier (OTA) for SC circuits that operates with a supply voltage of less than two transistor threshold voltages is presented. Its simplicity relies on the use of a low-voltage regulated cascode circuit, which achieves very high output impedance under low-voltage restrictions. The OTA has been designed to operate with a supply voltage of V/sub DD/=1.5 V, using a 0.6 /spl mu/m CMOS technology with transistor threshold voltages of V/sub TN/=0.75 V and V/sub TP/=-0.85 V. Post-layout simulation results for a load capacitance (C/sub L/) of 2 pF show a 75 MHz gain-bandwidth product and 100 dB DC gain with a quiescent power consumption of 750 /spl mu/W.     

数字电视用高压开关电源设计

描述一种用于数字彩电的小功率高压开关电源的基本工作原理及设计要点。该开关电源采用了高压发生电路与行扫描电路相分离的独立结构。独立振荡器产生的开关信号提供给开关管,推动高压变压器输出CRT管所需的阳极高压,并通过对阳极高压取样,控制振荡信号频率,以达到稳定高压的目的,彻底解决了大屏幕显像管所需的阳极高压及其稳定性问题。采用独立高压供电方案,行扫描电路的设计和调整得以简化,也使行扫描输出电路负载过重问题得到较好的解决。     

Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM

Circuit techniques for battery-operated DRAMs which cover supply voltages from 1.5 to 3.6 V (universal V_cc), as well as their applications to an experimental 64-Mb DRAM, are presented. The universal-V_cc DRAM concept features a low-voltage (1.5 V) DRAM core and an on-chip power supply unit optimized for the operation of the DRAM. A circuit technique for oxide-stress relaxation is proposed to improve high-voltage sustaining characteristics while only scaled MOSFETs are used in the entire chip. This technique increases sustaining voltage by about 1.5 V compared with conventional circuits and allows scaled MOSFETs to be used for the circuits, which can be operated from an external V_cc of up to 4 V. A two-way power supply scheme is proposed to suppress the internal voltage fluctuation within 10% when the DRAM is operated from external power supply voltages ranging from 1.5 to 3.6 V. An experimental 1.5-3.6-V 64-Mb DRAM is designed based on these techniques and fabricated by using 0.3-μm electron-beam lithography. An almost constant access time of 70 ns is obtained. This indicates that battery operation is a promising target for future DRAMs     

A low-voltage,versatile CMOS four-quadrant analogue multiplier

This paper describes a four-quadrant analogue multiplier circuit using a low-voltage power supply. It comprises two voltage/current adders and a basic multiplier. Its major advantages over other low-voltage multipliers are that it can operate on either a single power supply or two power supplies, and that its output can be the product of two signal currents, the product of two signal voltages, or the product of a signal current and a signal voltage. Second-order effects were analysed and the simulated results revealed that: (1) for a two-power supply voltage of 2?V, the total harmonic distortion is about 1%, whereas the input voltage is 0.4?V_P–P, the power dissipation is about 0.4?mW and the ?3?dB bandwidth is more than 55?MHz; (2) for a single-power supply voltage of 2?V, the total harmonic distortion is about 1%, whereas the input voltage is 0.4?V_P–P, the power dissipation is about 0.2?mW and the ?3?dB bandwidth is more than 55?MHz. Experimental results are provided to confirm the operation of the circuit.     

A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme

Multithreshold-voltage CMOS (MTCMOS) technology has a great advantage in that it provides high-speed operation with low supply voltages of less than 1 V. A logic gate with low-V/sub th/ MOSFETs has a high operating speed, while a low-leakage power switch with a high-V/sub th/ MOSFET eliminates the off-leakage current during sleep time. By using MTCMOS circuits and silicon-on-insulator (SOI) devices, the authors have developed a 256-kb SRAM for solar-power-operated digital equipment. A double-threshold-voltage MOSFET (DTMOS) is adopted for the power switch to further reduce the off leakage. As regards the SRAM core design, we consider a hybrid configuration consisting of high-V/sub th/ and low-V/sub th/ MOSFETs (that is, multi-V/sub th/ CMOS). A new memory cell with a separate read-data path provides a larger readout current without degrading the static noise margin. A negatively overdriven bitline scheme guarantees sure write operation at ultralow supply voltages close to 0.5 V. In addition, a charge-transfer amplifier integrated with a selector and data latches for intrabus circuitry are installed to enhance the operating speed and/or reduce power dissipation. A 32K-word /spl times/ 8-bit SRAM chip, fabricated with the 0.35-/spl mu/m multi-V/sub th/ CMOS/SOI process, has successfully operated at 25 MHz under typical conditions with 0.5-V (SRAM core) and 1-V (I/O buffers) power supplies. The power dissipation during sleep time is less than 0.4 /spl mu/W and that for 25-MHz operation is 1 mW, excluding that of the I/O buffers.     

A power IC technology with excellent cross-talk isolation

This paper reports a low-cost, excellent cross-talk isolation power integrated circuit (PIG) technology capable of integrating high-voltage LDMOS, high-voltage LIGBT, and low-voltage CMOS control circuit. The technology is implemented using a conventional twin-well CMOS process with no compromise on the CMOS devices, and the breakdown voltages of the LDMOS and LIGBT with drift length of 40 μm are over 400 V. Using this technology, operating current of the body diode of the LDMOS can be improved by over 16 times and operating current of the LIGBT can be improved by over five times before CMOS latch-up in the control circuit occurs     

FGMOS based voltage-controlled resistor and its applications

The paper presents floating gate MOSFET (FGMOS) based low-voltage tunable resistor operating at supply voltages of ±0.75 V. The proposed circuit is then used as basic building block to develop tunable negative resistor, current-mode divider, and variable transresistance amplifier. The circuit is simple, compact, and accurate. The total power dissipation of the proposed circuit is 18.6 μW. The circuits are simulated to demonstrate the effectiveness using SPICE in 0.5-μm CMOS technology.     

改进结构的低压低功耗CMOS带隙基准源

提出了一种低电压、低功耗、中等精度的带隙基准源,针对电阻分流结构带隙基准源在低电源电压下应用的不足作出了一定的改进,整体电路结构简单且便于调整,同时尽可能地减少了功耗.该电路采用UMC 0.18 μm Mixed Mode 1.8 V CMOS工艺实现.测试结果表明,电路在1 V电源电压下,在-20～30℃的温度范围内,基准电压的温度系数为20×10-6/℃,低频时的电源电压抑制比为-54 dB,1 V电源电压下电路总功耗仅为3μW.     

低电压低功耗ECL电路设计

首先指出了 ECL电路随着集成度和速度的提高 ,存在着功耗太大的问题 ,进而提出了采用低电压电源以降低功耗 ,为此发展了将串联开关转换成并联开关的技术 ,保证了电路能在低电压下正常工作 ,并由此实现了适合于低电压工作的 ECL电路的开关级设计。从对设计的电路进行的计算机模拟结果表明 ,采用文中提出的并联开关技术设计的电路 ,在电源电压为 -2 .5 V时 ,不仅具有正确的逻辑功能和较高的工作速度 ,且比采用-5 .0 V电源的电路节约了 80 %以上的功耗     

普通高压电源超二代微光像增强器亮度增益温度特性研究

针对匹配普通高压电源的超二代微光像增强器亮度增益在高温条件下大幅下降的问题,根据理论分析搭建了高低温试验平台,并分别对普通高压电源超二代像增强器、像增强管和普通高压电源的高低温特性进行研究。试验结果表明,匹配普通高压电源的超二代像增强器高温（55℃）亮度增益与低温（-55℃）相比衰减约65%;在阴极电压、MCP电压和阳极电压恒定的条件下,像增强管高温亮度增益仅衰减约20%,且主要是由于阴极灵敏度和荧光屏发光效率随温度升高而降低导致的;普通高压电源高温（55℃）与低温（-55℃）相比阴极电压降低约40 V,MCP电压降低约18 V,阳极电压降低约100 V,三者共同作用加剧了普通高压电源超二代像增强器高温亮度增益的衰减。因此,在高温条件下通过软、硬件的方式对电源阴极电压、MCP电压和阳极电压进行补偿是提高普通高压电源超二代微光像增强器高低温亮度增益一致性的有效手段。     

A 15-GHz monolithic two-modulus prescaler

A high-speed two-modulus prescaler for divide-by-4/5 select was successfully realized adopting a new circuit design that reduces the effective fan-out of each D-flip-flop (D-FF) to one. To assure stable and high-speed operation, a low-voltage signal amplitude of 250 mV in the D-FF was adopted for both true-and-complementary and single-phase signals. Using a 70-GHz-f_T GaAs/AlGaAs HBT technology, the D-FF operated stably up to 18.6 Gb/s at designed bias voltages of 9 V with power dissipation of 0.55 W, and the prescaler operated up to 15.5 GHz with power dissipation of 1.5 W     

一种阴控速调管恒流灯丝电源的设计

阴控高功率速调管阴极工作在高压脉冲状态,灯丝电源悬浮在随阴极脉冲变化的电位上,开关稳压电源直接工作在阴极电位,极易受高压脉冲干扰无法工作。介绍了一种AC 220V输入低压端控制的恒流灯丝电源,具有抗干扰强、稳定度和可靠性高等特点。     

A low-voltage micropower JFET/bipolar operational amplifier

A single cell supply (operable down to 1.2 V) micropower operational amplifier using compatible low pinchoff voltage JFET's (V/SUB p/=0.4 V) in conjunction with standard bipolar technology has been developed. The subvolt pinchoff JFET's have proved useful in the common-mode feedback-assisted biasing of a simple p-n-p input stage to permit single supply operation, the design of a low-voltage high-performance current mirror and a differential to single-ended converter. The amplifier exhibits excellent ac performance (unity gain slew rate=0.25 V//spl mu/s, unity gain bandwidth=850 kHz) with low power dissipation (245 /spl mu/W).     

Circuit techniques for a 1.8-V-only NAND flash memory

Focusing on internal high-voltage (V_pp) switching and generation for low-voltage NAND flash memories, this paper describes a V _(pp) switch, row decoder, and charge-pump circuit. The proposed nMOS V_pp switch is composed of only intrinsic high-voltage transistors without channel implantation, which realizes both reduction of the minimum operating voltage and elimination of the V _pp leakage current. The proposed row decoder scheme is described in which all blocks are in selected state in standby so as to prevent standby current from flowing through the proposed V_pp switches in the row decoder. A merged charge-pump scheme generates a plurality of voltage levels with an individually optimized efficiency, which reduces circuit area in comparison with the conventional scheme that requires a separate charge-pump circuit for each voltage level. The proposed circuits were implemented on an experimental NAND flash memory. The charge pump and V_pp switch successfully operated at a supply voltage of 1.8 V with a standby current of 10 μA. The proposed pump scheme reduced the area required for charge-pump circuits by 40%     

Power Si-MOSFET operating with high efficiency under low supply voltage

A design method for RF power Si-MOSFETs suitable for low-voltage operation with high power-added efficiency is presented. In our experiments, supply voltages from 1 V to 3 V are examined. As the supply voltage is decreased, degradation of transconductance also takes place. However, this problem is overcome, even at extremely low supply voltages, by adopting a short gate length and also increasing the N/sup -/ extension impurity concentration-which determines the source-drain breakdown voltage (V/sub dss/)-and thinning the gate oxide-which determines the TDDB between gate and drain. Additionally, in order to reduce gate resistance, the Co-salicide process is adopted instead of metal gates. With salicide gates, a 0.2 /spl mu/m gate length is easily achieved by poly Si RIE etching, while if metal gates were chosen, the metal film itself would have to be etched by RIE and it would be difficult to achieve such a small gate length. Although the resistance of a Co-salicided gate is higher than that of metal gate, there is no evidence of a difference in power-added efficiency when the finger length is below 100 /spl mu/m. It is demonstrated that 0.2 /spl mu/m gate length Co-salicided Si MOSFETs can achieve a high power-added efficiency of more than 50% in 2 GHz RF operation with an adequate breakdown voltage (V/sub dss/). In particular, an efficiency of more than 50% was confirmed at the very low supply voltage of 1.0 V, as well as at higher supply voltages such as 2 V and 3 V. Small gate length Co-salicided Si-MOSFETs are a good candidate for low-voltage, high-efficiency RF power circuits operating in the 2 GHz range.     

High-voltage CMOS SIMOX technology and its application to a BSH-LSI

This paper describes high-voltage CMOS separation by implanted oxygen (SIMOX) technology and its application to a BSH-LSI that provides the basic functions of battery feed, supervision, and hybrid for subscriber line interface cuircuits. This technology is characterized by the existence of an electric-field-shielding (EFS) layer formed between the buried SiO2and the surface Si layer by oxygen implantation. The density of localized states at the Fermi level of the EFS layer has been estimated to be about 1 × 10¹⁹cm^-3. eV^-1using the Cohen-Fritzsche-Ovshinsky model. The EFS layer reduces substrate voltage dependence of the threshold voltage and increases the drain-to-source breakdown voltage for MOSFET's. Specifically, the drain-to-source breakdown voltage has been raised to 180 V. The BSH-LSI, which is composed of high-voltage CMOS of more than 60 V and low-voltage CMOS of 15 V, has been successfully fabricated containing resistors and capacitors. Compared with a conventional bipolar BSH-LSI, the chip size and the dissipation power of the LSI have been reduced to approximately one-third and one-half, respectively.     

5.7 GHz low-power variable-gain LNA in 0.18 /spl mu/m CMOS

A variable-gain low-noise amplifier (LNA) suitable for low-voltage and low-power operation is designed and implemented in a standard 0.18 /spl mu/m CMOS technology. With a current-reused topology, the common-source gain stages are stacked for minimum power dissipation while achieving high small-signal gain. The fully integrated 5.7 GHz LNA exhibits 16.4 dB gain, 3.5 dB noise figure and 8 dB gain tuning range with good input and output return losses. The LNA consumes 3.2 mW DC power from a supply voltage of 1 V. A gain/power quotient of 5.12 dB/mW is achieved in this work.