A low-noise, process-variation-tolerant double-gate FinFET based sense amplifier

In this paper, we propose a new independent-gate, process-variation-tolerant double-gate (DG) FinFET based sense amplifier design. The new design exploits the DICE (dual interlock cell) latch and the back gate of a double-gate FinFET (DG FinFET) device for dynamic compensation against process variation. The proposed design improves the sensing delay and show excellent tolerance to process variations as compared to independent-gate sense amplifier (IGSA). The primary advantage of the proposed amplifier over previously reported sense amplifier is the low-noise voltage and large critical charge, making it more stable against single event upsets. Failure probability of the proposed design against process parameter variations is analyzed through Monte Carlo analysis.     

Modeling and performance study of nanoscale double gate junctionless and inversion mode MOSFETs including carrier quantization effects

In this report we focus on the performance of nanoscale double gate (DG) junctionless (JL) and inversion mode (IM) MOSFETs. The study is performed using an analytical 2-D modeling approach from our previous work and an extension for the inclusion of carrier quantization effects (QEs). The model itself is physics-based, predictive and valid in all operating regimes. Important device metrics such as the drain-induced barrier lowering (DIBL), subthreshold slope (S  ) and the _Ion/_Ioff$I_{\mathit{on}}/I_{\mathit{off}}$ ratios are in focus and discussed. The model is compared versus 2-D numerical simulation results from TCAD Sentaurus. To stand the pace with recent ITRS requirements for future CMOS technology, we target devices with a minimum channel length of 16 nm and channel thicknesses down to 3 nm. The purpose of the research is to gain knowledge about the device?s performance at such aggressively scaled dimensions.     

A fuzzy-logic-based approach to accurate modeling of a double gate MOSFET for nanoelectronic circuit design

正The double gate(DG) silicon MOSFET with an extremely short-channel length has the appropriate features to constitute the devices for nanoscale circuit design.To develop a physical model for extremely scaled DG MOSFETs,the drain current in the channel must be accurately determined under the application of drain and gate voltages.However,modeling the transport mechanism forthe nanoscale structures requires the use of overkill methods and models in terms of their complexity and computation time(self-consistent,quantum computations,...). Therefore,new methods and techniques are required to overcome these constraints.In this paper,a new approach based on the fuzzy logic computation is proposed to investigate nanoscale DG MOSFETs.The proposed approach has been implemented in a device simulator to show the impact of the proposed approach on the nanoelectronic circuit design.The approach is general and thus is suitable for any type of nanoscale structure investigation problems in the nanotechnology industry.     

Two-dimensional quantum effects in nanoscale MOSFETs

In this paper, a full two-dimensional (2-D) quantum mechanical (QM) device simulator for deep submicron MOSFETs is presented. The model couples a 2-D Schrodinger-Poisson solver with a semiclassical transport model. The validity of the proposed model is first tested against a QM model for transport, developed as a benchmark. Then, QM effects on nanoscale MOSFETs performance are quantitatively addressed and discussed. It is shown that QM effects strongly influence the device performance, namely subthreshold slope drain-induced barrier lowering and short-channel effects. These results show that full QM simulations will become a mandatory issue for nanoscale MOSFETs modeling and design     

On the feasibility of nanoscale triple-gate CMOS transistors

The feasibility of triple-gate MOSFETs (TGFETs) for nanoscale CMOS applications is examined with regard to short-channel effects (SCEs) and gate-layout area. Three-dimensional numerical simulations of TGFETs reveal that much more stringent body scaling for SCE control is needed for undoped bodies relative to doped ones (which are not viable for nanoscale devices) due to the suppression of corner current conduction (which is technologically advantageous) in the former. When the undoped body is scaled for adequate SCE control, further analysis shows that the generic TGFET suffers from severe layout-area inefficiency relative to the fully depleted single-gate SOI MOSFET (FDFET) and the double-gate (DG) FinFET, and the inefficiency can be improved only by evolving the TGFET into a virtual FDFET or a virtual DG FinFET. We suggest then that the TGFET is not a feasible nanoscale CMOS transistor, and thus the DG FinFET, which is more scalable than the FDFET, seems to be the most promising candidate for future CMOS applications.     

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DG devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut–off frequency (f_T) and intrinsic voltage gain (A_VO). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate–underlap DG MOSFETs.     

A fuzzy-logic-based approach to accurate modeling of a double gate MOSFETfor nanoelectronic circuit design

The double gate (DG) silicon MOSFET with an extremely short-channel length has the appropriate features to constitute the devices for nanoscale circuit design. To develop a physical model for extremely scaled DG MOSFETs, the drain current in the channel must be accurately determined under the application of drain and gate voltages. However, modeling the transport mechanism for the nanoscale structures requires the use of overkill methods and models in terms of their complexity and computation time (self-consistent, quantum computations, ...). Therefore, new methods and techniques are required to overcome these constraints. In this paper, a new approach based on the fuzzy logic computation is proposed to investigate nanoscale DG MOSFETs. The proposed approach has been implemented in a device simulator to show the impact of the proposed approach on the nanoelectronic circuit design. The approach is general and thus is suitable for any type of nanoscale structure investigation problems in the nanotechnology industry.     

Short-Channel Effects in Independent-Gate FinFETs

A physics-based model is used to examine short-channel effects (SCEs) in undoped nanoscale independent-gate FinFETs, e.g., the MIGFET (L. Mathew, , Proc. IEEE Internat. SOI Conf., p. 187, 2004). Predicted current-voltage characteristics of MIGFETs in the single-gate mode show that the SCEs (threshold-voltage rolloff, subthreshold-swing degradation, and drain-induced barrier lowering) are actually less severe than those of the device in the double-gate mode. Insightful explanations of the results are given     

Investigation of the source/drain asymmetric effects due to gate misalignment in planar double-gate MOSFETs

A planar double-gate SOI MOSFET (DG-SOI) with thin channel and thick source/drain (S/D) was successfully fabricated. Using both experimental data and simulation results, the S/D asymmetric effect induced by gate misalignment was studied. For a misaligned DG-SOI, there is gate nonoverlapped region on one side and extra gate overlapped region on the other side. The nonoverlapped region introduces extra series resistance and weakly controlled channel, while the extra overlapped region introduces additional overlap capacitance and gate leakage current. We compared two cases: bottom gate shift to source side (DG/spl I.bar/S) and bottom gate shift to drain side (DG/spl I.bar/D). At the same gate misalignment value, DG/spl I.bar/S resulted in a larger drain-induced barrier lowering effect and smaller overlap capacitance at drain side than DG/spl I.bar/D. Because of reduced drain-side capacitance, the speed of three-stage ring oscillator of DG/spl I.bar/S, with 20% gate misalignment length (L/sub mis/) over gate length (L/sub g/), or L/sub mis//L/sub g/=20%, was faster than that of two-gate aligned DG-SOI.     

Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops

An energy recovery or resonant clocking scheme is very attractive for saving the clock power in nanoscale ASICs and systems-on-chips, which have increased functionality and die sizes. The technology scaling followed Moore’s law, that lowers node capacitance and supply voltage, making nanoscale integrated circuits more vulnerable to radiation-induced single event upsets (SEUs) or soft errors. In this work, we propose soft-error robust flip-flops (FFs) capable of working with a sinusoidal resonant clock to save the overall chip power. The proposed conditional-pass Quatro (CPQ) FF and true single phase clock energy recovery (TSPCER) FF are based on a unique soft error robust latch, which we refer to as a Quatro latch. The proposed C²-DICE FF is based on a dual interlocked cell (DICE) latch. In addition to the storage cell, each FF consists of a unique input-stage and a two-transistor, two-input output buffer. In each FF with a sinusoidal clock, the transfer unit passes the data to the Quatro and DICE latches. The latches store the data values at two storage nodes and two redundant nodes, the latter enabling recovery from a particle-induced transient with or without multiple-node charge sharing. Post-layout simulations in 65nm CMOS technology show that the FF exhibits as much as 82% lower power-delay product compared to recently reported soft error robust FFs. We implemented 1024 proposed FFs distributed in an H-tree clock network driven by a resonant clock-generator that generates a 1–5 GHz sinusoidal clock signal. The simulation results show a power reduction of 93% on the clock tree and total power saving of up to 74% as compared to the same implementation using the conventional square-wave clocking scheme and FFs.     

Two-Dimensional Analytical Threshold Voltage and Subthreshold Swing Models of Undoped Symmetric Double-Gate MOSFETs

We have developed analytical physically based models for the threshold voltage [including the drain-induced barrier lowering (DIBL) effect] and the subthreshold swing of undoped symmetrical double-gate (DG) MOSFETs. The models are derived from an analytical solution of the 2-D Poisson equation in which the electron concentration was included. The models for DIBL, subthreshold swing, and threshold voltage roll-off have been verified by comparison with 2-D numerical simulations for different values of channel length, channel thickness, and drain-source voltage; very good agreement with the numerical simulations has been observed     

ANFIS-based approach to studying subthreshold behavior including the traps effect for nanoscale thin-film DG MOSFETs

A fuzzy framework based on an adaptive network fuzzy inference system(ANFIS) is proposed to evaluate the relative degradation of the basic subthreshold parameters due to hot-carrier effects for nanoscale thin-film double-gate(DG) MOSFETs.The effect of the channel length and thickness on the resulting degradation is addressed, and 2-D numerical simulations are used for the elaboration of the training database.Several membership function shapes are developed,and the best one in terms of accuracy is selected.The predicted results agree well with the 2-D numerical simulations and can be efficiently used to investigate the impact of the interface fixed charges and quantum confinement on nanoscale DG MOSFET subthreshold behavior.Therefore,the proposed ANFIS-based approach offers a simple and accurate technique to study nanoscale devices,including the hot-carrier and quantum effects.     

Off-state current and performance analysis for double-gate CMOS with non-self-aligned back gate

Numerical simulation-based study of double-gate (DG) field-effect transistors (FETs) leads to the possibly viable concept of extremely scaled but nonself-aligned DG CMOS. Predictions of off-state current, on-state current, and circuit performance, accounting for short-channel effects and energy-quantization effects, in 25-nm DG FETs suggest that moderate back-gate underlap does not severely undermine the superior performance and leakage current of nanoscale DG CMOS relative to those of bulk-Si CMOS. The reverse back-gate biasing scheme for leakage reduction in DG CMOS is shown to be much more efficient than the reverse body biasing scheme in bulk Si even with moderate back-gate underlap.     

Modeling and Significance of Fringe Capacitance in Nonclassical CMOS Devices With Gate–Source/Drain Underlap

Parasitic gate–source/drain (G–S/D) fringe capacitance in nonclassical nanoscale CMOS devices, e.g., double-gate (DG) MOSFETs, is shown, using two-dimensional numerical simulations, to be very significant, gate bias-dependent, and substantially reduced by a well-designed G–S/D underlap. Analytical modeling of the outer and inner components of the fringe capacitance is developed and verified by the numerical simulations; a BOX-fringe component is modeled for single-gate fully depleted silicon-on-insulator MOSFETs. With the new modeling implemented in UFDG, our process/physics-based generic compact model for DG MOSFETs, UFDG/Spice3 shows how nanoscale DG CMOS speed is severely affected by the fringe capacitance and how this effect can be moderated by an optimal underlap, which yields a good tradeoff between the parasitic capacitance and the S/D resistance.     

Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs

A simple analytical expression of the 2-D potential distribution along the channel of silicon symmetrical double-gate (DG) MOSFETs in weak inversion is derived. The analytical solution of the potential distribution is compared with the numerical solution of the 2-D Poisson's equation in terms of the channel length L, the silicon thickness t _Si, and the gate oxide thickness t _OX. The obtained results show that the analytical solution describes, with good accuracy, the potential distribution along the channel at different positions from the gate interfaces for well-designed devices when the ratio of L/t _Si is ges 2-3. Based on the 2-D extra potential induced in the silicon film due to short-channel effects (SCEs), a semi-analytical expression for the subthreshold drain current of short-channel devices is derived. From the obtained subthreshold characteristics, the extracted device parameters of the subthreshold slope, drain-induced barrier lowering, and threshold voltage are discussed. Application of the proposed model to devices with silicon replaced by germanium demonstrates that the germanium DG MOSFETs are more prone to SCEs.     

Full quantum simulation study of a nano tri-material double gate silicon-on-insulator MOSFET

We present 2D full quantum simulation based on the self-consistent solution of 2D Poisson–Schrödinger equations, within the nonequilibrium Green’s function formalism, for a novel multiple region silicon-on-insulator (SOI) MOSFET device architecture – tri-material double gate (TMDG) SOI MOSFET. This new structure has three materials with different work functions in the front gate, which show reduced short-channel effects such as the drain-induced barrier lowering and subthreshold swing, because of a step function of the potential in the channel region that ensures the screening of the drain potential variation by the gate near the drain. Also, the quantum simulations show the new structure significantly decreases leakage current and drain conductance and increases on–off current ratio and voltage gain as compared to conventional and dual material DG SOI MOSFET.     

A four-interleaving HBD SRAM cell based on dual DICE for multiple node collection mitigation

A 4-interleaving cell of 2-dual interlocked cells (DICE) is proposed, which reduces single event induced multiple node collection between the sensitive nodes of sensitive pairs in a DICE storage cell in 65 nm technology. The technique involves the 4-interleaving of dual DICE cells at a layout level to meet the required spacing between sensitive nodes in an area-efficient manner. Radiation experiments using a 65 nm CMOS test chip demonstrate that the LETth of our 4-interleaving cell of dual DICE encounters are almost 4× larger and the SEU cross section per bit for our proposed dual DICE design is almost two orders of magnitude less compared to the reference traditional DICE cell.     

Self-aligned vertical double-gate MOSFET (VDGM) with the oblique rotating ion implantation (ORI) method

A process of making a symmetrical self-aligned n-type vertical double-gate MOSFET (n-VDGM) over a silicon pillar is revealed. This process utilizes the technique of oblique rotating ion implantation (ORI). The self-aligned region forms a sharp vertical channel profile and decreases the channel length L_g. A tremendous improvement in the drive-on current is noted. The electron concentration profile obtained demonstrates an increased number of electrons in the channel injected from the source end as the drain voltage increases. The enhanced carrier concentration results in significant reduction in the off-state leakage current and improves the drain-induced barrier-lowering (DIBL) effect. These simulated characteristics when compared to those in a fabricated device without the ORI method show the distinct advantage of the technique reported for suppression of short-channel effects (SCE) in nanoscale vertical MOSFET.     

A physical compact model of DG MOSFET for mixed-signal circuit applications- part I: model description

To use double-gate (DG) MOSFET for mixed-signal circuit applications, especially for circuits in which the two gates are independently driven, such as in the case of dynamic-threshold and fixed-potential-plane operations, physical compact models that are valid for all modes of operations are necessary for accurate design and analysis. Employing physically rigorous current-voltage (I-V) relationship in subthreshold and above-threshold regions as asymptotic cases, we have constructed a model that joins the two operating regions by using carrier-screening functions. We have included consistently source/drain series resistance, low drain-field mobility, and small-geometry effects of drain-induced barrier lowering (DIBL), MOS interface mobility, velocity saturation and channel-length modulation (CLM) with validation from two-dimensional (2-D) distributed simulation. All model parameters can be extracted from large-signal I-V characteristics in dc conditions with given geometrical data. Parameter extraction methods and verification from simulation are presented in Part II.     

Improved performance of nanoscale junctionless transistor based on gate engineering approach

In this paper, we propose an effective method to improve the electrical characteristics of dual-material-gate (DMG) junctionless transistor (JLT) based on gate engineering approach, with the example of n-type double gate (DG) JLT with total channel length down to 30 nm. The characteristics are demonstrated and compared with conventional DMG DGJLT and single-material gate (SMG) DGJLT. The results show that the novel DMG DGJLT presents superior subthreshold swing (SS), drain-induced barrier lowering (DIBL), transconductance (G_m), ON/OFF current ratio, and intrinsic delay (τ). Moreover, these unique features can be controlled by engineering the length and workfunction of the gate material. In addition, the sensitivities of the novel DMG device with respect to structural parameters are investigated.