A CMOS gate array architecture for digital signal processingapplications

A new CMOS gate array architecture for digital signal processing (DSP) is presented. The basic cell structure takes into account the high degree of regularity of DSP datapaths. Therefore, it supports in particular the implementation of systolic arrays in connection with a pipelining scheme of one addition per half clock cycle. Together with a new gate array approach (macrocell design style), macrocells can be implemented efficiently on the new architecture. All DSP macrocells use dynamic transmission gate latches. Furthermore, the routing is done exclusively by cell abutment which results in short intercell routing. The macrocell design style is compared with the conventional gate array approach. In the common gate array approach, conventional gate array architectures are used together with conventional design equipment and layout strategies. The comparison shows a reduction in area and power consumption by a factor of 2.5 and 3.7, respectively. The efficiency increases by a factor of at least nine. These results were proved by analog circuit simulations and test chip measurements     

A BiCMOS continuous-time filter for video signal processingapplications

A fully integrated BiCMOS continuous-time filter for video signal processing applications is presented. It incorporates an input clamping circuit, a third-order equalizer, a fifth-order elliptic filter with sinx/x correction, and a 75-Ω driver. The architectures of the input and output amplifiers as well as the filter and the equalizer are chosen based on the extensive study of circuit structures and Monte Carlo simulation to meet the linearity requirement for the broadcast-quality video system. The complete chip achieves a low-pass filter response with a 5.5-MHz cutoff frequency (f_cc), 0.3-dB passband ripple, 20-ns group delay variation up to 0.9 f_c, and 43-dB attenuation at 1.45 f_c. With a nominal 2-Vpp signal at the output, measured results show 0.2% differential gain, 0.38° differential phase, and 1.7-mV rms noise demonstrating 10-bit linearity in a 1.5-μm 4-GHz BiCMOS process technology. The filter active area is 8 mm² and it dissipates 350 mW in a single 5-V power supply     

Vlsi programmable digital filter for video signal processing

High speed digital filtering is required in real time video signal processing, as well as high order filters are needed to match television studio signal quality. The hardware complexity involved by such system constraints may be faced by a two-fold approach, concerning both the architecture and the technological aspects of a specific electronics device devoted to the above task.This article deals with a processor especially developed for the purpose of fast digital video signal applications, such as filtering, equalization, interpolation and so on. The nonrecursive transposed F.I.R. (Finite Impulse Response) structure has been selected, which exhibits a linear phase behavior. A novel approach has been developed for the multipliers implementation, by optimizing an EPROM based look-up table storing the products between all video samples and the filter coefficients significant bits, resulting in a programmable system.TheProgrammable Filter Processor has been designed with a high level of parallelism and pipelining and a 1.2 µm CMOS EPROM, single metal technology has been employed for the integration process of the chip. This has been successfully production-tested for 40 Msamples/s throughput rate, thus both allowing to meet most video filtering applications and demonstrating the potentialities of nonvolatile memory technologies in embedded applications.Moreover multiple devices can be interconnected to yield multiprocessor structures for more demanding performances such as, cascaded or longer filters, input signal precision extension, computation improved accuracy, increased throughput rate, and two-dimensional signal processing.Work carried out in the framework of the agreement between the Italian P.T. Administration and the Fondazione UGO BORDONI.     

An 85-MHz fourth-order programmable IIR digital filter chip

The authors describe the design and VLSI implementation of a single-chip 85-MHz fourth-order infinite impulse response (IIR) digital filter chip fabricated in 0.9-μm CMOS technology. The coefficient and input data word lengths of the filter are 10 b each, and the output data word length is 15 b. The coefficients are fully programmable. The chip can be programmed to implement any IIR filter from first to fourth order or an FIR filter up to 16th order at sample rates up to 85 MHz. A total of seventeen 10×10 multiply-add modules are used in this chip. The chip contains 80000 devices in an active area of 14 mm². It dissipates 2.2 W at 85-MHz clock rate and performs over 1.5×10⁹ multiply-add operations per second. The underlying filtering algorithm, chip architecture, circuit and layout design, speed issues, and test results are described. The results of an E-beam probing experiment on packaged chips at 100-MHz clock rates are also presented and discussed     

A 40 MHz multi applicable digital signal processing chip

A multi applicable building block capable of performing several typical signal processing (sub) operations such as addition, multiplication, multiplexing, etc. is discussed. The chip, made in 4 /spl mu/m E/D NMOS technology with implanted undercrossings, runs at clock frequencies up to 40 MHz, which is particularly suited for digital video signal processing.     

A programmable analog neural network chip

A generic chip is implemented in CMOS to facilitate studying networks by building them in analog VLSI. By utilizing the well-known properties of charge storage and charge injection in a novel way, the authors have achieved a high enough level of complexity (>10³ weights and 10 bits of analog depth) to be interesting, in spite of the limitation of a modest 6.00×3.5-mm² die size required by a multiproject fabrication run. If the cell were optimized to represent fixed-weight networks by eliminating weight decay and bidirectional weight changes, the density could easily be increased by a factor of 2 with no loss in resolution. Once a weight change vector has been written to the RAM cells, charge transfers can be clocked at a rate of 2 MHz, corresponding to peak learning rates of 2×10⁹ weight changes/second and exceeding the throughput of `neural network accelerators' by two orders of magnitude     

A programmable focal-plane MIMD image processor chip

An 80×78 pixels vision chip for focal-plane image processing is presented. The chip employs a Multiple-Instruction-Multiple-Data (MIMD) architecture to provide five spatially processed images in parallel. The size, configuration, and coefficients of the spatial kernels are programmable. The chip's architecture allows the photoreceptor cells to be small and parked densely by performing all computations on the read-out, away from the array. The processing core uses digitally programmed current-mode analog computation. Operating at 9.6 K frames/s in 800-lux ambient light, the chip consumes 4 mW from a 2.5-V power supply. Performing 11×11 spatial convolutions, an equivalent computation (5.5 bit scale-accumulate) rate of 12.4 GOPS/mW is achieved using 22 mm² in a 1.2-μm CMOS process. The application of the chip to line-segment orientation detection is also presented     

A configurable convolution chip with programmable coefficients

Describes the architecture and implementation of a bit-level configurable convolver array. The systolic field supports a configuration during operation in terms of number of taps and coefficient word length. A chip has been designed in 1.5- mu m CMOS using a full-custom design style which contains 112586 transistors on an active area of 46 mm/sup 2/. The configurability consumes only 9% of that area. The prototypes are shown to be fully functional up to 20 MHz. An extension of the architecture for optimized calculation of transformations is also presented.<>     

A CCD programmable signal processor

A generic large-coupled device (CCD) signal processor that performs 2.8-billion computations per second with a 10-MHz clock rate is described. The device's concept, design, operation, performance, and applications are reviewed. A dynamic range greater than 42 dB has been demonstrated by the device. This processor can be used as a one-dimensional correlator, a two-dimensional matched filter or a two-layer neural net device. The device demonstrates the flexibility and computational power that is possible using CCD technology     

用于实时目标检测的高速可编程视觉芯片

视觉芯片是一种高速、低功耗的智能视觉处理系统芯片,在生产生活中有广阔的应用前景。文中提出了一种新型的可编程视觉芯片架构,该架构的设计考虑了传统计算机视觉算法和卷积神经网络的运算特点,使其能够同时高效地支持这两类算法。该视觉芯片集成了可编程的多层次并行处理阵列、高速数据传输通路和系统控制模块,并采用65 nm标准CMOS工艺制程流片。测试结果表明:视觉芯片在200 MHz系统时钟下达到413GOPS的峰值运算性能,能够高效地完成包括完成人脸识别、目标检测等多种计算机视觉和人工智能算法。该视觉芯片在可编程度、运算性能以及能耗效率等方面都大大超越了其他视觉芯片。     

A new semi-flat architecture for high speed and reduced area CORDIC chip

In this contribution we present a new CORDIC architecture called ‘semi-flat’ which reduces considerably the latency time and the amount of hardware. In our semi-flat architecture the first rotations are executed with an unfolded scheme but the remaining iterations are flattened using a fast redundant addition tree. Detailed comparisons with other major contributions show that our semi-flat redundant CORDIC is 30% faster and occupy 39% less silicon area.     

控制激光的可编程脉冲信号发生器

用可编程脉冲信号发生器控制激光脉冲的频率、脉宽和功率,使激光脉冲在微机控制下可组成各种激光脉冲序列。     

A programmable floating-point cell for systolic signal processing

The FPC controller and the AMD Am29325 32-bit floating-point mathematics processor form a two-chip cell designed for one- or two-dimensional systolic arrays which can be used to implement a wide variety of signal processing applications. The FPC controls the Am29325, routes data to and from it, and routes data and control to other cells in the array. Unique architectural features include two interchangeable data memories, an input port which can be used as either a local or global port, and a 32-bit instruction word that allows concurrent use of all cell resources. Additional features include a program memory, two data streams, and three control streams.     

A high speed programmable focal-plane SIMD vision chip

A high speed analog VLSI image acquisition and low-level image processing system is presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Each pixel include a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A 64 × 64 pixel proof-of-concept chip was fabricated in a 0.35 μm standard CMOS process, with a pixel size of 35 μm × 35 μm. The chip can capture raw images up to 10,000 fps and runs low-level image processing at a framerate of 2,000–5,000 fps.     

On the digital signal processor based programmable real-time reed-solomon coding-decoding system

A real-time high-speed Reed-Solomon coding—decoding system has been built based on a low-cost signal processor TMS 32010. By taking advantage of the TMS 320 16-bit multiplier and barrel shifter, the evaluation of the sum-of-products expression over a prime field can be simplified. Decoding of a (256,228) code with powerful error correcting capability over GF(257) has been implemented in this system, and the information bit rate is at least twice that of the ISDN B-channel basic rate.     

真正的单芯片可编程SOC

可编程的SOC:两芯片系统与真正单 芯片系统 系统级集成仍然是半导体产业中的 标题新闻。正在进行的工作把几乎是全 部的系统功能集成到单个硅片上。片上 系统（SOC）可以提供更好的性能、更低 的功耗、更小的印制板空间,以及更低的 成本,因而受到人们的青睐。片上系统传 统上一直是用掩模ASIC去实现。但是, ASIC的不可重用的工程费用达到每次设 计25万美元或更多,最低订购量大,设 计周期长。因此,只适合在批量大、能够 承受得起这种成本的项目上使用。 几家IC厂商已经推出一种新的混合 型SOC器件,即可编程片上系统。它们     

基于CORDIC算法的数字下变频

采用CORDIC算法设计实现数字下变频（DDC）。该设计方法克服了传统的数控振荡器（NCO）查找表（LUT）大的缺点,且该算法模块同时实现数控振荡器和混频器的功能,省去了2个硬件乘法器。这种方法能够有效地提高信号处理效率,减小硬件实现的代价,通过仿真证明了该方法的有效性和高效性。最终实现的下变频模块可以工作在200MHz的系统时钟之下,占用FPGA资源约9％。     

可编程信号处理器的低功耗设计

可编程信号处理器已获得广泛应用，随着VLSI技术的发展，现在已可利用信号处理器实现SOC功能，实现SOC功能还必须降低处理器的功耗。本文首先叙述可编程信号处理器降低功耗的各种途径，然后介绍低功耗可编程处理器的结构设计，最后对最新的TMS320C55X的低功耗性能进行分析。     

A programmable analog cellular neural network CMOS chip for highspeed image processing

A high speed analog image processor chip is presented. It is based on the cellular neural network architecture. The implementation of an analog programmable CNN-chip in a standard CMOS technology is discussed. The control parameters or templates in all cells are under direct user control and are tunable over a continuous value range from 1/4 to 4. This tuning property is implemented with a compact current scaling circuit based on MOS transistors operating in the linear region. A 4×4 CNN prototype system has been designed in a 2.4 μm CMOS technology and successfully tested. The cell density is 380 cells/cm² and the cell time constant is 10 μs. The current drain for a typical template is 40 μA/cell. The real-time image processing capabilities of the system are demonstrated. From this prototype it is estimated that a 128×128 fully programmable analog image processing system can be integrated on a single chip using a standard digital submicron CMOS technology. This work demonstrates that powerful high speed programmable analog processing systems can be built using standard CMOS technologies