A two-dimensional quasi-optical power combining oscillator array with external injection locking

A quasi-optical power combiner for a 4/spl times/4 IMPATT oscillator array has been designed and experimentally investigated. The combiner consists of a bi-periodic dielectric phase grating which transforms the near field of a rectangular horn array into a pseudoplane wave. The horn array is excited by oscillators which operate uniformly in both amplitude and phase. A parabolic mirror with a superimposed surface relief couples the pseudoplane wave into a rectangular output horn antenna. In principle, the combiner has no restriction in inter-element spacing and is hence scalable up to submillimeter wavelengths without degradation of power combining efficiency. The quasi-optical design has been verified by scalar field measurements in several planes. The oscillator matrix is injection-locked by a master oscillator from the output port. A continuous wave output power of 1.3 W with an overall power combining efficiency of 70% has been measured at 65 GHz.     

一种Ka波段三路波导功率分配/合成器的设计

提出了一种波导三路功分器结构,该功分器采用E面T型缝隙耦合结构来实现功分比的调节。通过调节耦合缝隙以及感性膜片,使输入阻抗匹配并且实现等功率同相位的三路功分输出。为了实现功率合成,采用对称的两个三路功分器进行背靠背级联实现功率合成网络,仿真结果显示出良好的驻波效果和极低的插损。最终对加工出的实物进行测量,在32.5~36 GHz频段内实现了输出功率幅度不平衡度小于0.5 dB的良好效果。通过背靠背连接两个功分器实现了在33.3~35.3 GHz带宽内插损小于0.3 dB的功率分配/合成网络。     

Quasi-optical 150-GHz power combining oscillator

A quasi-optical power combiner for a five-element in-line oscillator array is experimentally investigated at 150 GHz. The combiner consists of a periodic dielectric phase grating (hologram) which transforms the near-field of a rectangular horn antenna array into a pseudo-plane wave. The horn array is excited by IMPATT oscillators operating uniformly in both amplitude and phase. A dual offset reflector set-up transforms the pseudo-plane wave to a Gaussian beam which matches the field pattern of a dual mode receiving antenna. Even though an inter-element spacing of 9.5 /spl lambda/ has been chosen, the passive structure gives a power combining efficiency of 74.1%. The power combining oscillator has been operated in both free-running and injection-locked mode. A CW output power of 78.0 mW and 83.5 mW was measured for the free-running and injection-locked oscillator, respectively, which is corresponding to a power combining efficiency of 66.5% and 71.2%, respectively.     

Wide-Band Phase Locking and Phase Shifting Using Feedback Control of Oscillators (Short Papers)

Two Yig-tuned Gunn oscillators/sup 1/ have been frequency locked over a 3-GHz range in X-band. Injected power into the locked oscillator was approximately 10 dB below its output power. Analog frequency-tracking circuitry was used together with phase-comparator feedback to achieve output phase which remained within /spl plus mn/10/spl deg/ over a 1.2 GHz bandwidth. Controlled phase shifting was obtained by applying dc voltages within the feedback loop.     

Combining the Powers from Multiple-Device Oscillators

This paper describes the results of power combining with multiple-device oscillators. A combiner circuit consisting of 3 oscillators and a directional coupler is analyzed. Conditions are set to obtain the maximum combining efficiency and a key approach is developed to control the frequency of the combiner. It is shown that the performance of the system is not seriously affected by the dissimilarity of the oscillators used in the combiner. A prototype 84-diode power combiner is constructed and total output power of 1.72 W with combining efficiency of 98.3 percent is obtained at 9.7 GHz. No fundamental limiting factor for the maximum number of devices to be combined was found.     

Hybrid combiner design for downlink massive MIMO systems

We consider a hybrid combiner design for downlink massive multiple‐input multiple‐output systems when there is residual inter‐user interference and each user is equipped with a limited number of radio frequency (RF) chains (less than the number of receive antennas). We propose a hybrid combiner that minimizes the mean‐squared error (MSE) between the information symbols and the ones estimated with a constant amplitude constraint on the RF combiner. In the proposed scheme, an iterative alternating optimization method is utilized. At each iteration, one of the analog RF and digital baseband combining matrices is updated to minimize the MSE by fixing the other matrix without considering the constant amplitude constraint. Then, the other matrix is updated by changing the roles of the two matrices. Each element in the RF combining matrix is obtained from the phase component of the solution matrix of the optimization problem for the RF combining matrix. Simulation results show that the proposed scheme performs better than conventional matrix‐decomposition schemes.     

Sub-THz Four-Way Waveguide Power Combiner With Low Insertion Loss

A four-way waveguide power divider has been developed in sub-THz band. The waveguide power divider was achieved with the improved H-plane T-junction structure. By tuning the depth and width at the junction of the waveguide, the input impendence was matched and the two-way output power amplitude and phase were at the same level. The four-way power divider was realized by the concatenation of two same T-junction at the two output ports. A sub-THz four-way passive power combiner is designed, fabricated and measured. The measure results show that the measured insertion loss of the fabricated four-way passive power combiner is less than 1.2 dB whereas the input return loss is greater than 14.8 dB from 97.5 to 101.7 GHz. Experiments on the sub-THz four-way passive power combiner show that a minimum insertion loss of 1 dB has been achieved at about 99.5 GHz. The measured minimum insertion loss of the waveguide power divider is half of the insertion loss for the entire passive power combiner (0.5 dB), which corresponds to a power-combining efficiency of 89 %. The measured results agree with the simulated ones closely.     

50W Ka频段固态功率放大器设计

阐述了3 dB分支波导定向耦合器、波导—微带双探针过渡、改进型波导T型结的原理,介绍了一种4路功率分配/合成网络。提出了一种8路功率分配/合成器,其结构具有插入损耗低、输入驻波好、幅度相位一致性好等优点。研制了50 W Ka频段固态功率放大器,由驱动级放大器、8路功率分配/合成器和8个7 W功放模块组成,在29~31 GHz频率范围内实现了大于50 W的线性输出功率,合成效率高于80%。     

Load Dependence of Gunn-Oscillator Performance

A detailed analysis of an experimental resonator as a basis for determining the output power and the tuning range of Gunn oscillators as functions of the fundamental resonant-load resistance. Differing n/sub 0/L products (1.2 and 4.8x10/sup 12/ cm/sup -2/) lead to strikingly different results which are related to the delayed-and quenched-domain resonant modes, respectively. Variations of the second-harmonic frequency termination cause the fundamental output power of Gunn oscillators to change by a factor of up to 5, this change being accompanied by a frequency pulling of a few percent. From detailed impedance measurements it is concluded that the maximum fundamental power occurs if the second-harmonic circuit is tuned near an open-circuit resonance, the total circuit susceptance being somewhat capacitive.     

A single-chip CMOS transceiver for 802.11a/b/g wireless LANs

A dual-band trimode radio fully compliant with the IEEE 802.11a, b, and g standards is implemented in a 0.18-/spl mu/m CMOS process and packaged in a 48-pin QFN package. The transceiver achieves a receiver noise figure of 4.9/5.6 dB for the 2.4-GHz/5-GHz bands, respectively, and a transmit error vector magnitude (EVM) of 2.5% for both bands. The transmit output power is digitally controlled, allowing per-packet power control as required by the forthcoming 802.11 h standard. A quadrature accuracy of 0.3/spl deg/ in phase and 0.05 dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a total integrated phase noise of better than -34 dBc. Compatibility with multiple baseband chips is ensured by flexible interfaces toward the A/D and D/A converters, as well as a calibration scheme not requiring any baseband support. The chip passes /spl plusmn/2 kV human body model ESD testing on all pins, including the RF pins. The total die area is 12 mm/sup 2/. The power consumption is 207 mW in the receive mode and 247 mW in the transmit mode using a 1.8-V supply.     

Millimeter-wave-band amplifier and mixer MMICs using a broad-band45° power divider/combiner

This paper demonstrates millimeter-wave-band amplifier and mixer monolithic microwave integrated circuits (MMIC's) using a broad-band 45° power divider/combiner. At first, we propose a broad-band 45° power divider/combiner, which combines a Wilkinson divider/combiner, 45° delay line, and 90° short stub. A coupling loss of 4.0±0.2 dB and a return loss and an isolation of more than 19 dB with 45±1° phase difference was obtained from 17 to 22 GHz for the fabricated K-band MMIC 45° power divider/combiner. Next, a parallel amplifier using the broad-band 45° power divider/combiner, which can be used in a power-combining circuit configuration requiring no isolator, is shown. Comparing the transmitter intermodulation generated in the parallel amplifier using the broad-band 45° power divider/combiner and that generated in the one using the conventional type, the broad-band suppression effect was confirmed. Finally, an application of the broad-band 45° power divider/combiner to a single-sideband (SSB) subharmonically pumped (SHP) mixer requiring no IF switch is shown. In an RF frequency range from 22.89 to 26.39 GHz, the fabricated K-band MMIC mixer achieved (for up-conversion) the good results of more than -13-dB conversion gain and more than 24-dB image-rejection ratio. These contribute significantly to the miniaturization of millimeter-wave communication equipment     

An analytical formulation of phase noise of signals with Gaussian-distributed jitter

The output of many oscillatory systems can be approximated by a stochastic square-wave signal with noise-free amplitude and Gaussian-distributed jitter. We present an analytical treatment of the phase noise of this signal with white and Lorentzian jitter spectra. With a white jitter spectrum, the phase noise is nearly Lorentzian around each harmonic. With a Lorentzian jitter spectrum, it is a sum of several Lorentzian spectra, a summation that has a 1/f/sup 4/ shape at far-out frequencies. With a combination of the two, it has 1/f/sup 4/ and 1/f/sup 2/ shapes at close-in and far-out frequencies, respectively. In all cases, the phase noise at the center frequency and the total signal power are both finite. These findings will improve our understanding of phase noise and will facilitate the calculation of phase noise using time- domain jitter analysis.     

Corporate and Tandem Structures for Combining Power from 3/sup N/ and 2N+ 1 Oscillators

The output power from three Gunn oscillators was combined using a short-slot coupler in conjunction with high-level injection locking with the power combining efficiency of ahout 100 percent at 9.7 GHz. Using the 3-oscillator structure as the building block, we constructed (3/sup 2/ = )9-oscillator corporate structure and (2X4+1=)9- and (2X6+1 = )13-oscillator tandem structures to demonstrate power combining efficiencies of 92, 95, and 93 percent, respectively, at 9.6 GHz.     

Ka波段三路波导功分器/合路器

文章设计了一种可以使用在固态合成发射机上的三路等分功率波导功分器/合路器。在波导分支定向耦合器的基础上,增加一路副线波导,构成了一个一路输入、一路直通、两路耦合、两路隔离的六端口网络;采用增加波导长度的方式解决了实际应用中的相位补偿问题。另外在功分器的三路输出端增加了微带部分以提高功分器的可调试性。实际测量数据基本符合仿真结果:在1GHz带宽内,功分器的一路插损小于6dB,输入驻波小于1.6;合路器的一路插损小于4.9dB,输出驻波小于1.3。其性能满足使用要求。文章最后对该类型的波导功分器/合路器的设计提出若干改进方案。     

A 10-gb/s CMOS clock and data recovery circuit with an analog phase interpolator

This paper presents a 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel applications. The module aligns the phase of a plesiochronous system clock to the incoming data by use of phase interpolation. Thus, coupling between voltage-controlled oscillators (VCOs) in adjacent channels can be avoided. The controller for the phase interpolator is realized with analog circuitry to overcome the speed and phase resolution limitations of digital implementations. Fabricated in a 0.11-/spl mu/m CMOS technology the module has a size of 0.25/spl times/1.4 mm/sup 2/. The power consumption is 220 mW from a supply voltage of 1.5 V. The CDR exceeds the SDH/SONET jitter tolerance specifications with a pseudo random bit sequence of length 2/sup 23/-1 and a bit-error rate threshold of 10/sup -12/. The re-timed and demultiplexed data has an rms jitter of 3.2 ps at a data rate of 2.7 Gb/s.     

A 4-Gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-/spl mu/m standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 2/sup 31/-1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10/sup -6/ for 2/sup 31/-1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply.     

A Self-Aliglned 1-/spl mu/m-Channel CMOS Technology with Retrograde n-Well and Thin Epitaxy

A six-mask 1-/spl mu/m CMOS process with many self-aligned features is described. It uses a thin p-type epitaxial layer on a p/sup +/ substrate and a retrograde n-well. Self-aligned TiSi/sub 2/ is formed on n/sup +/ and p/sup +/ diffusions to reduce the sheet resistance and to make butted source contacts. It is shown that n/sup +/ poly-gated p-channel devices can be properly designed with low threshold magnitudes and good turn-off characteristics. With a 5-V supply, the minimum gate delay of unloaded CMOS ring oscillators is 150 ps/stage. Furthermore, it is dernonstrated that this CMOS technology is Iatchup free since the holding voltage for Iatchup is higher than 5 V.     

10?30 GHz monolithic GaAs travelling-wave divider/combiner

A four-way monolithic GaAs travelling-wave power divider/combiner has been designed, fabricated and evaluated. With a design centre frequency of 20 GHz, a bandwidth of from 10 GHz to 30 GHz has been measured. The insertion loss per dividing or combining action is less than 0.5 dB, with isolation between ports no worse than 20 dB. The input/output VSWRs are better than 2:1 across the same band. This divider/combiner can readily be used with monolithic GaAs power FET amplifiers to produce a several-fold increase in output powers over the 10 to 30 GHz frequency range.     

Design of a 16 way radial microwave power divider/combiner with rectangular waveguide output and coaxial inputs

In this paper, design of a radial power combiner at microwave frequencies has been presented. This structure combines 16 coaxial inputs together and creates one rectangular waveguide output of type WR-187. Although complexity of the proposed combiner compared to combiners with coaxial output has increased, its return loss and VSWR have been improved. In order to achieve a good matching in its high frequency response, a fast tune technique has been applied to design procedure. In its design, a rectangular waveguide has been used together with its radial structure but symmetry among its ports and its phase and amplitude deviations have remained at standard values. Also, in its design, in order to avoid corona breakdown strength of electric field has been controlled and reduced.     

A Mach-Zehnder-interferometer-based low-loss combiner

Passive optical combiners have an unwanted 3-dB loss. This is avoided with optical switches, but these need control functions to synchronize with the optical signals. A nonlinear Mach-Zehnder interferometer can provide the combiner function without control signals. In the experiment reported here, this combiner was realized with a fiber component. Semiconductor optical amplifiers (SOAs) acted as the nonlinear phase shifting elements. Thus a proof-of-principle for the self-routing combiner is obtained: optical signals on either of the two input ports are guided to one and the same output port without any control mechanism in the interferometer. The nonlinear effect used is self-phase modulation, caused by carrier depletion in the SOAs as they approach saturation. The optical power at which the nonlinear switching occurred was about -2 dBm. The residual combiner loss was only 0.7 dB