A 0.25-μm CMOS 0.9-V 100-MHz DSP core

This paper describes a 0.25-μm CMOS 0.9-V 100-MHz DSP core which is composed of a 2-mW 16-b multiplier-accumulator and a 1.5-mW 8-kb SRAM. High-speed operation with a supply of less than 1 V has been achieved by developing 0.25-μm CMOS technology, reducing threshold voltage to 0.3 V, developing tristate inverter 3-2/4-2 adders for the multiplier, realizing small bit-line swing operation for the SRAM, and so on. The adder circuits operate faster than conventional adders at low supply voltages. In addition, short-circuit current and area for diffusion contact are reduced. Small bit-line swing operation has been realized by using a device-deviation immune sense amplifier. Leakage current during sleep mode was reduced by the use of high threshold voltage MOSFETs     

Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM

Circuit techniques for battery-operated DRAMs which cover supply voltages from 1.5 to 3.6 V (universal V_cc), as well as their applications to an experimental 64-Mb DRAM, are presented. The universal-V_cc DRAM concept features a low-voltage (1.5 V) DRAM core and an on-chip power supply unit optimized for the operation of the DRAM. A circuit technique for oxide-stress relaxation is proposed to improve high-voltage sustaining characteristics while only scaled MOSFETs are used in the entire chip. This technique increases sustaining voltage by about 1.5 V compared with conventional circuits and allows scaled MOSFETs to be used for the circuits, which can be operated from an external V_cc of up to 4 V. A two-way power supply scheme is proposed to suppress the internal voltage fluctuation within 10% when the DRAM is operated from external power supply voltages ranging from 1.5 to 3.6 V. An experimental 1.5-3.6-V 64-Mb DRAM is designed based on these techniques and fabricated by using 0.3-μm electron-beam lithography. An almost constant access time of 70 ns is obtained. This indicates that battery operation is a promising target for future DRAMs     

A 0.5-μm, 3-V 1T1C, 1-Mbit FRAM with a variable referencebit-line voltage scheme using a fatigue-free reference capacitor

A 0.5-μm, 3-V operated, 1TIC, 1-Mbit FRAM with 160-ns access time has been developed. In FRAM, a reference voltage design using a ferroelectric capacitor is difficult because of the degradation due to fatigue, a chip-to-chip variation, and a temperature dependence. A variable reference voltage scheme is generated to solve this problem, boosting a fatigue-free and temperature-independent MOS reference capacitance by a driver. The driver is operated from a compact reference voltage generator that provides 32 equally divided voltages and occupies only half the layout area of a conventional one. During sense operation, memory-cell capacitance C_ferr is larger than reference-cell capacitance C_MOS. A double word-line pulse scheme has also been developed to eliminate a bit-line capacitance imbalance in the bit-line pairs, where a memory cell and a reference cell are separated from the bit-line pairs during sense operation. A six-order improvement in imprint lifetime has been achieved by the new scheme     

A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme

Multithreshold-voltage CMOS (MTCMOS) technology has a great advantage in that it provides high-speed operation with low supply voltages of less than 1 V. A logic gate with low-V/sub th/ MOSFETs has a high operating speed, while a low-leakage power switch with a high-V/sub th/ MOSFET eliminates the off-leakage current during sleep time. By using MTCMOS circuits and silicon-on-insulator (SOI) devices, the authors have developed a 256-kb SRAM for solar-power-operated digital equipment. A double-threshold-voltage MOSFET (DTMOS) is adopted for the power switch to further reduce the off leakage. As regards the SRAM core design, we consider a hybrid configuration consisting of high-V/sub th/ and low-V/sub th/ MOSFETs (that is, multi-V/sub th/ CMOS). A new memory cell with a separate read-data path provides a larger readout current without degrading the static noise margin. A negatively overdriven bitline scheme guarantees sure write operation at ultralow supply voltages close to 0.5 V. In addition, a charge-transfer amplifier integrated with a selector and data latches for intrabus circuitry are installed to enhance the operating speed and/or reduce power dissipation. A 32K-word /spl times/ 8-bit SRAM chip, fabricated with the 0.35-/spl mu/m multi-V/sub th/ CMOS/SOI process, has successfully operated at 25 MHz under typical conditions with 0.5-V (SRAM core) and 1-V (I/O buffers) power supplies. The power dissipation during sleep time is less than 0.4 /spl mu/W and that for 25-MHz operation is 1 mW, excluding that of the I/O buffers.     

1.5 V resistive fuse for image smoothing and segmentation

A 1.5 V resistive fuse for image smoothing and segmentation using bulk-driven MOSFETs is presented. The circuit switches on only if the differential voltage applied across its input terminals is less than a set voltage; it switches off if the differential voltage is higher than the set value. The useful operation range of the circuit is 0.4 V with a supply voltage of 1.5 V and threshold voltages of V_Tn=0.828 V and V_Tp=-0.56 V for n and p channel MOSFETs, respectively     

A boosted negative bit-line SRAM with write-assisted cell in 45 nm CMOS technology

A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage.In this technique,a negative bit-line voltage is applied to one of the write bit-lines,while a boosted voltage is applied to the other write bit-line where transmission gate access is used in proposed 11 T cell.Supply voltage to one of the inverters is interrupted to weaken the feedback.Improved write feature is attributed to strengthened write access devices and weakened feedback loop of cell at the same time.Amount of boosting required for write performance improvement is also reduced due to feedback weakening,solving the persistent problem of half-selected cells and reliability reduction of access devices with the other suggested boosted and negative bit-line techniques.The proposed design improves write time by 79％,63％ and slower by 52％ with respect to LP 10 T,WRE 8 T and 6 Tcells respectively.It is found that write margin for the proposed cell is improved by about 4×,2.4× and 5.37× compared to WRE8 T,LP10 T and 6 T respectively.The proposed cell with boosted negative bit line (BNBL) provides 47％,31％,and 68.4％ improvement in write margin with respect to no write-assist,negative bit line (NBL) and boosted bit line (BBL) write-assist respectively.Also,new sensing circuit with replica bit-line is proposed to give a more precise timing of applying boosted voltages for improved results.All simulations are done on TSMC 45 nm CMOS technology.     

A 25-ns 1-Mbit CMOS SRAM with loading-free bit lines

A 128 K/spl times/8-b CMOS SRAM is described which achieves a 25-ns access time, less than 40-mA active current at 10 MHz, and 2-/spl mu/A standby current. The novel bit-line circuitry (loading-free bit line), using two kinds of NMOSFETs with different threshold voltages, improves bit-line signal speed and integrity. The two-stage local amplification technique minimizes the data-line delay. The dynamic double-word-line scheme (DDWL) allows the cell array to be divided into 32 sections along the word-line direction without a huge increase in chip area. This allows the DDWL scheme to reduce the core-area delay time and operating power to about half that of other conventional structures. A double-metal 0.8-/spl mu/m twin-tub CMOS technology has been developed to realize the 5.6/spl times/9.5-/spl mu//SUP 2/ cell size and the 6.86/spl times/15.37-mm/SUP 2/ chip size.     

Power Si-MOSFET operating with high efficiency under low supply voltage

A design method for RF power Si-MOSFETs suitable for low-voltage operation with high power-added efficiency is presented. In our experiments, supply voltages from 1 V to 3 V are examined. As the supply voltage is decreased, degradation of transconductance also takes place. However, this problem is overcome, even at extremely low supply voltages, by adopting a short gate length and also increasing the N/sup -/ extension impurity concentration-which determines the source-drain breakdown voltage (V/sub dss/)-and thinning the gate oxide-which determines the TDDB between gate and drain. Additionally, in order to reduce gate resistance, the Co-salicide process is adopted instead of metal gates. With salicide gates, a 0.2 /spl mu/m gate length is easily achieved by poly Si RIE etching, while if metal gates were chosen, the metal film itself would have to be etched by RIE and it would be difficult to achieve such a small gate length. Although the resistance of a Co-salicided gate is higher than that of metal gate, there is no evidence of a difference in power-added efficiency when the finger length is below 100 /spl mu/m. It is demonstrated that 0.2 /spl mu/m gate length Co-salicided Si MOSFETs can achieve a high power-added efficiency of more than 50% in 2 GHz RF operation with an adequate breakdown voltage (V/sub dss/). In particular, an efficiency of more than 50% was confirmed at the very low supply voltage of 1.0 V, as well as at higher supply voltages such as 2 V and 3 V. Small gate length Co-salicided Si-MOSFETs are a good candidate for low-voltage, high-efficiency RF power circuits operating in the 2 GHz range.     

A 100 ns 5 V only 64K/spl times/1 MOS dynamic RAM

A new high performance 36500 mil/SUP 2/ 64K dynamic RAM has been designed and incorporates: 1) a twisted-metal bit-line architecture, 2) an ultrasensitive sense amplifier with self-restore to V/SUB DD/, 3) internal constant-voltage supply to memory cell plate, 4) a bit-line equalizer and full-size reference capacitor, 5) high-performance enhancement-depletion mode inverter-buffer circuits, 6) TTL negative undershoot protection on address circuits, and 7) active hold-down transistors for both X and Y drivers. A nominal 100 ns access time and power dissipation of less than 150 mW was observed during active operation with a 20 mW power dissipation in the standby mode.     

A high-density dual-port memory cell operation and arrayarchitecture for ULSI DRAMs

A high-density dual-port DRAM architecture is proposed. It realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual-port (TDP) DRAM, adopts the previously proposed divided/shared bit-line (DSB) sensing scheme in a dual-port 2Tr-1C DRAM array. A 2Tr-1C dual-port memory cell array with folded bit-line sensing operation, which does not increase the number of bit lines of the 1Tr-1C folded bit-line memory array, is realized, thus reducing the memory cell size. This architecture offers a solution to the fundamental limitations in the 2Tr-1C dual-port memory cell, and it is easily applicable to dual-port memory cores in ASIC environments. An analysis of the memory array noise in various dual-port architectures shows a significant improvement with this architecture. Applications to the complete pipelining operation of a DRAM array and a refresh-free DRAM core are also discussed     

X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs

In an SRAM circuit, the leakage currents on the bit lines are getting increasingly prominent with the dwindling of transistors' threshold voltages as the technology scales down to 90 nm and beyond. Excessive bit-line leakage current results in slower read operations or even functional failure. In this paper, we present a new technique, called X-calibration, to combat this phenomenon. Unlike the previous method that attempts to compensate the leakage current directly, this scheme first transforms the bit-line leakage current into an equilibrium offset voltage across the bit-line pair, and then simple circuitry is utilized to cancel this offset accurately at the input of the sense amplifier so that the sensing is not affected by the bit-line leakage. SPICE simulation of a 1 Kbit SRAM macro shows that this X-calibration scheme can handle 83% higher bit-line leakage current than the previous bit-line leakage compensation scheme. Measurement results of the test chip show that the SRAM macro adopting X-calibration scheme can cope with up to 320 $mu{hbox{A}}$ bit-line leakage current.      

A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS

This paper presents a new very low-power, low-voltage successive approximation analog to digital converter (SAR ADC) design based on supply boosting technique. The supply boosting technique (SBT) and supply boosted (SB) circuits including level shifter, comparator, and supporting electronics are described. Supply boosting provides wide input common mode range and sub-1 Volt operation for the circuits designed in standard CMOS processes that have only high-V_t MOSFETs. A 10-bit supply boosted SAR ADC was designed and fabricated in a standard 0.5 μm, 5 V, 2P3M, CMOS process in which threshold voltages of NMOS and PMOS devices are +0.8 and −0.9 V, respectively. Fabricated SB-SAR ADC achieves effective number of bits (ENOB) of 8.04, power consumption of 147 nW with sampling rate of 1.0 KS/s on 1 Volt supply. Measured figure of merit (FOM) was 280 fJ/conversion-step. Proposed supply boosting technique improves input common mode range of both SB comparator and SAR ADC, allows sub-1 Volt operation when threshold voltages are in the order of the supply voltage, and achieves low energy operation. Thus, SBT is suitable for mixed-signal circuit designed for energy limited applications and systems in where supply voltage is in the order of threshold voltages of the process.     

A divided/shared bit-line sensing scheme for ULSI DRAM cores

A new dynamic RAM (DRAM) signal sensing principle, a divided/shared bit-line (DSB) sensing scheme, is proposed. This sensing scheme provides folded bit-line sensing operation in a crosspoint-type memory cell array. The DSB scheme offers a high-density DRAM memory core with the common-mode array noise eliminated. A bit-line architecture based on this new sensing principle and its operation are demonstrated. A divided/pausing bit-line sensing (DIPS) scheme, which is an application of this DSB principle to the conventional folded bit-line type of memory cell arrangement, is also proposed. The DIPS architecture achieves complete pausing states for alternate bit lines throughout the active period. These alternate pausing bit lines shield the inter-bit-line coupling noise between active bit lines. Here the inter-bit-line coupling noise is eliminated by a slight architectural change to the conventional folded bit-line memory cell array. These new memory core design alternatives provide high-density DRAM memory cores suitable for the 64-Mb level and beyond. with the memory array noise reduced significantly     

A 16-Mb CMOS SRAM with a 2.3-μm2 single-bit-linememory cell

A novel architecture that enables fast write/read in poly-PMOS load or high-resistance polyload single-bit-line cells is developed. The architecture for write uses alternate twin word activation (ATWA) with bit-line pulsing. A dummy cell is used to obtain a reference voltage for reading. An excellent balance between a normal cell signal line and a dummy cell signal line is attained using balanced common data-line architecture. A newly developed self-bias-control (SBC) sense amplifier provides excellent stability and fast sensing performance for input voltages close to V_CC at a low power supply of 2.5 V. The single-bit-line architecture is incorporated in a 16-Mb SRAM, which was fabricated using 0.25-μm CMOS technology. The proposed single-bit-line architecture reduces the cell area to 2.3-μm² , which is two-thirds of a conventional two-bit-line cell with the same processes. The 16-Mb SRAM, a test chip for a 64-Mb SRAM, shows a 15-ns address access time and a 20-ns cycle time     

A high-speed sensing scheme for 1T dynamic RAMs utilizing theclamped bit-line sense amplifier

A clamped-bit-line sense amplifier (CBLSA) capable of very high-speed operation in one-transistor (1T) DRAM applications has been developed. Results from an experimental test chip demonstrate that the speed of the new circuit is insensitive to bit-line capacitance. Circuit speed is also found to be insensitive to the initial bit-line difference voltage. The CBLSA maintains a low impedance fixed potential on the bit lines during sensing, virtually eliminating sensitivity to inter-bit-line noise coupling and minimizing power supply bounce during sensing. The new sense amplifier operates at higher speeds than conventional circuits and still dissipates less power     

An experimental 4 Mb flash EEPROM with sector erase

A 512K×8 flash EEPROM (electrically erasable programmable ROM) which operates from a single 5-V supply was designed and fabricated. A double-poly, single-metal CMOS process with a minimum feature size of 0.9 μm was developed to manufacture the test vehicle, which resulted in a die size of 95 mm². The storage cell is 8.64 μm² and consists of a one-transistor cell that uses a remote, scalable, tunnel diode for programming and erasing by Fowler-Nordheim tunneling. Process high-voltage requirements are relaxed by utilizing circuit techniques to alleviate the burden of high voltages. A segmented architecture provides the flexibility to erase any one sector (16 kB) or the entire chip during one cycle by an erase algorithm. The memory can be programmed one byte at a time, or the internal bit-line latches can be used to program a 256-B page in one cycle. A programming time of 10 ms is typical, which results in a write time of 40 μs/B during page programming. The chip features an access time of 90 ns     

High-speed, high-reliability circuit design for megabit DRAM

Circuit techniques for improving the speed and reliability of submicrometer geometry CMOS DRAMs are described. Double-bootstrap voltages are eliminated with an internal voltage supply and a unique word-line driver, reducing stress on short-channel devices. A row and column redundancy technique equivalent to physical disconnect of word lines and bit lines solves leakage problems. Speed enhancements are achieved through bit-line isolation for accelerated column access, a high-speed SRAM-style data path, and by tailoring sensing currents within the limitations of package inductance. The design of a fast 1-Mb DRAM employing these circuits is outlined     

Memory characteristics of MOSFETs with densely stacked silicon nanocrystal Layers in the gate oxide synthesized by low-energy ion beam

Densely stacked silicon nanocrystal layers embedded in the gate oxide of MOSFETs are synthesized with Si ion implantation into an SiO/sub 2/ layer at an implantation energy of 2 keV. In this letter, the memory characteristics of MOSFETs with 7-nm tunnel oxide and 20-nm control oxide at various temperatures have been investigated. A threshold voltage window of /spl sim/ 0.5 V is achieved under write/erase (W/E) voltages of +12 V/-12 V for 1 ms. The devices exhibit good endurance up to 10/sup 5/ W/E cycles even at a high operation temperature of 150/spl deg/C. They also have good retention characteristics with an extrapolated ten-year memory window of /spl sim/ 0.3 V at 100/spl deg/C.     

High-speed sensing scheme for CMOS DRAMs

A significant improvement in sensing speed over the half-V_DD bit-line precharge sensing scheme is obtained by precharging the bit line to approximately 2/3 V_DD. The 2/3-V_DD sensing scheme also results in higher-bit-line capacitance, asymmetrical bit-line swing, and higher power consumption. However, the speed advantage of 2/3-V_DD sensing may outweigh the disadvantages and can significantly improve DRAM performance. For the unboosted word-line case, symmetrical bit-line swing can be retained by limiting the bit-line downward voltage swing through a clamping circuit added to the sense amplifier, resulting in almost no loss of stored charge in a cell. The authors show that the 2/3-V_DD sensing with a limited bit-line swing has several distinct advantages over the half-V_DD sensing scheme and is particularly suitable for high-performance high density CMOS DRAMs     

A 0.5-V 1-/spl mu/W successive approximation ADC

A successive approximation analog-to-digital converter (ADC) is presented operating at ultralow supply voltages. The circuit is realized in a 0.18-/spl mu/m standard CMOS technology. Neither low-V/sub T/ devices nor voltage boosting techniques are used. All voltage levels are between supply voltage V/sub DD/ and ground V/sub SS/. A passive sample-and-hold stage and a capacitor-based digital-to-analog converter are used to avoid application of operational amplifiers, since opamp operation requires higher values for the lowest possible supply voltage. The ADC has signal-to-noise-and-distortion ratios of 51.2 and 43.3 dB for supply voltages of 1 and 0.5 V, at sampling rates of 150 and 4.1 kS/s and power consumptions of 30 and 0.85 /spl mu/W, respectively. Proper operation is achieved down to a supply voltage of 0.4 V.