State-of-the-art graphene high-frequency electronics

High-performance graphene transistors for radio frequency applications have received much attention and significant progress has been achieved. However, devices based on large-area synthetic graphene, which have direct technological relevance, are still typically outperformed by those based on mechanically exfoliated graphene. Here, we report devices with intrinsic cutoff frequency above 300 GHz, based on both wafer-scale CVD grown graphene and epitaxial graphene on SiC, thus surpassing previous records on any graphene material. We also demonstrate devices with optimized architecture exhibiting voltage and power gains reaching 20 dB and a wafer-scale integrated graphene amplifier circuit with voltage amplification.     

Graphene epitaxy by chemical vapor deposition on SiC

We demonstrate the growth of high quality graphene layers by chemical vapor deposition (CVD) on insulating and conductive SiC substrates. This method provides key advantages over the well-developed epitaxial graphene growth by Si sublimation that has been known for decades. (1) CVD growth is much less sensitive to SiC surface defects resulting in high electron mobilities of ～1800 cm(2)/(V s) and enables the controlled synthesis of a determined number of graphene layers with a defined doping level. The high quality of graphene is evidenced by a unique combination of angle-resolved photoemission spectroscopy, Raman spectroscopy, transport measurements, scanning tunneling microscopy and ellipsometry. Our measurements indicate that CVD grown graphene is under less compressive strain than its epitaxial counterpart and confirms the existence of an electronic energy band gap. These features are essential for future applications of graphene electronics based on wafer scale graphene growth.     

Improvement of carrier mobility of top-gated SiC epitaxial graphene transistors using a PVA dielectric buffer layer

The effects of treatment with polyvinyl alcohol (PVA) and a dielectric film of HfO(2) on the properties of SiC based epitaxial graphene have been explored and analyzed. We have characterized the carrier mobility of graphene on Si-face and C-face SiC with a layer of HfO(2), with or without an initial PVA treatment on the device active layer. Epitaxial graphene grown on the C-face displays a higher mobility than a film grown on the silicon face. Also, the mobility in the presence of the PVA treatment with HfO(2) dielectric layer has been improved, compared with the mobility after deposition of only gate dielectric: ～20% in C-face graphene and ～90% in Si-face graphene. This is a major improvement over the degradation normally observed with dielectric/graphene systems.     

Bilayer graphene grown on 4H-SiC (0001) step-free mesas

We demonstrate the first successful growth of large-area (200 × 200 μm(2)) bilayer, Bernal stacked, epitaxial graphene (EG) on atomically flat, 4H-SiC (0001) step-free mesas (SFMs) . The use of SFMs for the growth of graphene resulted in the complete elimination of surface step-bunching typically found after EG growth on conventional nominally on-axis SiC (0001) substrates. As a result heights of EG surface features are reduced by at least a factor of 50 from the heights found on conventional substrates. Evaluation of the EG across the SFM using the Raman 2D mode indicates Bernal stacking with low and uniform compressive lattice strain of only 0.05%. The uniformity of this strain is significantly improved, which is about 13-fold decrease of strain found for EG grown on conventional nominally on-axis substrates. The magnitude of the strain approaches values for stress-free exfoliated graphene flakes. Hall transport measurements on large area bilayer samples taken as a function of temperature from 4.3 to 300 K revealed an n-type carrier mobility that increased from 1170 to 1730 cm(2) V(-1) s(-1), and a corresponding sheet carrier density that decreased from 5.0 × 10(12) cm(-2) to 3.26 × 10(12) cm(-2). The transport is believed to occur predominantly through the top EG layer with the bottom layer screening the top layer from the substrate. These results demonstrate that EG synthesized on large area, perfectly flat on-axis mesa surfaces can be used to produce Bernal-stacked bilayer EG having excellent uniformity and reduced strain and provides the perfect opportunity for significant advancement of epitaxial graphene electronics technology.     

Elucidating the electronic and magnetic properties of epitaxial graphene grown on SiC with a defective buffer layer

Journal of Materials Science - The epitaxial graphene layer (EG) grown on silicon carbide (SiC) is severely affected by the presence of the underlying graphene buffer layer (BL). However, little...     

Modulating the Surface State of SiC to Control Carrier Transport in Graphene/SiC

Silicon carbide (SiC) with epitaxial graphene (EG/SiC) shows a great potential in the applications of electronic and photoelectric devices. The performance of devices is primarily dependent on the interfacial heterojunction between graphene and SiC. Here, the band structure of the EG/SiC heterojunction is experimentally investigated by Kelvin probe force microscopy. The dependence of the barrier height at the EG/SiC heterojunction to the initial surface state of SiC is revealed. Both the barrier height and band bending tendency of the heterojunction can be modulated by controlling the surface state of SiC, leading to the tuned carrier transport behavior at the EG/SiC interface. The barrier height at the EG/SiC(000‐1) interface is almost ten times that of the EG/SiC(0001) interface. As a result, the amount of carrier transport at the EG/SiC(000‐1) interface is about ten times that of the EG/SiC(0001) interface. These results offer insights into the carrier transport behavior at the EG/SiC heterojunction by controlling the initial surface state of SiC, and this strategy can be extended in all devices with graphene as the top layer.     

The influence of high dielectric constant aluminum oxide sputter deposition on the structure and properties of multilayer epitaxial graphene

High dielectric constant aluminum oxide (Al(2)O(3)) is frequently used as the gate oxide in high electron mobility transistors and the impact of its deposition by radio frequency (RF) magnetron sputtering on the structural and electrical properties of multilayer epitaxial graphene (MLG) grown by graphitization of silicon carbide (SiC) is reported. Micro-Raman spectroscopy and temperature dependent Hall mobility measurements reveal that the processing induced changes to the structural and electrical properties of the MLG can be minimal when the oxide deposition conditions are optimal. High-resolution transmission electron microscopy (HRTEM) analysis confirms that the Al(2)O(3)/MLG interface is relatively sharp and that our thickness approximation of the MLG using angle resolved x-ray photoelectron spectroscopy (ARXPS) is accurate. An interface trap density of 5.1 × 10(10) eV(-1) cm(-2) was determined using capacitance-voltage techniques. The totality of our results indicates that ARXPS can be used as a nondestructive tool to measure the thickness of MLG, and that RF sputtered Al(2)O(3) can be used as a high dielectric (high-k) constant gate oxide in multilayer graphene based transistor applications.     

Josephson Coupling in Junctions Made of Monolayer Graphene Grown on SiC

Chemical vapor deposition has proved to be successful in producing graphene samples on silicon carbide (SiC) homogeneous at the centimeter scale in terms of Hall conductance quantization. Here, we report on the realization of co-planar diffusive Al/ monolayer graphene/ Al junctions on the same graphene sheet, with separations between the electrodes down to 200 nm. Robust Josephson coupling has been measured for separations not larger than 300 nm. Transport properties are reproducible on different junctions and indicate that graphene on SiC substrates is a concrete candidate to provide scalability of hybrid Josephson graphene/superconductor devices.     

Chemical vapor deposition-derived graphene with electrical performance of exfoliated graphene

While chemical vapor deposition (CVD) promises a scalable method to produce large-area graphene, CVD-grown graphene has heretofore exhibited inferior electronic properties in comparison with exfoliated samples. Here we test the electrical transport properties of CVD-grown graphene in which two important sources of disorder, namely grain boundaries and processing-induced contamination, are substantially reduced. We grow CVD graphene with grain sizes up to 250 μm to abate grain boundaries, and we transfer graphene utilizing a novel, dry-transfer method to minimize chemical contamination. We fabricate devices on both silicon dioxide and hexagonal boron nitride (h-BN) dielectrics to probe the effects of substrate-induced disorder. On both substrate types, the large-grain CVD graphene samples are comparable in quality to the best reported exfoliated samples, as determined by low-temperature electrical transport and magnetotransport measurements. Small-grain samples exhibit much greater variation in quality and inferior performance by multiple measures, even in samples exhibiting high field-effect mobility. These results confirm the possibility of achieving high-performance graphene devices based on a scalable synthesis process.     

Atomic-scale transport in epitaxial graphene

The high carrier mobility of graphene is key to its applications, and understanding the factors that limit mobility is essential for future devices. Yet, despite significant progress, mobilities in excess of the 2×10(5) cm(2) V(-1) s(-1) demonstrated in free-standing graphene films have not been duplicated in conventional graphene devices fabricated on substrates. Understanding the origins of this degradation is perhaps the main challenge facing graphene device research. Experiments that probe carrier scattering in devices are often indirect, relying on the predictions of a specific model for scattering, such as random charged impurities in the substrate. Here, we describe model-independent, atomic-scale transport measurements that show that scattering at two key defects--surface steps and changes in layer thickness--seriously degrades transport in epitaxial graphene films on SiC. These measurements demonstrate the strong impact of atomic-scale substrate features on graphene performance.     

Formation of bilayer bernal graphene: layer-by-layer epitaxy via chemical vapor deposition

We report the epitaxial formation of bilayer Bernal graphene on copper foil via chemical vapor deposition. The self-limit effect of graphene growth on copper is broken through the introduction of a second growth process. The coverage of bilayer regions with Bernal stacking can be as high as 67% before further optimization. Facilitated with the transfer process to silicon/silicon oxide substrates, dual-gated graphene transistors of the as-grown bilayer Bernal graphene were fabricated, showing typical tunable transfer characteristics under varying gate voltages. The high-yield layer-by-layer epitaxy scheme will not only make this material easily accessible but reveal the fundamental mechanism of graphene growth on copper.     

Graphene on cubic-SiC

The outstanding properties of graphene make it a top candidate for replacing silicon in future electronic devices. However, for technological applications, graphene must be synthesized on the surface of wide-gap semiconductors. In this review, we focus on graphene synthesized on single-crystalline cubic-SiC thin films epitaxially grown on standard silicon wafers. These low-cost substrates are commercially available and fully compatible with existing silicon technologies. The results obtained in recent years demonstrate that few-layer graphene synthesized on cubic-SiC substrates possesses the atomic structure and electronic properties of quasi-free-standing graphene. However, according to data obtained by various techniques, few-layer graphene on cubic-SiC consists of nanodomains connected to one another through nanodomain boundaries. After optimization of the preparation procedures, such a nanostructured graphene overlayer can represent a very promising system for the development of new graphene-based electronic devices. In particular, recent works demonstrate that continuous few-layer graphene with self-aligned nanodomain boundaries can be synthesized on vicinal SiC(0 0 1) substrates. Electrical measurements show the opening of a transport gap in nanostructured trilayer graphene synthesized on SiC/2°-off Si(0 0 1) wafers. This development may lead to new tunable electronic nanostructures made from graphene on cubic-SiC, opening up opportunities for a wide range of applications.     

Quality assessment of graphene: Continuity,uniformity, and accuracy of mobility measurements

With the increasing availability of large-area graphene,the ability to rapidly and accurately assess the quality of the electrical properties has become critically important.For practical applications,spatial variability in carrier density and carrier mobility must be controlled and minimized.We present a simple framework for assessing the quality and homogeneity of large-area graphene devices.The field effect in both exfoliated graphene devices encapsulated in hexagonal boron nitride and chemical vapor-deposited (CVD) devices was measured in dual current-voltage configurations and used to derive a single,gate-dependent effective shape factor,β,for each device.β is a sensitive indicator of spatial homogeneity that can be obtained from samples of arbitrary shape.All 50 devices investigated in this study show a variation (up to tenfold) inβ as a function of the gate bias.Finite element simulations suggest that spatial doping inhomogeneity,rather than mobility inhomogeneity,is the primary cause of the gate dependence ofβ,and that measurable variations ofβ can be caused by doping variations as small as 1010 cm-2.Our results suggest that local variations in the position of the Dirac point alter the current flow and thus the effective sample shape as a function of the gate bias.We also found that such variations lead to systematic errors in carrier mobility calculations,which can be revealed by inspecting the correspondingβ factor.     

Simultaneous N-intercalation and N-doping of epitaxial graphene on 6H-SiC(0001) through thermal reactions with ammonia

Surface functionalization of epitaxial graphene overlayers on 6H-SiC(0001) has been attempted through thermal reactions in NH₃. X-ray photoelectron spectroscopy and micro-region low energy electron diffraction results show that a significant amount of N is present at the NH₃-treated graphene surface, which results in strong band bending at the SiC surface as well as decoupling of the graphene overlayers from the substrate. The majority of the surface N species can be removed by annealing in vacuum up to 850 °C, weakening the surface band bending and resuming the strong coupling of graphene with the SiC surface. The desorbed N atoms can be attributed to the intercalated species between graphene and SiC. Low temperature scanning tunneling spectroscopy and density functional theory simulations confirm the presence of N dopants in the graphene lattice, which are in the form of graphitic substitution and can be stable above 850 °C. This is the first report of simultaneous N intercalation and N doping of epitaxial graphene overlayers on SiC, and it may be employed to alter the surface physical and chemical properties of epitaxial graphene overlayers.      

Long spin relaxation times in wafer scale epitaxial graphene on SiC(0001)

We developed an easy, upscalable process to prepare lateral spin-valve devices on epitaxially grown monolayer graphene on SiC(0001) and perform nonlocal spin transport measurements. We observe the longest spin relaxation times τ(S) in monolayer graphene, while the spin diffusion coefficient D(S) is strongly reduced compared to typical results on exfoliated graphene. The increase of τ(S) is probably related to the changed substrate, while the cause for the small value of D(S) remains an open question.     

Electron-microscopic investigation of a SiC/Si(111) structure obtained by solid phase epitaxy

First results of the electron-microscopic investigation of thin silicon carbide (SiC) layers grown on silicon using a new method of solid phase epitaxy are presented. It is shown that, at the initial stage of epitaxial growth, a transition layer is formed which consists of various SiC polytypes. This layer occurs at the interface between the substrate and a single-crystalline SiC layer possessing predominantly a 3C polytype structure. It is established that pores with dimensions ranging from a fraction of micron to several dozen nanometers are formed in a near-surface layer of the silicon substrate, which favor the growth of epitaxial, weakly strained single-crystalline SiC layers.     

Raman spectroscopy and imaging of graphene

Graphene has many unique properties that make it an ideal material for fundamental studies as well as for potential applications. Here we review recent results on the Raman spectroscopy and imaging of graphene. We show that Raman spectroscopy and imaging can be used as a quick and unambiguous method to determine the number of graphene layers. The strong Raman signal of single layer graphene compared to graphite is explained by an interference enhancement model. We have also studied the effect of substrates, the top layer deposition, the annealing process, as well as folding (stacking order) on the physical and electronic properties of graphene. Finally, Raman spectroscopy of epitaxial graphene grown on a SiC substrate is presented and strong compressive strain on epitaxial graphene is observed. The results presented here are highly relevant to the application of graphene in nano-electronic devices and help in developing a better understanding of the physical and electronic properties of graphene. This article is published with open access at Springerlink.com     

Vapour-phase graphene epitaxy at low temperatures

We report an epitaxial growth of graphene, including homo- and hetero-epitaxy on graphite and SiC substrates, at a temperature as low as ∼540 °C. This vapour-phase epitaxial growth, carried out in a remote plasma-enhanced chemical vapor deposition (RPECVD) system using methane as the carbon source, can yield large-area high-quality graphene with the desired number of layers over the entire substrate surfaces following an AB-stacking layer-by-layer growth model. We also developed a facile transfer method to transfer a typical continuous one layer epitaxial graphene with second layer graphene islands on top of the first layer with the coverage of the second layer graphene islands being 20% (1.2 layer epitaxial graphene) from a SiC substrate onto SiO₂ and measured the resistivity, carrier density and mobility. Our work provides a new strategy toward the growth of graphene and broadens its prospects of application in future electronics.      

Ballistic transport of graphene pnp junctions with embedded local gates

We fabricated graphene pnp devices, by embedding pre-defined local gates in an oxidized surface layer of a silicon substrate. With neither deposition of dielectric material on the graphene nor electron-beam irradiation, we obtained high-quality graphene pnp devices without degradation of the carrier mobility even in the local-gate region. The corresponding increased mean free path leads to the observation of ballistic and phase-coherent transport across a local gate 130 nm wide, which is about an order of magnitude wider than reported previously. Furthermore, in our scheme, we demonstrated independent control of the carrier density in the local-gate region, with a conductance map very much distinct from those of top-gated devices. This was caused by the electric field arising from the global back gate being strongly screened by the embedded local gate. Our scheme allows the realization of ideal multipolar graphene junctions with ballistic carrier transport.     

High-Performance Twin Silicon Nanowire MOSFET (TSNWFET) on Bulk Si Wafer

A gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 5-nm-radius channels on a bulk Si wafer is successfully fabricated to achieve extremely high-drive currents of 2.37 mA/ mum for n-channel and 1.30 mA/ mum for p-channel TSNWFETs with mid-gap TiN metal gate that are normalized by a nanowire diameter. It also shows good short-channel effects immunity down to 30-nm gate length due to the GAA structure and the nanowire channel. The effect of bottom parasitic transistor in TSNWFET is also investigated.