On‐Chip Debug Architecture for Multicore Processor

Because of the intrinsic lack of internal‐system observability and controllability in highly integrated multicore processors, very restricted access is allowed for the debugging of erroneous chip behavior. Therefore, the building of an efficient debug function is an important consideration in the design of multicore processors. In this paper, we propose a flexible on‐chip debug architecture that embeds a special logic supporting the debug functionality in the multicore processor. It is designed to support run‐stop‐type debug functions that can halt and control the execution of the multicore processor at breakpoint events and inspect the possible causes of any errors. The debug architecture consists of the following three functional components: the core debug support block, the multicore debug support block, and the debug interface and control block. By embedding this debug infrastructure, the embedded processor cores within the multicore processor can be debugged simultaneously as well as independently. The debug control is performed by employing a JTAG‐based scanning operation. We apply this on‐chip debug architecture to build a debugger for a prototype multicore processor and demonstrate the validity and scalability of our approach.     

基于NoC的多核SoC片上调试构架

为解决基于NoC的多核SoC调试问题,提出一个片上硬件调试构架.详细分析了该构架的重要组成部分,调试代理及调试探测器.通过仿真验证了片上调试构架的功能,并针对逻辑综合的结果讨论了实现该调试构架的面积开销.     

基于OCP通信事务的SOC调试控制器

基于OCP通信事务进行SOC调试,提高了调试的抽象级别,对于以通信为核心的多核SOC,可以大大提高调试效率.为实现事务级调试,提出基于OCP通信事务的可配置调试控制器.通过分析OCP通信事务,该控制器根据预先配置的触发条件产生本地和远端调试控制信息,从而控制调试过程.通过对实验设计的仿真和综合,验证了调试控制器的功能,并分析了设计的面积开销.     

Easily Adaptable On‐Chip Debug Architecture for Multicore Processors

Nowadays, the multicore processor is watched with interest by people all over the world. As the design technology of system on chip has developed, observing and controlling the processor core's internal state has not been easy. Therefore, multicore processor debugging is very difficult and time‐consuming. Thus, we need a reliable and efficient debugger to find the bugs. In this paper, we propose an on‐chip debug architecture for multicore processors that is easily adaptable and flexible. It is based on the JTAG standard and supports monitoring mode debugging, which is different from run‐stop mode debugging. Compared with the debug architecture that supports the run‐stop mode debugging, the proposed architecture is easily applied to a debugger and has the advantage of having a desirable gate count and execution cycle. To verify the on‐chip debug architecture, it is applied to the debugger of the prototype multicore processor and is tested by interconnecting it with a software debugger based on GDB and configured for the target processor.     

一种SoC片上调试与可测性的整合设计

随着SoC的复杂度和规模的不断增长,SoC的片上调试与可测性变得越来越困难和重要。片上调试与可测性都是系统芯片设计的重要组成部分。文章针对某款32位SoC,充分利用CPU核原有的调试结构,提出一种可测试系统与调试系统的一体化结构设计,并针对不同的模块利用不同的测试策略。基于JTAG端口,该结构能够进行系统程序的调试、边界扫描的测试、扫描链的测试、嵌入式SRAM的内建自测试,同时有效地降低了电路逻辑规模,实现了在测试覆盖率和测试代价之间的一个有效折衷。     

Debug Facilities in the TriMedia CPU64 Architecture

This paper describes debug facilities in the Philips TriMedia CPU64, which is an embedded processor core for multimedia applications. Its architecture provides a VLIW pipeline, support for 64-bit vector data, and virtual memory management. The debug hardware in the TriMedia CPU64 supports two complementary debug strategies. One strategy provides a snapshot of the processor state at certain moments in time, which is achieved by single-step execution and various breakpoint types. The other debug strategy provides continuous monitoring of the processor state by using a PC trace buffer. Precise exceptions are used to provide accurate context switching from application software to debugger software.     

面向电子控制器的片上可调试性结构设计

提出一种满足电子控制器高可靠要求的片上调试结构。通过复用JTAG接口,可以消除冗余引脚带来的成本和体积开销,同时基于TAP控制器而设计的自定义指令,使得JTAG链路实现结构测试和功能调试的融合;针对调试命令与总线访问的协议转换需求,设计一种低开销与高效率的串并转换单元,配合外围的调试软件和协议转换器,实现全局地址空间的调试访问。实验结果表明,设计的调试结构使得调试时间平均缩短79.8%,面积开销下降16.73%,同时显著提高了调试链路的可靠性。     

基于多DSP系统的交叉调试系统的设计和实现

本文介绍了一种由多个DSP构建的并行处理系统,探讨了多DSP系统中实现交叉调试的方法,详细讨论了调试器和目标机调试的具体内容,给出了调试模式下的程序下载方式。实际应用显示,该交叉调试系统能够有效满足多DSP系统的调试需求,拥有较好的多处理器支持性能和较高的性价比。     

SoC中视频解码模块的测试系统

介绍了一种SoC中视频模块在初调阶段的测试方法,主要的思路是将视频模块的数据从调试接口引出,送入FPGA板中, FPGA将其编码成符合ITU-R BT.656标准的SDI信号,送入外部显示设备.这种测试方法能够很好地排除SoC中其他后端处理模块的干扰,从而获得较好的调试效果.本设计在多个SoC项目中应用,经实际检验表明,系统稳定效果良好.     

一种双核SoC调试系统的设计与验证

调试系统的设计和验证是多核SoC设计中的重要环节。基于某双核SoC的设计,提出一个片上硬件调试构架,利用FPGA构建该调试系统的硬件验证平台。双核SoC调试系统验证平台利用System Verilog DPI,将RealView调试器、Keil C51及目标芯片的验证testbench集成在一起,实现了双核SoC调试系统的RTL级调试验证。利用该平台,在RTL仿真验证阶段可方便地对ARM和8051核构成的双核SoC进行调试,解决仿真中出现的问题,从而有效缩短设计周期,并提高验证效率。该双核SoC调试系统验证平台的实现对其他系统芯片设计具有一定的参考价值。     

可重用片上仿真调试协议结构

提出了一种可重用片上仿真调试协议结构,基于此结构设计实现的片上仿真调试逻辑,简单高效,便于重用于新的芯片和新的体系结构.     

线阵CCD相机模拟器的分析与设计

为降低某线阵CCD相机因屡次调试而被损坏的风险,对相机的特性和时序进行了分析,设计了一种基于现场可编程门阵列(FPGA)的CCD相机模拟器.整个系统以FPGA作为核心器件,在FPGA内部开辟一片ROM,里面存放一幅标准图像的灰度值,在像素时钟的下降沿输出灰度值,并对像素时钟进行计数,产生外加行同步信号和行有效信号.仿真结果显示,此线阵CCD相机模拟器模拟过程符合实际相机的输出时序要求.模拟器的设计缩短了工程上的调试时间,为后期的采集和存储等处理提供了保证.     

振弦式传感器智能调试系统的设计与实现

设计一个智能调试系统,该系统主要由带机械手的调试台、示渡器、激励电路、检测电路、控制电路、显示电路和MCU等要素组成。试验结果表明,系统运行正确,可缩短调试时间,提高产品质量,具有较高的实用价值。     

基于C30的嵌入式计算机自主调试环境的建立和软件设计

文章介绍自主研制基于ＴＭＳ３２０Ｃ３０的嵌入式计算机调试环境的建立和软件设计，该方法特别适用于结构复杂，功能强及可靠性要求高的嵌入式系统，可提高工作效率，节省试验费用。     

针对ARM SoC的Angel调试监控器实现与移植

本文阐述利用Angel目标监控程序构建一个有效而低成本的嵌入式系统调试方案，提高自主开发Garfield SoC系统方案的竞争力。首先从Angel原理入手。介绍调试系统的宿主机和Angel之间的ADP通信协议以及利用开源调试器GDB建立调试环境的方法。然后以软件断点为例剖析了Angel调试的具体实现，并且阐述将Angel移植到自主设计的SoC上的过程。此方法已成功应用于Garfield SoC平台。     

电子装备调试过程可靠性管理若干问题探讨

分析了电子装备调试试验与可靠性的关系,提出了对电子装备调试过程实施管理的工作要点和实施程序。总结了行之有效的管理方法。     

跨时钟域信号的几种同步方法研究

为使跨时钟域信号能够被目标时钟正确采集,提出并总结了几种同步方法,详尽论述了这些方法所涉及的存储器计算和synthesis设置。跨时钟域信号的同步方法应根据源时钟与目标时钟的相位关系、该信号的时间宽度和多个跨时钟域信号之间的时序关系来选择。如果两时钟有确定的相位关系,可由目标时钟直接采集跨时钟域信号,且在synthesis中应设此两时钟为同步关系;否则,需要借助FIFO(First in,First out),在synthesis时,此两时钟必须设为false path关系。跨时钟域信号的宽度至少应为目标时钟周期的两倍。对于彼此有确定时序关系的多个跨时钟域信号,在同步前应使其保持足够距离。所述方法在CMOS(Complementary Metal Oxide Semiconductor)图像传感器的设计中被实际应用。经仿真和芯片的系统验证,该图像传感器可以正确完成信号在各时钟间的同步,并以60帧/s的速率正确输出分辨率为1 280×720的数据。     

基于串口的高速SerDes高效调试方法研究

随着高速串并收发器(SerDes)传输速率的飞速提升,随之而来的是高速SerDes功能性能参数复杂度的提升,因此针对高速SerDes的高效调试方法成为国内外研究的重要课题.在分析和评价现有测试方法的基础上,提出了一种基于串口的高速SerDes调试方案,设计了相应的串口协议,实现了SerDes参数的动态调试.相比于传统S...     

Design of a single-chip digital lattice equalizer filter

One lattice equalizer stage is designed on a single chip using 4-/spl mu/m NMOS technology. All the arithmetic operations of the chip are performed bit-serially under the control of a global two-phase clock, and they are totally pipelined. The data are represented as 16-bit two's complement fixed-point numbers. A built-in test scheme allows the offline testing of the chip with high fault coverage at a minimal hardware overhead. Direct coupling between chips permits the realization of filters of higher order. In addition, the structure of the lattice equalizer permits the use of the same chip in linear prediction problems. SPICE simulation results and fabrication of the major blocks in the design demonstrated that operating clock frequencies of up to 8 MHz are possible. At the maximum estimated operating clock frequency, the chip can accommodate applications with data rates of up to 500 kHz.     

A multigigahertz clocking scheme for the Pentium(R) 4microprocessor

Core and I/O clock design for the Pentium(R) 4 microprocessor is described. Two phase-locked loops generate core and I/O clocks supporting concurrent multiple frequencies. A clock distribution network with skew optimization and jitter reduction is designed to achieve low clock inaccuracies for processors at frequencies ⩾2 GHz for the core and ⩾4 GHz for the rapid execution engine. A global medium clock frequency is distributed. Local clock drivers generate pulsed or regular (nonpulsed) clocks at fast, medium, and slow frequencies. A 3.2-GB/s system bus is achieved using a dedicated I/O phase-locked loop with glitch protection and detection. Silicon speed path tools and clock debug features are designed to enable a short debug cycle