A CCD color signal separation IC for single-chip color imagers

A CCD color signal separation IC for solid-state imagers with color filter arrays is described. The device simplifies peripheral circuitry and enhances picture qualities such as resolution, color fidelity, and stability for single-chip color imaging systems, by incorporating CCD delay lines, sample-and-hold circuits, and dual clamp circuit. Also described is a new geometry color filter array which is required by the separation IC. Color image corresponding to horizontal resolution of 340 TV lines with no erroneous color has been obtained from the device when used with a 580 × 475 element CCD imager.     

An integrated optical channel waveguide-CCD transversal filter

Operation of an integrated optical channel waveguide array-CCD transversal filter is reported. Channel waveguides formed in V-grooves couple directly to the sensor elements of the four phase, double polysilicon CCD. Experimental results include a CCD transfer inefficiency of 1.0 × 10^-4and a filter transfer function having good agreement with theoretical results.     

High-resolution CCD image sensors with reduced smear

Two types of interline transfer CCD image sensors with reduced smear signal were developed, one for a 525-line TV system (EIA) and one for a 625-line system (CCIR). An MOS diode is employed as a sensing element to realize negligibly small lag compared with that of a junction diode. The EIA and CCIR version have effective number of pixels of 510 × 492 and 500 × 582, respectively. Smear is reduced down to -92 dB by fabricating the vertical shift register on the p-well. In spite of the shrunken element area, the blue sensitivity similar to that for a conventional 384 × 491 CCD imager [1] is obtained by optimization of the film thickness on the diode. Resolution as high as 330 TV lines in color is also attained.     

Some general experimental studies on charge-coupled device circuits†

The first part, of the paper includes the derivation of a lump model for the basic CCD unit. This model consists of two capacitors, a current generator and a switch. Experimental results are given for the justification of this model.

In the second part of the paper a report is given on the successful operation of silicon gate CCD shift registers, two-phase and three-phase.

The last part presents photosensitivity results of CCD silicon gate shift registers operated as imaging arrays. The noise equivalent power (NEP) was 2 × 10^?8 W/cm² at a wavelength of 0·7 μm. Relative output as a function of integration time is also given.     

清晰热成象红外双色肖特基势垒CCD图象传感器

用控制肖特基光电二极管阵列势垒高度的方法，研制出象素包含低和高势垒高度二极管的红外双色肖特基ＣＣＤ图象传感器。研制的６４８（Ｈ）×４８８（Ｖ）红外双色ＣＣＤ图象传感器转移效率高达９９．７４％，解决了常规单色红外ＣＣＤ图象传感器探测灰色物体温度的错误，获得清晰的热成象。     

Operation and characteristics of a CLIP imager

An interline-transfer CCD imager with 580 × 475 elements for the ⅔-in optical format is described. The imager employs the clock-line-isolated photodiode (CLIP) structure that eliminates the field oxide and the field ion implant by exploiting the clock lines which so far have been placed only to carry the driving pulses. In spite of the elimination of such channel stops, it can operate not only in a frame integration mode but in a field integration mode. A saturation current of 170 nA and a horizontal resolution of 340 TV lines were obtained in both the modes. The vertical resolution was 570 TV lines in the frame-integration mode, while over 400 TV lines in the field-integration mode.     

A frame-transfer CCD color imager with vertical antiblooming

A high-density 604 (H)× 576 (V) frame-transfer CCD color image sensor is realized with a pixel dimension of 10.0 (H) × 15.6 (V) µm², an image diagonal of 7.5 mm, and a total chip area of 66 mm². On-chip color filters and the use of a triple read-out register result in separate Cy, G, and Ye output signals. The imager is an n-p-n buried-channel CCD which can handle 125 times overexposure with vertical antiblooming. For the calculation of a suitable dopant distribution in the image, storage, and output sections, a four-step procedure has been developed. This procedure has proved to be successful and is much faster than an approach based exclusively on two-dimensional potential calculations.     

一种单片集成有源开关滤波器组设计

集成化发展趋势是射频系统的重要发展趋势之一,其中,有源开关与无源滤波器组的组合是射频集成宽带系统的常用电路单元之一。由于二者采用了不同的制造工艺,其加工工艺与材料组成均不同。因此,将二者高密度集成时须借助于其他介质。文中根据集成无源器件技术和高密度封装技术的发展进度,完成了一种S波段的有源开关带通滤波器组的研制,产品尺寸为7.0 mm×5.5 mm×1.14 mm,且内集成隔直电容和电源去耦电容,在实现了小型化、轻量化的同时,其工程应用将十分便利。     

A very small "Super-8" format CCD imager for single-chip color camera

A "Super-8" format CCD single-chip color imager has been developed. The imager maintains high performance comparable to the conventional ⅔-in image sensors. This has been realized by using low noise and wide dynamic range designs, and monolithic complementary color filter.     

Color Imaging System Using a Single CCD Area Array

A color imaging system employing a single CCD sensor with a color filter array has been implemented. The system incorporates color channel enhancement and interpolation and provides display on a conventional color video monitor. Color correction matrix coefficients are computed. The response of the system is compared to that of a photographic film.     

Color imaging system using a single CCD area array

A color imaging system employing a single CCD sensor with a color filter array has been implemented. The system incorporates color channel enhancement and interpolation and provides display on a conventional color video monitor. Color correction matrix coefficients are computed. The response of the system is compared to that of a photographic film.     

A CCD color signal separation IC for single-chip color imagers

A CCD color signal separation IC for solid-state imagers with color filter arrays is described. The device simplifies peripheral circuitry and enhances picture qualities such as resolution, color fidelity, and stability for single-chip color imaging systems by incorporating CCD delay lines, sample-and-hold circuits, and dual clamp circuit. Also described is a color filter array utilizing Bayer geometry, which is used in the separation IC. Color images corresponding to a horizontal resolution of 340 TV lines with no erroneous color have been obtained from the device when used with a 580/spl times/475 element CCD imager.     

Hybrid IRCCD imaging array

A hybrid IRCCD for high background application has been successfully fabricated. The device consists of fifty Hg0.7Cd0.3Te detector diodes of 50-µm × 50-µm sensitive areas and a silicon CCD maltiplexer with input circuits on 40-µm centers having bucket background subtraction and blooming protection circuits. The noise-equivalent power (NEP) of the IRCCD is 5 × 10^-14W-Hz^-1/2at background photon flux level of 4 × 10¹⁵photons . cm^-2s^-1, integration time of 2 × 10^-5s, and clock frequency of 3 × 10⁶Hz. The noise source of the detector diodes limits the IRCCD performance. The IRCCD is also evaluated with the real-time raster-scanned thermal images displayed on a CRT monitor. Two-dimensional images are generated by using a scanning mirror. A fixed-pattern noise is reduced by comparison of an object video to the reference video stored in a memory. A noise-equivalent temperature difference of the system is 0.6°C at a frame rate of 30 Hz. Instantaneous field of view is 1 mrad × 1 mrad and the field of view of the system is 12° × 5.7°.     

Color reproduction of a single chip color camera with a frame transfer CCD

A single chip color camera of phase separation type employing a 512 V/spl times/486 H element frame transfer CCD with a high color fidelity has been fabricated. The horizontal color crosstalk is successfully suppressed by using a color stripe filter array in which optically opaque stripes are vertically aligned on the channel stop regions of the CCD.     

High-resolution 8-mm CCD image sensor with correlated clamp sample and hold charge detection circuit

This paper describes the performance of an optimally designed virtual-phase frame-transfer CCD image sensor having 774H × 488V elements and an 8-mm diagonal for the image-sensing area. The sensor employs electron-hole recombination antiblooming and achieves high performance by both maximizing the well capacity and reducing the reset noise using an on-chip correlated clamp sample and hold signal processing technique. The imager conforms to the NTSC standard and is intended for color camera applications. The details described include processing modifications, circuit optimization for maximum signal-to-noise performance, and various layout illustrations with emphasis on the design of the three serial registers that multiplex the signals into the three individual outputs. The minimal driving requirements characteristic of the virtual-phase CCD device have been preserved by interconnecting the serial registers with the gates of signal-processing transistors and by applying timing pulses that clock the registers as well as provide the appropriate signal-processing functions. Discussions presented in the paper are focused on comparisons of theoretical predictions of maximum attainable performance with measured results.     

A 1/2-in. CCD image sensor overlaid with a hydrogenated amorphous silicon

A half-inch size CCD image sensor overlaid with a hydrogen-erated amorphous silicon (α-Si:H) as a photodetector has been developed. The array consists of 506V × 404H picture elements. The glow-discharged α-Si:H film has high quantum efficiency of 0.75-0.8 in the visible wavelength range and low dark current of 0.2 nA/cm²and is formed on the CCD scanner with vertical overflow drain. This CCD image sensor has a sensitivity of 0.014 µA/lx (3200 K)and a S/N ratio of 73 and 68 dB for fixed-pattern noise and random noise, respectively. Smearing signal is suppressed to below 5 percent at incident light intensity of 1000 times saturation exposure. The blooming and highlight lag are completely suppressed by the vertical overflow drain structure.     

应用光学自由曲面的曲面结构大视场仿生复眼系统

受限于制造技术,大多数仿生复眼的传感器为平 面结构,与生物复眼的曲面结构存在差异,限制了其成像质量和视场 扩展。本文设计制造了一个模拟生物复眼结构的大视场仿生复眼,将16mm CCD传感器组成2×8的曲面阵列,并 设计制造了配套的单层结构的曲面2×8透镜阵列,各透镜与传感器成 一一垂直对应关系,贴合了生物复眼的结构特征,消除 了传统复眼的离轴像差。通过引入光学自由曲面和非球面,保证了单层结构透镜阵列的成像 质量,单层透镜阵列降低了系统 的制造及装配难度。系统实现了180°×75°视场范围内无盲区的图 像采集。实验结果表明,与传统鱼眼镜头相比,本文系统畸变更小,分辨率更高。     

Design and Fabrication of Silcon Microlens with Low SAG for 528(H) × 528(V) Infrared Charge-Coupled Device Application

Microlens array is an important optical element to improve the photosensitivity of charge-coupled device (CCD). In this paper, a monolithic integration technology between microlens and 528 × 528 element PtSi Schottky-barrier infrared charge-coupled device (IRCCD) with a pixel size of 30μm × 30μm has been developed. The microlens array with low sag and long focal length is designed based on geometrical optics theory. It is directly formed on the back side of the substrate in IRCCD chip using successive photolithography and A⁺ ion beam etching (IBE) technology. The microlens array is characterized by both surface stylus and point spread function (PSF). The experiment results of integration device between IRCCD and microlens array indicate that the optical signal response is improved obviously and a responsivity increase by a factor of 1.8 in the operation band.     

Optimum scaling of buried-channel CCD's

The maximum charge packet size in a two-phase charge-coupled device (CCD) is limited by many constraints relating to the transfer efficiency requirement and control circuit limitations. The constraints are quantified and an optimization routine is developed for designing CCD's with maximum charge capacity per unit area under these constraints. The optimum charge capacity for scaled down CCD's is calculated and it is shown that the normal buried channel cannot be designed to have adequate charge capacity at small geometries. A novel low-voltage buried-channel structure is introduced which uses a shallow p-type surface implant to minimize surface trapping and increases the charge capacity per unit area 2.4× compared to the normal buried channel. The optimum charge packet size at ∼1-µm geometry for these CCD structures, based on these calculations, is shown to be inadequate for VLSI dynamic memory applications.     

高集成度多光谱TDI CCD焦平面系统

提出了一种高集成度TDI CCD焦平面系统,成功应用TDI CCD驱动单元厚膜集成模块完成了具有16路CCD信号输出、像元读出频率20 MHz的高集成度高速多光谱TDI CCD焦平面系统的研制。通过采用双通道CCD信号处理模拟前端、厚膜集成驱动单元模块、高速LVDS图像数据传输接口以及机、电、热一体化仿真设计方法,极大提高了TDI CCD焦平面系统的集成度,降低了系统互连的复杂程度。系统共有4路图像数据传输接口,单路传输能力达到1.6~2.5 Gbps,最高可实现10 Gbps的图像数据带宽,在保证高数据率的同时,提高了数据传输的抗干扰能力。阐述了系统设计方案及多光谱TDI CCD探测器工作原理,并对其中的机电集成设计、驱动单元厚膜集成技术以及高速串行传输总线等关键技术进行了分析描述。通过采用TDI CCD传函测试片对系统进行了测试,焦平面全系统调制传函平均为0.511。